diff options
| author | Corbin Simpson <MostAwesomeDude@gmail.com> | 2009-10-14 13:27:10 -0700 |
|---|---|---|
| committer | Corbin Simpson <MostAwesomeDude@gmail.com> | 2009-10-14 13:27:10 -0700 |
| commit | cba8fafaffc2c6a86c543730c707f3c58a39d0b7 (patch) | |
| tree | 6d57291b6f78cfe00f4fa89769e6edeb43b46872 | |
| parent | b48d455bae68432ecfd29eeefd9723c42352d22c (diff) | |
Indent r300reg.xml.
Prettify.
| -rw-r--r-- | r300reg.xml | 21045 | ||||
| -rwxr-xr-x | radeonreg.py | 2 |
2 files changed, 10749 insertions, 10298 deletions
diff --git a/r300reg.xml b/r300reg.xml index 62fe6da..13d2da4 100644 --- a/r300reg.xml +++ b/r300reg.xml @@ -2,7 +2,7 @@ <!-- This file was automatically generated from radeonreg.py. -I strongly suggest running "tidy -m -xml 'name_of_file.xml'" on this file +I strongly suggest running "tidy -i -m -xml 'name_of_file.xml'" on this file before attempting to read it. ~ C. @@ -10,10300 +10,10751 @@ before attempting to read it. <database xmlns="http://nouveau.freedesktop.org/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="rules-ng.xsd"> -<domain name="R300" /> -<enum name="ENUM0"> -<value name="NORMAL_OPERATION" value="0"> -<doc>Normal operation.</doc> -</value> -<value name="RESOLVE_OPERATION" value="1"> -<doc>Resolve operation.</doc> -</value> -</enum> -<enum name="ENUM1"> -<value name="1" value="0"> -<doc>1.0</doc> -</value> -<value name="2" value="1"> -<doc>2.2</doc> -</value> -</enum> -<enum name="ENUM2"> -<value name="ADD_AND_CLAMP" value="0"> -<doc>Add and Clamp</doc> -</value> -<value name="ADD_BUT_NO_CLAMP" value="1"> -<doc>Add but no Clamp</doc> -</value> -<value name="SUBTRACT_DST_FROM_SRC" value="2"> -<doc>Subtract Dst from Src, and Clamp</doc> -</value> -<value name="SUBTRACT_DST_FROM_SRC" value="3"> -<doc>Subtract Dst from Src, and don`t Clamp</doc> -</value> -<value name="MINIMUM_OF_SRC" value="4"> -<doc>Minimum of Src, Dst (the src and dst blend functions are -forced to D3D_ONE)</doc> -</value> -<value name="MAXIMUM_OF_SRC" value="5"> -<doc>Maximum of Src, Dst (the src and dst blend functions are -forced to D3D_ONE)</doc> -</value> -<value name="SUBTRACT_SRC_FROM_DST" value="6"> -<doc>Subtract Src from Dst, and Clamp</doc> -</value> -<value name="SUBTRACT_SRC_FROM_DST" value="7"> -<doc>Subtract Src from Dst, and don`t Clamp</doc> -</value> -</enum> -<enum name="ENUM3"> -<value name="D3D_ZERO" value="1"> -<doc>D3D_ZERO</doc> -</value> -<value name="D3D_ONE" value="2"> -<doc>D3D_ONE</doc> -</value> -<value name="D3D_SRCCOLOR" value="3"> -<doc>D3D_SRCCOLOR</doc> -</value> -<value name="D3D_INVSRCCOLOR" value="4"> -<doc>D3D_INVSRCCOLOR</doc> -</value> -<value name="D3D_SRCALPHA" value="5"> -<doc>D3D_SRCALPHA</doc> -</value> -<value name="D3D_INVSRCALPHA" value="6"> -<doc>D3D_INVSRCALPHA</doc> -</value> -<value name="D3D_DESTALPHA" value="7"> -<doc>D3D_DESTALPHA</doc> -</value> -<value name="D3D_INVDESTALPHA" value="8"> -<doc>D3D_INVDESTALPHA</doc> -</value> -<value name="D3D_DESTCOLOR" value="9"> -<doc>D3D_DESTCOLOR</doc> -</value> -<value name="D3D_INVDESTCOLOR" value="10"> -<doc>D3D_INVDESTCOLOR</doc> -</value> -<value name="D3D_SRCALPHASAT" value="11"> -<doc>D3D_SRCALPHASAT</doc> -</value> -<value name="D3D_BOTHSRCALPHA" value="12"> -<doc>D3D_BOTHSRCALPHA</doc> -</value> -<value name="D3D_BOTHINVSRCALPHA" value="13"> -<doc>D3D_BOTHINVSRCALPHA</doc> -</value> -<value name="GL_ZERO" value="32"> -<doc>GL_ZERO</doc> -</value> -<value name="GL_ONE" value="33"> -<doc>GL_ONE</doc> -</value> -<value name="GL_SRC_COLOR" value="34"> -<doc>GL_SRC_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_SRC_COLOR" value="35"> -<doc>GL_ONE_MINUS_SRC_COLOR</doc> -</value> -<value name="GL_DST_COLOR" value="36"> -<doc>GL_DST_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_DST_COLOR" value="37"> -<doc>GL_ONE_MINUS_DST_COLOR</doc> -</value> -<value name="GL_SRC_ALPHA" value="38"> -<doc>GL_SRC_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_SRC_ALPHA" value="39"> -<doc>GL_ONE_MINUS_SRC_ALPHA</doc> -</value> -<value name="GL_DST_ALPHA" value="40"> -<doc>GL_DST_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_DST_ALPHA" value="41"> -<doc>GL_ONE_MINUS_DST_ALPHA</doc> -</value> -<value name="GL_SRC_ALPHA_SATURATE" value="42"> -<doc>GL_SRC_ALPHA_SATURATE</doc> -</value> -<value name="GL_CONSTANT_COLOR" value="43"> -<doc>GL_CONSTANT_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_CONSTANT_COLOR" value="44"> -<doc>GL_ONE_MINUS_CONSTANT_COLOR</doc> -</value> -<value name="GL_CONSTANT_ALPHA" value="45"> -<doc>GL_CONSTANT_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_CONSTANT_ALPHA" value="46"> -<doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc> -</value> -</enum> -<enum name="ENUM4"> -<value name="D3D_ZERO" value="1"> -<doc>D3D_ZERO</doc> -</value> -<value name="D3D_ONE" value="2"> -<doc>D3D_ONE</doc> -</value> -<value name="D3D_SRCCOLOR" value="3"> -<doc>D3D_SRCCOLOR</doc> -</value> -<value name="D3D_INVSRCCOLOR" value="4"> -<doc>D3D_INVSRCCOLOR</doc> -</value> -<value name="D3D_SRCALPHA" value="5"> -<doc>D3D_SRCALPHA</doc> -</value> -<value name="D3D_INVSRCALPHA" value="6"> -<doc>D3D_INVSRCALPHA</doc> -</value> -<value name="D3D_DESTALPHA" value="7"> -<doc>D3D_DESTALPHA</doc> -</value> -<value name="D3D_INVDESTALPHA" value="8"> -<doc>D3D_INVDESTALPHA</doc> -</value> -<value name="D3D_DESTCOLOR" value="9"> -<doc>D3D_DESTCOLOR</doc> -</value> -<value name="D3D_INVDESTCOLOR" value="10"> -<doc>D3D_INVDESTCOLOR</doc> -</value> -<value name="GL_ZERO" value="32"> -<doc>GL_ZERO</doc> -</value> -<value name="GL_ONE" value="33"> -<doc>GL_ONE</doc> -</value> -<value name="GL_SRC_COLOR" value="34"> -<doc>GL_SRC_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_SRC_COLOR" value="35"> -<doc>GL_ONE_MINUS_SRC_COLOR</doc> -</value> -<value name="GL_DST_COLOR" value="36"> -<doc>GL_DST_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_DST_COLOR" value="37"> -<doc>GL_ONE_MINUS_DST_COLOR</doc> -</value> -<value name="GL_SRC_ALPHA" value="38"> -<doc>GL_SRC_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_SRC_ALPHA" value="39"> -<doc>GL_ONE_MINUS_SRC_ALPHA</doc> -</value> -<value name="GL_DST_ALPHA" value="40"> -<doc>GL_DST_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_DST_ALPHA" value="41"> -<doc>GL_ONE_MINUS_DST_ALPHA</doc> -</value> -<value name="GL_CONSTANT_COLOR" value="43"> -<doc>GL_CONSTANT_COLOR</doc> -</value> -<value name="GL_ONE_MINUS_CONSTANT_COLOR" value="44"> -<doc>GL_ONE_MINUS_CONSTANT_COLOR</doc> -</value> -<value name="GL_CONSTANT_ALPHA" value="45"> -<doc>GL_CONSTANT_ALPHA</doc> -</value> -<value name="GL_ONE_MINUS_CONSTANT_ALPHA" value="46"> -<doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc> -</value> -</enum> -<enum name="ENUM5"> -<value name="DISABLE" value="0"> -<doc>Disable</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</enum> -<enum name="ENUM6"> -<value name="DISABLED" value="0"> -<doc>Disabled (Use RB3D_BLENDCNTL)</doc> -</value> -<value name="ENABLED" value="1"> -<doc>Enabled (Use RB3D_ABLENDCNTL)</doc> -</value> -</enum> -<enum name="ENUM7"> -<value name="DISABLE_READS" value="0"> -<doc>Disable reads</doc> -</value> -<value name="ENABLE_READS" value="1"> -<doc>Enable reads</doc> -</value> -</enum> -<enum name="ENUM9"> -<value name="1_BUFFER" value="0"> -<doc>1 buffer. This is the only mode where the cb processes the end -of packet command.</doc> -</value> -<value name="2_BUFFERS" value="1"> -<doc>2 buffers</doc> -</value> -<value name="3_BUFFERS" value="2"> -<doc>3 buffers</doc> -</value> -<value name="4_BUFFERS" value="3"> -<doc>4 buffers</doc> -</value> -</enum> -<enum name="ENUM10"> -<value name="DISABLE_COLOR_COMPARE" value="0"> -<doc>Disable color compare.</doc> -</value> -<value name="ENABLE_COLOR_COMPARE" value="1"> -<doc>Enable color compare.</doc> -</value> -</enum> -<enum name="ENUM11"> -<value name="DISABLE_AA_COMPRESSION" value="0"> -<doc>Disable AA compression</doc> -</value> -<value name="ENABLE_AA_COMPRESSION" value="1"> -<doc>Enable AA compression</doc> -</value> -</enum> -<enum name="ENUM12"> -<value name="3D_DESTINATION_IS_NOT_MACROTILED" value="0"> -<doc>3D destination is not macrotiled</doc> -</value> -<value name="3D_DESTINATION_IS_MACROTILED" value="1"> -<doc>3D destination is macrotiled</doc> -</value> -</enum> -<enum name="ENUM13"> -<value name="3D_DESTINATION_IS_NO_MICROTILED" value="0"> -<doc>3D destination is no microtiled</doc> -</value> -<value name="3D_DESTINATION_IS_MICROTILED" value="1"> -<doc>3D destination is microtiled</doc> -</value> -<value name="3D_DESTINATION_IS_SQUARE_MICROTILED" value="2"> -<doc>3D destination is square microtiled. Only available in -16-bit</doc> -</value> -</enum> -<enum name="ENUM14"> -<value name="NO_SWAP" value="0"> -<doc>No swap</doc> -</value> -<value name="WORD_SWAP" value="1"> -<doc>Word swap (2 bytes in 16-bit)</doc> -</value> -<value name="DWORD_SWAP" value="2"> -<doc>Dword swap (4 bytes in a 32-bit)</doc> -</value> -<value name="HALF" value="3"> -<doc>Half-Dword swap (2 16-bit in a 32-bit)</doc> -</value> -</enum> -<enum name="ENUM16"> -<value name="DISABLE" value="0"> -<doc>disable</doc> -</value> -<value name="ENABLE" value="1"> -<doc>enable</doc> -</value> -</enum> -<enum name="ENUM17"> -<value name="TRUNCATE" value="0"> -<doc>Truncate</doc> -</value> -<value name="ROUND" value="1"> -<doc>Round</doc> -</value> -<value name="LUT_DITHER" value="2"> -<doc>LUT dither</doc> -</value> -</enum> -<enum name="ENUM22"> -<value name="AF_NEVER" value="0"> -<doc>AF_NEVER</doc> -</value> -<value name="AF_LESS" value="1"> -<doc>AF_LESS</doc> -</value> -<value name="AF_EQUAL" value="2"> -<doc>AF_EQUAL</doc> -</value> -<value name="AF_LE" value="3"> -<doc>AF_LE</doc> -</value> -<value name="AF_GREATER" value="4"> -<doc>AF_GREATER</doc> -</value> -<value name="AF_NOTEQUAL" value="5"> -<doc>AF_NOTEQUAL</doc> -</value> -<value name="AF_GE" value="6"> -<doc>AF_GE</doc> -</value> -<value name="AF_ALWAYS" value="7"> -<doc>AF_ALWAYS</doc> -</value> -</enum> -<enum name="ENUM23"> -<value name="DISABLE_ALPHA_FUNCTION" value="0"> -<doc>Disable alpha function.</doc> -</value> -<value name="ENABLE_ALPHA_FUNCTION" value="1"> -<doc>Enable alpha function.</doc> -</value> -</enum> -<enum name="ENUM24"> -<value name="DISABLE_ALPHA_TO_MASK_FUNCTION" value="0"> -<doc>Disable alpha to mask function.</doc> -</value> -<value name="ENABLE_ALPHA_TO_MASK_FUNCTION" value="1"> -<doc>Enable alpha to mask function.</doc> -</value> -</enum> -<enum name="ENUM25"> -<value name="2" value="0"> -<doc>2/4 sub-pixel samples.</doc> -</value> -<value name="3" value="1"> -<doc>3/6 sub-pixel samples.</doc> -</value> -</enum> -<enum name="ENUM26"> -<value name="DISABLE_DITHERING" value="0"> -<doc>Disable Dithering</doc> -</value> -<value name="ENABLE_DITHERING" value="1"> -<doc>Enable Dithering.</doc> -</value> -</enum> -<enum name="ENUM30"> -<value name="SOLID_FILL_COLOR" value="0"> -<doc>Solid fill color</doc> -</value> -<value name="FLAT_SHADING" value="1"> -<doc>Flat shading</doc> -</value> -<value name="GOURAUD_SHADING" value="2"> -<doc>Gouraud shading</doc> -</value> -</enum> -<enum name="ENUM32"> -<value name="NO_EFFECT" value="0"> -<doc>No effect.</doc> -</value> -<value name="PREVENTS_TCL_INTERFACE_FROM_DEADLOCKING_ON_GA_SIDE" -value="1"> -<doc>Prevents TCL interface from deadlocking on GA side.</doc> -</value> -</enum> -<enum name="ENUM33"> -<value name="NO_EFFECT" value="0"> -<doc>No effect.</doc> -</value> -<value name="ENABLES_HIGH" value="1"> -<doc>Enables high-performance register/primitive switching.</doc> -</value> -</enum> -<enum name="ENUM34"> -<value name="HORIZONTAL" value="0"> -<doc>Horizontal</doc> -</value> -<value name="VERTICAL" value="1"> -<doc>Vertical</doc> -</value> -<value name="SQUARE" value="2"> -<doc>Square (horizontal or vertical depending upon slope)</doc> -</value> -<value name="COMPUTED" value="3"> -<doc>Computed (perpendicular to slope)</doc> -</value> -</enum> -<enum name="ENUM37"> -<value name="DRAW_POINTS" value="0"> -<doc>Draw points.</doc> -</value> -<value name="DRAW_LINES" value="1"> -<doc>Draw lines.</doc> -</value> -<value name="DRAW_TRIANGLES" value="2"> -<doc>Draw triangles.</doc> -</value> -<value name="7" value="3"> -<doc>7.</doc> -</value> -</enum> -<enum name="ENUM38"> -<value name="ROUND_TO_TRUNC" value="0"> -<doc>Round to trunc</doc> -</value> -<value name="ROUND_TO_NEAREST" value="1"> -<doc>Round to nearest</doc> -</value> -</enum> -<enum name="ENUM43"> -<value name="DISABLE_POINT_TEXTURE_STUFFING" value="0"> -<doc>Disable point texture stuffing.</doc> -</value> -<value name="ENABLE_POINT_TEXTURE_STUFFING" value="1"> -<doc>Enable point texture stuffing.</doc> -</value> -</enum> -<enum name="ENUM44"> -<value name="DISABLE_LINE_TEXTURE_STUFFING" value="0"> -<doc>Disable line texture stuffing.</doc> -</value> -<value name="ENABLE_LINE_TEXTURE_STUFFING" value="1"> -<doc>Enable line texture stuffing.</doc> -</value> -</enum> -<enum name="ENUM45"> -<value name="DISABLE_TRIANGLE_TEXTURE_STUFFING" value="0"> -<doc>Disable triangle texture stuffing.</doc> -</value> -<value name="ENABLE_TRIANGLE_TEXTURE_STUFFING" value="1"> -<doc>Enable triangle texture stuffing.</doc> -</value> -</enum> -<enum name="ENUM46"> -<value name="DISABLE_STENCIL_AUTO_INC" value="0"> -<doc>Disable stencil auto inc/dec (def).</doc> -</value> -<value name="ENABLE_STENCIL_AUTO_INC" value="1"> -<doc>Enable stencil auto inc/dec based on triangle cw/ccw, force -into dzy low bit.</doc> -</value> -<value name="FORCE_0_INTO_DZY_LOW_BIT" value="2"> -<doc>Force 0 into dzy low bit.</doc> -</value> -</enum> -<enum name="ENUM55"> -<value name="32_WORDS" value="0"> -<doc>32 words</doc> -</value> -<value name="64_WORDS" value="1"> -<doc>64 words</doc> -</value> -<value name="128_WORDS" value="2"> -<doc>128 words</doc> -</value> -<value name="256_WORDS" value="3"> -<doc>256 words</doc> -</value> -</enum> -<enum name="ENUM56"> -<value name="16_WORDS" value="0"> -<doc>16 words</doc> -</value> -<value name="32_WORDS" value="1"> -<doc>32 words</doc> -</value> -<value name="64_WORDS" value="2"> -<doc>64 words</doc> -</value> -<value name="128_WORDS" value="3"> -<doc>128 words</doc> -</value> -</enum> -<enum name="ENUM57"> -<value name="64_WORDS" value="0"> -<doc>64 words</doc> -</value> -<value name="128_WORDS" value="1"> -<doc>128 words</doc> -</value> -<value name="256_WORDS" value="2"> -<doc>256 words</doc> -</value> -<value name="512_WORDS" value="3"> -<doc>512 words</doc> -</value> -</enum> -<enum name="ENUM58"> -<value name="0_WORDS" value="0"> -<doc>0 words</doc> -</value> -<value name="4_WORDS" value="1"> -<doc>4 words</doc> -</value> -<value name="8_WORDS" value="2"> -<doc>8 words</doc> -</value> -<value name="12_WORDS" value="3"> -<doc>12 words</doc> -</value> -</enum> -<enum name="ENUM59"> -<value name="SELECT_C0A" value="0"> -<doc>Select C0A</doc> -</value> -<value name="SELECT_C1A" value="1"> -<doc>Select C1A</doc> -</value> -<value name="SELECT_C2A" value="2"> -<doc>Select C2A</doc> -</value> -<value name="SELECT_C3A" value="3"> -<doc>Select C3A</doc> -</value> -<value name="SELECT_1" value="4"> -<doc>Select 1/(1/W)</doc> -</value> -<value name="SELECT_Z" value="5"> -<doc>Select Z</doc> -</value> -</enum> -<enum name="ENUM60"> -<value name="SELECT_Z" value="0"> -<doc>Select Z</doc> -</value> -<value name="SELECT_1" value="1"> -<doc>Select 1/(1/W)</doc> -</value> -</enum> -<enum name="ENUM61"> -<value name="SELECT" value="0"> -<doc>Select (1/W)</doc> -</value> -<value name="SELECT_1" value="1"> -<doc>Select 1.0</doc> -</value> -</enum> -<enum name="ENUM62"> -<value name="TILING_DISABLED" value="0"> -<doc>Tiling disabled.</doc> -</value> -<value name="TILING_ENABLED" value="1"> -<doc>Tiling enabled (def).</doc> -</value> -</enum> -<enum name="ENUM65"> -<value name="1X1_TILE" value="0"> -<doc>1x1 tile (one 1x1).</doc> -</value> -<value name="2_TILES" value="1"> -<doc>2 tiles (two 1x1 : ST-A,B).</doc> -</value> -<value name="4_TILES" value="2"> -<doc>4 tiles (one 2x2).</doc> -</value> -<value name="8_TILES" value="3"> -<doc>8 tiles (two 2x2 : ST-A,B).</doc> -</value> -<value name="16_TILES" value="4"> -<doc>16 tiles (one 4x4).</doc> -</value> -<value name="32_TILES" value="5"> -<doc>32 tiles (two 4x4 : ST-A,B).</doc> -</value> -<value name="64_TILES" value="6"> -<doc>64 tiles (one 8x8).</doc> -</value> -<value name="128_TILES" value="7"> -<doc>128 tiles (two 8x8 : ST-A,B).</doc> -</value> -</enum> -<enum name="ENUM66"> -<value name="ST" value="0"> -<doc>ST-A tile.</doc> -</value> -<value name="ST" value="1"> -<doc>ST-B tile.</doc> -</value> -</enum> -<enum name="ENUM67"> -<value name="SELECT_1" value="0"> -<doc>Select 1/12 subpixel precision.</doc> -</value> -<value name="SELECT_1" value="1"> -<doc>Select 1/16 subpixel precision.</doc> -</value> -</enum> -<enum name="ENUM68"> -<value name="NO_WRITE" value="0"> -<doc>No write - texture coordinate not valid</doc> -</value> -<value name="WRITE" value="1"> -<doc>write - texture valid</doc> -</value> -</enum> -<enum name="ENUM70"> -<value name="SAMPLE_TEXTURE_COORDINATES_AT_REAL_PIXEL_CENTERS" -value="0"> -<doc>Sample texture coordinates at real pixel centers</doc> -</value> -<value name="SAMPLE_TEXTURE_COORDINATES_AT_ADJUSTED_PIXEL_CENTERS" -value="1"> -<doc>Sample texture coordinates at adjusted pixel centers</doc> -</value> -</enum> -<enum name="ENUM72"> -<value name="FOUR_COMPONENTS" value="0"> -<doc>Four components (R,G,B,A)</doc> -</value> -<value name="THREE_COMPONENTS" value="1"> -<doc>Three components (R,G,B,0)</doc> -</value> -<value name="THREE_COMPONENTS" value="2"> -<doc>Three components (R,G,B,1)</doc> -</value> -<value name="ONE_COMPONENT" value="4"> -<doc>One component (0,0,0,A)</doc> -</value> -<value name="ZERO_COMPONENTS" value="5"> -<doc>Zero components (0,0,0,0)</doc> -</value> -<value name="ZERO_COMPONENTS" value="6"> -<doc>Zero components (0,0,0,1)</doc> -</value> -<value name="ONE_COMPONENT" value="8"> -<doc>One component (1,1,1,A)</doc> -</value> -<value name="ZERO_COMPONENTS" value="9"> -<doc>Zero components (1,1,1,0)</doc> -</value> -<value name="ZERO_COMPONENTS" value="10"> -<doc>Zero components (1,1,1,1)</doc> -</value> -</enum> -<enum name="ENUM73"> -<value name="C" value="0"> -<doc>C</doc> -</value> -<value name="1ST_TEXTURE_COMPONENT" value="0"> -<doc>1st texture component</doc> -</value> -<value name="C" value="1"> -<doc>C</doc> -</value> -<value name="2ND_TEXTURE_COMPONENT" value="1"> -<doc>2nd texture component</doc> -</value> -<value name="C" value="2"> -<doc>C</doc> -</value> -<value name="3RD_TEXTURE_COMPONENT" value="2"> -<doc>3rd texture component</doc> -</value> -<value name="C" value="3"> -<doc>C</doc> -</value> -<value name="4TH_TEXTURE_COMPONENT" value="3"> -<doc>4th texture component</doc> -</value> -<value name="K" value="4"> -<doc>K</doc> -</value> -<value name="THE_VALUE_0" value="0"> -<doc>The value 0.0</doc> -</value> -<value name="K" value="5"> -<doc>K</doc> -</value> -<value name="THE_VALUE_1" value="1"> -<doc>The value 1.0</doc> -</value> -</enum> -<enum name="ENUM74"> -<value name="L" value="0"> -<doc>L-in,R-in,HT-in,HB-in</doc> -</value> -<value name="L" value="1"> -<doc>L-in,R-in,HT-in,HB-out</doc> -</value> -<value name="L" value="2"> -<doc>L-in,R-in,HT-out,HB-in</doc> -</value> -<value name="L" value="3"> -<doc>L-in,R-in,HT-out,HB-out</doc> -</value> -<value name="L" value="4"> -<doc>L-in,R-out,HT-in,HB-in</doc> -</value> -<value name="L" value="5"> -<doc>L-in,R-out,HT-in,HB-out</doc> -</value> -<value name="L" value="6"> -<doc>L-in,R-out,HT-out,HB-in</doc> -</value> -<value name="L" value="7"> -<doc>L-in,R-out,HT-out,HB-out</doc> -</value> -<value name="L" value="8"> -<doc>L-out,R-in,HT-in,HB-in</doc> -</value> -<value name="L" value="9"> -<doc>L-out,R-in,HT-in,HB-out</doc> -</value> -<value name="L" value="10"> -<doc>L-out,R-in,HT-out,HB-in</doc> -</value> -<value name="L" value="11"> -<doc>L-out,R-in,HT-out,HB-out</doc> -</value> -<value name="L" value="12"> -<doc>L-out,R-out,HT-in,HB-in</doc> -</value> -<value name="L" value="13"> -<doc>L-out,R-out,HT-in,HB-out</doc> -</value> -<value name="L" value="14"> -<doc>L-out,R-out,HT-out,HB-in</doc> -</value> -<value name="L" value="15"> -<doc>L-out,R-out,HT-out,HB-out</doc> -</value> -<value name="T" value="16"> -<doc>T-in,B-in,VL-in,VR-in</doc> -</value> -<value name="T" value="17"> -<doc>T-in,B-in,VL-in,VR-out</doc> -</value> -<value name="T" value="18"> -<doc>T-in,B-in,VL,VR-in</doc> -</value> -<value name="T" value="19"> -<doc>T-in,B-in,VL-out,VR-out</doc> -</value> -<value name="T" value="20"> -<doc>T-out,B-in,VL-in,VR-in</doc> -</value> -<value name="T" value="21"> -<doc>T-out,B-in,VL-in,VR-out</doc> -</value> -<value name="T" value="22"> -<doc>T-out,B-in,VL-out,VR-in</doc> -</value> -<value name="T" value="23"> -<doc>T-out,B-in,VL-out,VR-out</doc> -</value> -<value name="T" value="24"> -<doc>T-in,B-out,VL-in,VR-in</doc> -</value> -<value name="T" value="25"> -<doc>T-in,B-out,VL-in,VR-out</doc> -</value> -<value name="T" value="26"> -<doc>T-in,B-out,VL-out,VR-in</doc> -</value> -<value name="T" value="27"> -<doc>T-in,B-out,VL-out,VR-out</doc> -</value> -<value name="T" value="28"> -<doc>T-out,B-out,VL-in,VR-in</doc> -</value> -<value name="T" value="29"> -<doc>T-out,B-out,VL-in,VR-out</doc> -</value> -<value name="T" value="30"> -<doc>T-out,B-out,VL-out,VR-in</doc> -</value> -<value name="T" value="31"> -<doc>T-out,B-out,VL-out,VR-out</doc> -</value> -</enum> -<enum name="ENUM75"> -<value name="L" value="0"> -<doc>L-in,R-in,HT-in,HB-in</doc> -</value> -<value name="L" value="1"> -<doc>L-in,R-in,HT-in,HB-out</doc> -</value> -<value name="L" value="2"> -<doc>L-in,R-in,HT-out,HB-in</doc> -</value> -<value name="L" value="3"> -<doc>L-in,R-in,HT-out,HB-out</doc> -</value> -<value name="L" value="4"> -<doc>L-in,R-out,HT-in,HB-in</doc> -</value> -<value name="L" value="5"> -<doc>L-in,R-out,HT-in,HB-out</doc> -</value> -<value name="L" value="6"> -<doc>L-in,R-out,HT-out,HB-in</doc> -</value> -<value name="L" value="7"> -<doc>L-in,R-out,HT-out,HB-out</doc> -</value> -<value name="L" value="8"> -<doc>L-out,R-in,HT-in,HB-in</doc> -</value> -<value name="L" value="9"> -<doc>L-out,R-in,HT-in,HB-out</doc> -</value> -<value name="L" value="10"> -<doc>L-out,R-in,HT-out,HB-in</doc> -</value> -<value name="L" value="11"> -<doc>L-out,R-in,HT-out,HB-out</doc> -</value> -<value name="L" value="12"> -<doc>L-out,R-out,HT-in,HB-in</doc> -</value> -<value name="L" value="13"> -<doc>L-out,R-out,HT-in,HB-out</doc> -</value> -<value name="L" value="14"> -<doc>L-out,R-out,HT-out,HB-in</doc> -</value> -<value name="L" value="15"> -<doc>L-out,R-out,HT-out,HB-out</doc> -</value> -<value name="T" value="16"> -<doc>T-in,B-in,VL-in,VR-in</doc> -</value> -<value name="T" value="17"> -<doc>T-in,B-in,VL-in,VR-out</doc> -</value> -<value name="T" value="18"> -<doc>T-in,B-in,VL,VR-in</doc> -</value> -<value name="T" value="19"> -<doc>T-in,B-in,VL-out,VR-out</doc> -</value> -<value name="T" value="20"> -<doc>T-in,B-out,VL-in,VR-in</doc> -</value> -<value name="T" value="21"> -<doc>T-in,B-out,VL-in,VR-out</doc> -</value> -<value name="T" value="22"> -<doc>T-in,B-out,VL-out,VR-in</doc> -</value> -<value name="T" value="23"> -<doc>T-in,B-out,VL-out,VR-out</doc> -</value> -<value name="T" value="24"> -<doc>T-out,B-in,VL-in,VR-in</doc> -</value> -<value name="T" value="25"> -<doc>T-out,B-in,VL-in,VR-out</doc> -</value> -<value name="T" value="26"> -<doc>T-out,B-in,VL-out,VR-in</doc> -</value> -<value name="T" value="27"> -<doc>T-out,B-in,VL-out,VR-out</doc> -</value> -<value name="T" value="28"> -<doc>T-out,B-out,VL-in,VR-in</doc> -</value> -<value name="T" value="29"> -<doc>T-out,B-out,VL-in,VR-out</doc> -</value> -<value name="T" value="30"> -<doc>T-out,B-out,VL-out,VR-in</doc> -</value> -<value name="T" value="31"> -<doc>T-out,B-out,VL-out,VR-out</doc> -</value> -</enum> -<enum name="ENUM136"> -<value name="WRAP" value="0"> -<doc>Wrap (repeat)</doc> -</value> -<value name="MIRROR" value="1"> -<doc>Mirror</doc> -</value> -<value name="CLAMP_TO_LAST_TEXEL" value="2"> -<doc>Clamp to last texel (0.0 to 1.0)</doc> -</value> -<value name="MIRRORONCE_TO_LAST_TEXEL" value="3"> -<doc>MirrorOnce to last texel (-1.0 to 1.0)</doc> -</value> -<value name="CLAMP_HALF_WAY_TO_BORDER_COLOR" value="4"> -<doc>Clamp half way to border color (0.0 to 1.0)</doc> -</value> -<value name="MIRRORONCE_HALF_WAY_TO_BORDER_COLOR" value="5"> -<doc>MirrorOnce half way to border color (-1.0 to 1.0)</doc> -</value> -<value name="CLAMP_TO_BORDER_COLOR" value="6"> -<doc>Clamp to border color (0.0 to 1.0)</doc> -</value> -<value name="MIRRORONCE_TO_BORDER_COLOR" value="7"> -<doc>MirrorOnce to border color (-1.0 to 1.0)</doc> -</value> -</enum> -<enum name="ENUM137"> -<value name="POINT" value="1"> -<doc>Point</doc> -</value> -<value name="LINEAR" value="2"> -<doc>Linear</doc> -</value> -</enum> -<enum name="ENUM138"> -<value name="NONE" value="0"> -<doc>None</doc> -</value> -<value name="POINT" value="1"> -<doc>Point</doc> -</value> -<value name="LINEAR" value="2"> -<doc>Linear</doc> -</value> -</enum> -<enum name="ENUM139"> -<value name="NONE" value="0"> -<doc>None (no filter specifed, select from MIN/MAG filters)</doc> -</value> -<value name="POINT" value="1"> -<doc>Point</doc> -</value> -<value name="LINEAR" value="2"> -<doc>Linear</doc> -</value> -</enum> -<enum name="ENUM140"> -<value name="DISABLE" value="0"> -<doc>Disable</doc> -</value> -<value name="CHROMAKEY" value="1"> -<doc>ChromaKey (kill pixel if any sample matches chroma key)</doc> -</value> -<value name="CHROMAKEYBLEND" value="2"> -<doc>ChromaKeyBlend (set sample to 0 if it matches chroma -key)</doc> -</value> -</enum> -<enum name="ENUM141"> -<value name="NORMAL_ROUNDING_ON_ALL_COMPONENTS" value="0"> -<doc>Normal rounding on all components (+0.5)</doc> -</value> -<value name="MPEG4_ROUNDING_ON_ALL_COMPONENTS" value="1"> -<doc>MPEG4 rounding on all components (+0.25)</doc> -</value> -</enum> -<enum name="ENUM142"> -<value name="DONT_TRUNCATE_COORDINATE_FRACTIONS" value="0"> -<doc>Dont truncate coordinate fractions.</doc> -</value> -<value name="TRUNCATE_COORDINATE_FRACTIONS_TO_0" value="1"> -<doc>Truncate coordinate fractions to 0.0 and 0.5 for MPEG</doc> -</value> -</enum> -<enum name="ENUM143"> -<value name="NON" value="0"> -<doc>Non-Projected</doc> -</value> -<value name="PROJECTED" value="1"> -<doc>Projected</doc> -</value> -</enum> -<enum name="ENUM144"> -<value name="USE_TXWIDTH_FOR_IMAGE_ADDRESSING" value="0"> -<doc>Use TXWIDTH for image addressing</doc> -</value> -<value name="USE_TXPITCH_FOR_IMAGE_ADDRESSING" value="1"> -<doc>Use TXPITCH for image addressing</doc> -</value> -</enum> -<enum name="ENUM154"> -<value name="DISABLE_GAMMA_REMOVAL" value="0"> -<doc>Disable gamma removal</doc> -</value> -<value name="ENABLE_GAMMA_REMOVAL" value="1"> -<doc>Enable gamma removal</doc> -</value> -</enum> -<enum name="ENUM155"> -<value name="DISABLE_YUV_TO_RGB_CONVERSION" value="0"> -<doc>Disable YUV to RGB conversion</doc> -</value> -<value name="ENABLE_YUV_TO_RGB_CONVERSION" value="1"> -<doc>Enable YUV to RGB conversion (with clamp)</doc> -</value> -<value name="ENABLE_YUV_TO_RGB_CONVERSION" value="2"> -<doc>Enable YUV to RGB conversion (without clamp)</doc> -</value> -</enum> -<enum name="ENUM156"> -<value name="DISABLE_SWAP_YUV_MODE" value="0"> -<doc>Disable swap YUV mode</doc> -</value> -<value name="ENABLE_SWAP_YUV_MODE" value="1"> -<doc>Enable swap YUV mode (hw inverts upper bit of U and V)</doc> -</value> -</enum> -<enum name="ENUM157"> -<value name="2D" value="0"> -<doc>2D</doc> -</value> -<value name="3D" value="1"> -<doc>3D</doc> -</value> -<value name="CUBE" value="2"> -<doc>Cube</doc> -</value> -</enum> -<enum name="ENUM158"> -<value name="WHOLE" value="0"> -<doc>WHOLE</doc> -</value> -<value name="HALF_REGION_0" value="2"> -<doc>HALF_REGION_0</doc> -</value> -<value name="HALF_REGION_1" value="3"> -<doc>HALF_REGION_1</doc> -</value> -<value name="FOURTH_REGION_0" value="4"> -<doc>FOURTH_REGION_0</doc> -</value> -<value name="FOURTH_REGION_1" value="5"> -<doc>FOURTH_REGION_1</doc> -</value> -<value name="FOURTH_REGION_2" value="6"> -<doc>FOURTH_REGION_2</doc> -</value> -<value name="FOURTH_REGION_3" value="7"> -<doc>FOURTH_REGION_3</doc> -</value> -<value name="EIGHTH_REGION_0" value="8"> -<doc>EIGHTH_REGION_0</doc> -</value> -<value name="EIGHTH_REGION_1" value="9"> -<doc>EIGHTH_REGION_1</doc> -</value> -<value name="EIGHTH_REGION_2" value="10"> -<doc>EIGHTH_REGION_2</doc> -</value> -<value name="EIGHTH_REGION_3" value="11"> -<doc>EIGHTH_REGION_3</doc> -</value> -<value name="EIGHTH_REGION_4" value="12"> -<doc>EIGHTH_REGION_4</doc> -</value> -<value name="EIGHTH_REGION_5" value="13"> -<doc>EIGHTH_REGION_5</doc> -</value> -<value name="EIGHTH_REGION_6" value="14"> -<doc>EIGHTH_REGION_6</doc> -</value> -<value name="EIGHTH_REGION_7" value="15"> -<doc>EIGHTH_REGION_7</doc> -</value> -<value name="SIXTEENTH_REGION_0" value="16"> -<doc>SIXTEENTH_REGION_0</doc> -</value> -<value name="SIXTEENTH_REGION_1" value="17"> -<doc>SIXTEENTH_REGION_1</doc> -</value> -<value name="SIXTEENTH_REGION_2" value="18"> -<doc>SIXTEENTH_REGION_2</doc> -</value> -<value name="SIXTEENTH_REGION_3" value="19"> -<doc>SIXTEENTH_REGION_3</doc> -</value> -<value name="SIXTEENTH_REGION_4" value="20"> -<doc>SIXTEENTH_REGION_4</doc> -</value> -<value name="SIXTEENTH_REGION_5" value="21"> -<doc>SIXTEENTH_REGION_5</doc> -</value> -<value name="SIXTEENTH_REGION_6" value="22"> -<doc>SIXTEENTH_REGION_6</doc> -</value> -<value name="SIXTEENTH_REGION_7" value="23"> -<doc>SIXTEENTH_REGION_7</doc> -</value> -<value name="SIXTEENTH_REGION_8" value="24"> -<doc>SIXTEENTH_REGION_8</doc> -</value> -<value name="SIXTEENTH_REGION_9" value="25"> -<doc>SIXTEENTH_REGION_9</doc> -</value> -<value name="SIXTEENTH_REGION_A" value="26"> -<doc>SIXTEENTH_REGION_A</doc> -</value> -<value name="SIXTEENTH_REGION_B" value="27"> -<doc>SIXTEENTH_REGION_B</doc> -</value> -<value name="SIXTEENTH_REGION_C" value="28"> -<doc>SIXTEENTH_REGION_C</doc> -</value> -<value name="SIXTEENTH_REGION_D" value="29"> -<doc>SIXTEENTH_REGION_D</doc> -</value> -<value name="SIXTEENTH_REGION_E" value="30"> -<doc>SIXTEENTH_REGION_E</doc> -</value> -<value name="SIXTEENTH_REGION_F" value="31"> -<doc>SIXTEENTH_REGION_F</doc> -</value> -</enum> -<enum name="ENUM159"> -<value name="NO_SWAP" value="0"> -<doc>No swap</doc> -</value> -<value name="16_BIT_SWAP" value="1"> -<doc>16 bit swap</doc> -</value> -<value name="32_BIT_SWAP" value="2"> -<doc>32 bit swap</doc> -</value> -<value name="HALF" value="3"> -<doc>Half-DWORD swap</doc> -</value> -</enum> -<enum name="ENUM160"> -<value name="2KB_PAGE_IS_LINEAR" value="0"> -<doc>2KB page is linear</doc> -</value> -<value name="2KB_PAGE_IS_TILED" value="1"> -<doc>2KB page is tiled</doc> -</value> -</enum> -<enum name="ENUM161"> -<value name="32_BYTE_CACHE_LINE_IS_LINEAR" value="0"> -<doc>32 byte cache line is linear</doc> -</value> -<value name="32_BYTE_CACHE_LINE_IS_TILED" value="1"> -<doc>32 byte cache line is tiled</doc> -</value> -<value name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE" value="2"> -<doc>32 byte cache line is tiled square (only applies to 16-bit -texel)</doc> -</value> -</enum> -<enum name="ENUM164"> -<value name="A" value="0"> -<doc>A: Output to render target A</doc> -</value> -<value name="B" value="1"> -<doc>B: Output to render target B</doc> -</value> -<value name="C" value="2"> -<doc>C: Output to render target C</doc> -</value> -<value name="D" value="3"> -<doc>D: Output to render target D</doc> -</value> -</enum> -<enum name="ENUM166"> -<value name="SRC0" value="0"> -<doc>src0.r</doc> -</value> -<value name="SRC0" value="1"> -<doc>src0.g</doc> -</value> -<value name="SRC0" value="2"> -<doc>src0.b</doc> -</value> -<value name="SRC1" value="3"> -<doc>src1.r</doc> -</value> -<value name="SRC1" value="4"> -<doc>src1.g</doc> -</value> -<value name="SRC1" value="5"> -<doc>src1.b</doc> -</value> -<value name="SRC2" value="6"> -<doc>src2.r</doc> -</value> -<value name="SRC2" value="7"> -<doc>src2.g</doc> -</value> -<value name="SRC2" value="8"> -<doc>src2.b</doc> -</value> -<value name="SRC0" value="9"> -<doc>src0.a</doc> -</value> -<value name="SRC1" value="10"> -<doc>src1.a</doc> -</value> -<value name="SRC2" value="11"> -<doc>src2.a</doc> -</value> -<value name="SRCP" value="12"> -<doc>srcp.r</doc> -</value> -<value name="SRCP" value="13"> -<doc>srcp.g</doc> -</value> -<value name="SRCP" value="14"> -<doc>srcp.b</doc> -</value> -<value name="SRCP" value="15"> -<doc>srcp.a</doc> -</value> -<value name="0" value="16"> -<doc>0.0</doc> -</value> -<value name="1" value="17"> -<doc>1.0</doc> -</value> -<value name="0" value="18"> -<doc>0.5</doc> -</value> -</enum> -<enum name="ENUM167"> -<value name="NOP" value="0"> -<doc>NOP: Do not modify input</doc> -</value> -<value name="NEG" value="1"> -<doc>NEG: Negate input</doc> -</value> -<value name="ABS" value="2"> -<doc>ABS: Take absolute value of input</doc> -</value> -<value name="NAB" value="3"> -<doc>NAB: Take negative absolute value of input</doc> -</value> -</enum> -<enum name="ENUM168"> -<value name="1" value="0"> -<doc>1.0-2.0*A0</doc> -</value> -<value name="A1" value="1"> -<doc>A1-A0</doc> -</value> -<value name="A1" value="2"> -<doc>A1+A0</doc> -</value> -<value name="1" value="3"> -<doc>1.0-A0</doc> -</value> -</enum> -<enum name="ENUM170"> -<value name="RESULT" value="0"> -<doc>Result</doc> -</value> -<value name="RESULT" value="1"> -<doc>Result *2</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result *4</doc> -</value> -<value name="RESULT" value="3"> -<doc>Result *8</doc> -</value> -<value name="RESULT" value="4"> -<doc>Result / 2</doc> -</value> -<value name="RESULT" value="5"> -<doc>Result / 4</doc> -</value> -<value name="RESULT" value="6"> -<doc>Result / 8</doc> -</value> -</enum> -<enum name="ENUM171"> -<value name="DO_NOT_CLAMP_OUTPUT" value="0"> -<doc>Do not clamp output.</doc> -</value> -<value name="CLAMP_OUTPUT_TO_THE_RANGE" value="1"> -<doc>Clamp output to the range [0,1].</doc> -</value> -</enum> -<enum name="ENUM172"> -<value name="NONE" value="0"> -<doc>NONE: No not write any output.</doc> -</value> -<value name="R" value="1"> -<doc>R: Write the red channel only.</doc> -</value> -<value name="G" value="2"> -<doc>G: Write the green channel only.</doc> -</value> -<value name="RG" value="3"> -<doc>RG: Write the red and green channels.</doc> -</value> -<value name="B" value="4"> -<doc>B: Write the blue channel only.</doc> -</value> -<value name="RB" value="5"> -<doc>RB: Write the red and blue channels.</doc> -</value> -<value name="GB" value="6"> -<doc>GB: Write the green and blue channels.</doc> -</value> -<value name="RGB" value="7"> -<doc>RGB: Write the red, green, and blue channels.</doc> -</value> -</enum> -<enum name="ENUM173"> -<value name="SRC0" value="0"> -<doc>src0.rgb</doc> -</value> -<value name="SRC0" value="1"> -<doc>src0.rrr</doc> -</value> -<value name="SRC0" value="2"> -<doc>src0.ggg</doc> -</value> -<value name="SRC0" value="3"> -<doc>src0.bbb</doc> -</value> -<value name="SRC1" value="4"> -<doc>src1.rgb</doc> -</value> -<value name="SRC1" value="5"> -<doc>src1.rrr</doc> -</value> -<value name="SRC1" value="6"> -<doc>src1.ggg</doc> -</value> -<value name="SRC1" value="7"> -<doc>src1.bbb</doc> -</value> -<value name="SRC2" value="8"> -<doc>src2.rgb</doc> -</value> -<value name="SRC2" value="9"> -<doc>src2.rrr</doc> -</value> -<value name="SRC2" value="10"> -<doc>src2.ggg</doc> -</value> -<value name="SRC2" value="11"> -<doc>src2.bbb</doc> -</value> -<value name="SRC0" value="12"> -<doc>src0.aaa</doc> -</value> -<value name="SRC1" value="13"> -<doc>src1.aaa</doc> -</value> -<value name="SRC2" value="14"> -<doc>src2.aaa</doc> -</value> -<value name="SRCP" value="15"> -<doc>srcp.rgb</doc> -</value> -<value name="SRCP" value="16"> -<doc>srcp.rrr</doc> -</value> -<value name="SRCP" value="17"> -<doc>srcp.ggg</doc> -</value> -<value name="SRCP" value="18"> -<doc>srcp.bbb</doc> -</value> -<value name="SRCP" value="19"> -<doc>srcp.aaa</doc> -</value> -<value name="0" value="20"> -<doc>0.0</doc> -</value> -<value name="1" value="21"> -<doc>1.0</doc> -</value> -<value name="0" value="22"> -<doc>0.5</doc> -</value> -<value name="SRC0" value="23"> -<doc>src0.gbr</doc> -</value> -<value name="SRC1" value="24"> -<doc>src1.gbr</doc> -</value> -<value name="SRC2" value="25"> -<doc>src2.gbr</doc> -</value> -<value name="SRC0" value="26"> -<doc>src0.brg</doc> -</value> -<value name="SRC1" value="27"> -<doc>src1.brg</doc> -</value> -<value name="SRC2" value="28"> -<doc>src2.brg</doc> -</value> -<value name="SRC0" value="29"> -<doc>src0.abg</doc> -</value> -<value name="SRC1" value="30"> -<doc>src1.abg</doc> -</value> -<value name="SRC2" value="31"> -<doc>src2.abg</doc> -</value> -</enum> -<enum name="ENUM174"> -<value name="1" value="0"> -<doc>1.0-2.0*RGB0</doc> -</value> -<value name="RGB1" value="1"> -<doc>RGB1-RGB0</doc> -</value> -<value name="RGB1" value="2"> -<doc>RGB1+RGB0</doc> -</value> -<value name="1" value="3"> -<doc>1.0-RGB0</doc> -</value> -</enum> -<enum name="ENUM178"> -<value name="DISABLED" value="0"> -<doc>Disabled</doc> -</value> -<value name="ENABLED" value="1"> -<doc>Enabled</doc> -</value> -</enum> -<enum name="ENUM179"> -<value name="C4_8" value="0"> -<doc>C4_8 (S/U)</doc> -</value> -<value name="C4_10" value="1"> -<doc>C4_10 (U)</doc> -</value> -<value name="C4_10_GAMMA" value="2"> -<doc>C4_10_GAMMA - (U)</doc> -</value> -<value name="C" value="3"> -<doc>C_</doc> -</value> -<value name="C2" value="4"> -<doc>C2_</doc> -</value> -<value name="C4" value="5"> -<doc>C4_</doc> -</value> -<value name="C_16_MPEG" value="6"> -<doc>C_16_MPEG - (S)</doc> -</value> -<value name="C2_16_MPEG" value="7"> -<doc>C2_16_MPEG - (S)</doc> -</value> -<value name="C2" value="8"> -<doc>C2_</doc> -</value> -<value name="C_3_3" value="9"> -<doc>C_3_3_</doc> -</value> -<value name="C_6_5" value="10"> -<doc>C_6_5_</doc> -</value> -<value name="C_11_11" value="11"> -<doc>C_11_11_</doc> -</value> -<value name="C_10_11" value="12"> -<doc>C_10_11_</doc> -</value> -<value name="C_2_10_10" value="13"> -<doc>C_2_10_10_</doc> -</value> -<value name="UNUSED" value="15"> -<doc>UNUSED - Render target is not used</doc> -</value> -<value name="C_16_FP" value="16"> -<doc>C_16_FP - (S10E5)</doc> -</value> -<value name="C2_16_FP" value="17"> -<doc>C2_16_FP - (S10E5)</doc> -</value> -<value name="C4_16_FP" value="18"> -<doc>C4_16_FP - (S10E5)</doc> -</value> -<value name="C_32_FP" value="19"> -<doc>C_32_FP - (S23E8)</doc> -</value> -<value name="C2_32_FP" value="20"> -<doc>C2_32_FP - (S23E8)</doc> -</value> -<value name="C4_32_FP" value="21"> -<doc>C4_32_FP - (S23E8)</doc> -</value> -</enum> -<enum name="ENUM180"> -<value name="ALPHA" value="0"> -<doc>Alpha</doc> -</value> -<value name="RED" value="1"> -<doc>Red</doc> -</value> -<value name="GREEN" value="2"> -<doc>Green</doc> -</value> -<value name="BLUE" value="3"> -<doc>Blue</doc> -</value> -</enum> -<enum name="ENUM183"> -<value name="WSRC_US" value="0"> -<doc>WSRC_US - W comes from shader instruction</doc> -</value> -<value name="WSRC_RAS" value="1"> -<doc>WSRC_RAS - W comes from rasterizer</doc> -</value> -</enum> -<enum name="ENUM185"> -<value name="255" value="0"> -<doc>255.0) 0 1 0.</doc> -</value> -<value name="1" value="0"> -<doc>1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.</doc> -</value> -<value name="127" value="0"> -<doc>127.0) 1 1 -1.</doc> -</value> -<value name="1" value="0"> -<doc>1.0 where n is the number of bits in the associated fixed -point value For signed, normalize conversion, since the fixed point -range is not evenly distributed around 0, there are 3 different -methods supported by R300. See the VAP_PSC_SGN_NORM_CNTL -description for details.</doc> -</value> -</enum> -<enum name="ENUM187"> -<value name="HIERARCHICAL_Z_DISABLED" value="0"> -<doc>Hierarchical Z Disabled</doc> -</value> -<value name="HIERARCHICAL_Z_ENABLED" value="1"> -<doc>Hierarchical Z Enabled</doc> -</value> -</enum> -<enum name="ENUM188"> -<value name="UPDATE_HIERARCHICAL_Z_WITH_MAX_VALUE" value="0"> -<doc>Update Hierarchical Z with Max value</doc> -</value> -<value name="UPDATE_HIERARCHICAL_Z_WITH_MIN_VALUE" value="1"> -<doc>Update Hierarchical Z with Min value</doc> -</value> -</enum> -<enum name="ENUM189"> -<value name="FAST_FILL_DISABLED" value="0"> -<doc>Fast Fill Disabled</doc> -</value> -<value name="FAST_FILL_ENABLED" value="1"> -<doc>Fast Fill Enabled (ZB_DEPTHCLEARVALUE )</doc> -</value> -</enum> -<enum name="ENUM190"> -<value name="Z_READ_COMPRESSION_DISABLED" value="0"> -<doc>Z Read Compression Disabled</doc> -</value> -<value name="Z_READ_COMPRESSION_ENABLED" value="1"> -<doc>Z Read Compression Enabled</doc> -</value> -</enum> -<enum name="ENUM191"> -<value name="Z_WRITE_COMPRESSION_DISABLED" value="0"> -<doc>Z Write Compression Disabled</doc> -</value> -<value name="Z_WRITE_COMPRESSION_ENABLED" value="1"> -<doc>Z Write Compression Enabled</doc> -</value> -</enum> -<enum name="ENUM192"> -<value name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW" value="0"> -<doc>Z unit cache controller does RMW</doc> -</value> -<value name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE" value="1"> -<doc>Z unit cache controller does cache-line granular Write -only</doc> -</value> -</enum> -<enum name="ENUM196"> -<value name="16" value="0"> -<doc>16-bit Integer Z</doc> -</value> -<value name="16" value="1"> -<doc>16-bit compressed 13E3</doc> -</value> -<value name="24" value="2"> -<doc>24-bit Integer Z, 8 bit Stencil (LSBs)</doc> -</value> -</enum> -<enum name="ENUM202"> -<value name="NEVER" value="0"> -<doc>Never</doc> -</value> -<value name="LESS" value="1"> -<doc>Less</doc> -</value> -<value name="LESS_OR_EQUAL" value="2"> -<doc>Less or Equal</doc> -</value> -<value name="EQUAL" value="3"> -<doc>Equal</doc> -</value> -<value name="GREATER_OR_EQUAL" value="4"> -<doc>Greater or Equal</doc> -</value> -<value name="GREATER_THAN" value="5"> -<doc>Greater Than</doc> -</value> -<value name="NOT_EQUAL" value="6"> -<doc>Not Equal</doc> -</value> -<value name="ALWAYS" value="7"> -<doc>Always</doc> -</value> -</enum> -<enum name="ENUM203"> -<value name="NEVER" value="0"> -<doc>Never</doc> -</value> -<value name="LESS" value="1"> -<doc>Less</doc> -</value> -<value name="LESS_OR_EQUAL" value="2"> -<doc>Less or Equal</doc> -</value> -<value name="EQUAL" value="3"> -<doc>Equal</doc> -</value> -<value name="GREATER_OR_EQUAL" value="4"> -<doc>Greater or Equal</doc> -</value> -<value name="GREATER" value="5"> -<doc>Greater</doc> -</value> -<value name="NOT_EQUAL" value="6"> -<doc>Not Equal</doc> -</value> -<value name="ALWAYS" value="7"> -<doc>Always</doc> -</value> -</enum> -<enum name="ENUM204"> -<value name="KEEP" value="0"> -<doc>Keep: New value = Old value</doc> -</value> -<value name="ZERO" value="1"> -<doc>Zero: New value = 0</doc> -</value> -<value name="REPLACE" value="2"> -<doc>Replace: New value = STENCILREF</doc> -</value> -<value name="INCREMENT" value="3"> -<doc>Increment: New value++ (clamp)</doc> -</value> -<value name="DECREMENT" value="4"> -<doc>Decrement: New value-- (clamp)</doc> -</value> -<value name="INVERT_NEW_VALUE" value="5"> -<doc>Invert new value: New value = !Old value</doc> -</value> -<value name="INCREMENT" value="6"> -<doc>Increment: New value++ (wrap)</doc> -</value> -<value name="DECREMENT" value="7"> -<doc>Decrement: New value-- (wrap)</doc> -</value> -</enum> -<enum name="ENUM209"> -<value name="PHYSICAL" value="0"> -<doc>Physical (Default),</doc> -</value> -<value name="VIRTUAL" value="1"> -<doc>Virtual</doc> -</value> -</enum> -<enum name="ENUM216"> -<value name="FULL_SIZE" value="0"> -<doc>Full size</doc> -</value> -<value name="1" value="1"> -<doc>1/2 size</doc> -</value> -<value name="1" value="2"> -<doc>1/4 size</doc> -</value> -<value name="1" value="3"> -<doc>1/8 size</doc> -</value> -</enum> -<enum name="ENUM221"> -<value name="NO_OVERRIDE" value="0"> -<doc>No override</doc> -</value> -<value name="STUFF_TEXTURE_0" value="1"> -<doc>Stuff texture 0</doc> -</value> -<value name="STUFF_TEXTURE_1" value="2"> -<doc>Stuff texture 1</doc> -</value> -<value name="STUFF_TEXTURE_2" value="3"> -<doc>Stuff texture 2</doc> -</value> -<value name="STUFF_TEXTURE_3" value="4"> -<doc>Stuff texture 3</doc> -</value> -<value name="STUFF_TEXTURE_4" value="5"> -<doc>Stuff texture 4</doc> -</value> -<value name="STUFF_TEXTURE_5" value="6"> -<doc>Stuff texture 5</doc> -</value> -<value name="STUFF_TEXTURE_6" value="7"> -<doc>Stuff texture 6</doc> -</value> -<value name="STUFF_TEXTURE_7" value="8"> -<doc>Stuff texture 7</doc> -</value> -<value name="STUFF_TEXTURE_8" value="9"> -<doc>Stuff texture 8/C2</doc> -</value> -<value name="STUFF_TEXTURE_9" value="10"> -<doc>Stuff texture 9/C3</doc> -</value> -</enum> -<enum name="ENUM229"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES" value="0"> -<doc>Replicate VAP source texture coordinates (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</enum> -<enum name="ENUM247"> -<value name="DISABLE_CYLINDRICAL_WRAPPING" value="0"> -<doc>Disable cylindrical wrapping.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING" value="1"> -<doc>Enable cylindrical wrapping.</doc> -</value> -</enum> -<enum name="ENUM248"> -<value name="DISABLE" value="0"> -<doc>Disable, ARGB = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</enum> -<enum name="ENUM249"> -<value name="FILTER4" value="0"> -<doc>Filter4</doc> -</value> -<value name="POINT" value="1"> -<doc>Point</doc> -</value> -<value name="LINEAR" value="2"> -<doc>Linear</doc> -</value> -</enum> -<enum name="ENUM256"> -<value name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" -value="0"> -<doc>Component filter should interpret texel data as unsigned</doc> -</value> -<value name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" -value="1"> -<doc>Component filter should interpret texel data as signed</doc> -</value> -</enum> -<enum name="ENUM257"> -<value name="SELECT_TEXTURE_COMPONENT0" value="0"> -<doc>Select Texture Component0.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1" value="1"> -<doc>Select Texture Component1.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2" value="2"> -<doc>Select Texture Component2.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3" value="3"> -<doc>Select Texture Component3.</doc> -</value> -<value name="SELECT_THE_VALUE_0" value="4"> -<doc>Select the value 0.</doc> -</value> -<value name="SELECT_THE_VALUE_1" value="5"> -<doc>Select the value 1.</doc> -</value> -</enum> -<enum name="ENUM261"> -<value name="NONE" value="0"> -<doc>NONE: Do not modify destination address.</doc> -</value> -<value name="RELATIVE" value="1"> -<doc>RELATIVE: Add aL to address before write.</doc> -</value> -</enum> -<enum name="ENUM262"> -<value name="SRC0" value="0"> -<doc>src0</doc> -</value> -<value name="SRC1" value="1"> -<doc>src1</doc> -</value> -<value name="SRC2" value="2"> -<doc>src2</doc> -</value> -<value name="SRCP" value="3"> -<doc>srcp</doc> -</value> -</enum> -<enum name="ENUM263"> -<value name="RED" value="0"> -<doc>Red</doc> -</value> -<value name="GREEN" value="1"> -<doc>Green</doc> -</value> -<value name="BLUE" value="2"> -<doc>Blue</doc> -</value> -<value name="ALPHA" value="3"> -<doc>Alpha</doc> -</value> -<value name="ZERO" value="4"> -<doc>Zero</doc> -</value> -<value name="HALF" value="5"> -<doc>Half</doc> -</value> -<value name="ONE" value="6"> -<doc>One</doc> -</value> -<value name="UNUSED" value="7"> -<doc>Unused</doc> -</value> -</enum> -<enum name="ENUM264"> -<value name="RESULT" value="0"> -<doc>Result * 1</doc> -</value> -<value name="RESULT" value="1"> -<doc>Result * 2</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result * 4</doc> -</value> -<value name="RESULT" value="3"> -<doc>Result * 8</doc> -</value> -<value name="RESULT" value="4"> -<doc>Result / 2</doc> -</value> -<value name="RESULT" value="5"> -<doc>Result / 4</doc> -</value> -<value name="RESULT" value="6"> -<doc>Result / 8</doc> -</value> -<value name="DISABLE_OUTPUT_MODIFIER_AND_CLAMPING" value="7"> -<doc>Disable output modifier and clamping (result is copied -exactly; only valid for MIN/MAX/CMP/CND)</doc> -</value> -</enum> -<enum name="ENUM265"> -<value name="A" value="0"> -<doc>A: Output to render target A. Predicate == (ALU)</doc> -</value> -<value name="B" value="1"> -<doc>B: Output to render target B. Predicate < (ALU)</doc> -</value> -<value name="C" value="2"> -<doc>C: Output to render target C. Predicate >= (ALU)</doc> -</value> -<value name="D" value="3"> -<doc>D: Output to render target D. Predicate != (ALU)</doc> -</value> -</enum> -<enum name="ENUM267"> -<value name="TEMPORARY" value="0"> -<doc>TEMPORARY: Address temporary register or inline constant -value.</doc> -</value> -<value name="CONSTANT" value="1"> -<doc>CONSTANT: Address constant register.</doc> -</value> -</enum> -<enum name="ENUM268"> -<value name="NONE" value="0"> -<doc>NONE: Do not modify source address.</doc> -</value> -<value name="RELATIVE" value="1"> -<doc>RELATIVE: Add aL before lookup.</doc> -</value> -</enum> -<enum name="ENUM274"> -<value name="NORMAL_PREDICATION" value="0"> -<doc>Normal predication</doc> -</value> -<value name="INVERT_THE_VALUE_OF_THE_PREDICATE" value="1"> -<doc>Invert the value of the predicate</doc> -</value> -</enum> -<enum name="ENUM279"> -<value name="NONE" value="0"> -<doc>NONE: Do not write any output.</doc> -</value> -<value name="R" value="1"> -<doc>R: Write the red channel only.</doc> -</value> -<value name="G" value="2"> -<doc>G: Write the green channel only.</doc> -</value> -<value name="RG" value="3"> -<doc>RG: Write the red and green channels.</doc> -</value> -<value name="B" value="4"> -<doc>B: Write the blue channel only.</doc> -</value> -<value name="RB" value="5"> -<doc>RB: Write the red and blue channels.</doc> -</value> -<value name="GB" value="6"> -<doc>GB: Write the green and blue channels.</doc> -</value> -<value name="RGB" value="7"> -<doc>RGB: Write the red, green, and blue channels.</doc> -</value> -</enum> -<enum name="ENUM298"> -<value name="NONE" value="0"> -<doc>NONE: Do not modify source address</doc> -</value> -<value name="RELATIVE" value="1"> -<doc>RELATIVE: Add aL before lookup.</doc> -</value> -</enum> -<enum name="ENUM299"> -<value name="USE_R_CHANNEL_AS_S_COORDINATE" value="0"> -<doc>Use R channel as S coordinate</doc> -</value> -<value name="USE_G_CHANNEL_AS_S_COORDINATE" value="1"> -<doc>Use G channel as S coordinate</doc> -</value> -<value name="USE_B_CHANNEL_AS_S_COORDINATE" value="2"> -<doc>Use B channel as S coordinate</doc> -</value> -<value name="USE_A_CHANNEL_AS_S_COORDINATE" value="3"> -<doc>Use A channel as S coordinate</doc> -</value> -</enum> -<enum name="ENUM300"> -<value name="USE_R_CHANNEL_AS_T_COORDINATE" value="0"> -<doc>Use R channel as T coordinate</doc> -</value> -<value name="USE_G_CHANNEL_AS_T_COORDINATE" value="1"> -<doc>Use G channel as T coordinate</doc> -</value> -<value name="USE_B_CHANNEL_AS_T_COORDINATE" value="2"> -<doc>Use B channel as T coordinate</doc> -</value> -<value name="USE_A_CHANNEL_AS_T_COORDINATE" value="3"> -<doc>Use A channel as T coordinate</doc> -</value> -</enum> -<enum name="ENUM301"> -<value name="USE_R_CHANNEL_AS_R_COORDINATE" value="0"> -<doc>Use R channel as R coordinate</doc> -</value> -<value name="USE_G_CHANNEL_AS_R_COORDINATE" value="1"> -<doc>Use G channel as R coordinate</doc> -</value> -<value name="USE_B_CHANNEL_AS_R_COORDINATE" value="2"> -<doc>Use B channel as R coordinate</doc> -</value> -<value name="USE_A_CHANNEL_AS_R_COORDINATE" value="3"> -<doc>Use A channel as R coordinate</doc> -</value> -</enum> -<enum name="ENUM302"> -<value name="USE_R_CHANNEL_AS_Q_COORDINATE" value="0"> -<doc>Use R channel as Q coordinate</doc> -</value> -<value name="USE_G_CHANNEL_AS_Q_COORDINATE" value="1"> -<doc>Use G channel as Q coordinate</doc> -</value> -<value name="USE_B_CHANNEL_AS_Q_COORDINATE" value="2"> -<doc>Use B channel as Q coordinate</doc> -</value> -<value name="USE_A_CHANNEL_AS_Q_COORDINATE" value="3"> -<doc>Use A channel as Q coordinate</doc> -</value> -</enum> -<group name="rX00_regs"> -<reg32 access="rw" name="RB3D_AARESOLVE_OFFSET" offset="0x4E80"> -<doc>Resolve buffer destination address. The cache must be empty -before changing this register if the cb is in resolve mode. -Unpipelined</doc> -<bitfield high="31" low="5" name="AARESOLVE_OFFSET" /> -<doc>256-bit aligned 3D resolve destination offset.</doc> -</reg32> -<reg32 access="rw" name="RB3D_AARESOLVE_PITCH" offset="0x4E84"> -<doc>Resolve Buffer Pitch and Tiling Control. The cache must be -empty before changing this register if the cb is in resolve mode. -Unpipelined</doc> -<bitfield high="13" low="1" name="AARESOLVE_PITCH" /> -<doc>3D destination pitch in multiples of 2-pixels.</doc> -</reg32> -<reg32 access="rw" name="RB3D_ABLENDCNTL" offset="0x4E08"> -<doc>Alpha Blend Control for Alpha Channel. Pipelined through the -blender.</doc> -<bitfield high="14" low="12" name="COMB_FCN"> -<use-enum ref="ENUM2" /> -</bitfield> -<doc>Combine Function , Allows modification of how the SRCBLEND and -DESTBLEND are combined.</doc> -<bitfield high="21" low="16" name="SRCBLEND"> -<use-enum ref="ENUM3" /> -</bitfield> -<doc>Source Blend Function , Alpha blending function (SRC).</doc> -<bitfield high="29" low="24" name="DESTBLEND"> -<use-enum ref="ENUM4" /> -</bitfield> -<doc>Destination Blend Function , Alpha blending function -(DST).</doc> -</reg32> -<reg32 access="rw" name="RB3D_CLRCMP_CLR" offset="0x4E20"> -<doc>Color Compare Color. Stalls the 2d/3d datapath until it is -idle.</doc> -</reg32> -<reg32 access="rw" name="RB3D_CLRCMP_FLIPE" offset="0x4E1C"> -<doc>Color Compare Flip. Stalls the 2d/3d datapath until it is -idle.</doc> -</reg32> -<reg32 access="rw" name="RB3D_CLRCMP_MSK" offset="0x4E24"> -<doc>Color Compare Mask. Stalls the 2d/3d datapath until it is -idle.</doc> -</reg32> -<stripe length="4" offset="0x4E28" stride="0x0004"> -<reg32 access="rw" name="RB3D_COLOROFFSET" offset="0x0"> -<doc>Color Buffer Address Offset of multibuffer 0. -Unpipelined.</doc> -<bitfield high="31" low="5" name="COLOROFFSET" /> -<doc>256-bit aligned 3D destination offset address. The cache must -be empty before this is changed.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="RB3D_DITHER_CTL" offset="0x4E50"> -<doc>Dithering control register. Pipelined through the -blender.</doc> -<bitfield high="1" low="0" name="DITHER_MODE"> -<use-enum ref="ENUM17" /> -</bitfield> -<doc>Dither mode</doc> -<bitfield high="3" low="2" name="ALPHA_DITHER_MODE"> -<use-enum ref="ENUM17" /> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="RB3D_DSTCACHE_CTLSTAT" offset="0x4E4C"> -<doc>Destination Color Buffer Cache Control/Status. If the cb is in -e2 mode, then a flush or free will not occur upon a write to this -register, but a sync will be immediately sent if one is requested. -If both DC_FLUSH and DC_FREE are zero but DC_FINISH is one, then a -sync will be sent immediately -- the cb will not wait for all the -previous operations to complete before sending the sync. -Unpipelined except when DC_FINISH and DC_FREE are both set to -zero.</doc> -<bitfield high="1" low="0" name="DC_FLUSH"> -<value name="NO_EFFECT" value="0"> -<doc>No effect</doc> -</value> -<value name="NO_EFFECT" value="1"> -<doc>No effect</doc> -</value> -<value name="FLUSHES_DIRTY_3D_DATA" value="2"> -<doc>Flushes dirty 3D data</doc> -</value> -<value name="FLUSHES_DIRTY_3D_DATA" value="3"> -<doc>Flushes dirty 3D data</doc> -</value> -</bitfield> -<doc>Setting this bit flushes dirty data from the 3D Dst Cache. -Unless the DC_FREE bits are also set, the tags in the cache remain -valid. A purge is achieved by setting both DC_FLUSH and -DC_FREE.</doc> -<bitfield high="3" low="2" name="DC_FREE"> -<value name="NO_EFFECT" value="0"> -<doc>No effect</doc> -</value> -<value name="NO_EFFECT" value="1"> -<doc>No effect</doc> -</value> -<value name="FREE_3D_TAGS" value="2"> -<doc>Free 3D tags</doc> -</value> -<value name="FREE_3D_TAGS" value="3"> -<doc>Free 3D tags</doc> -</value> -</bitfield> -<doc>Setting this bit invalidates the 3D Dst Cache tags. Unless the -DC_FLUSH bit is also set, the cache lines are not written to -memory. A purge is achieved by setting both DC_FLUSH and -DC_FREE.</doc> -<bitfield high="4" low="4" name="DC_FINISH"> -<value name="DO_NOT_SEND_A_FINISH_SIGNAL_TO_THE_CP" value="0"> -<doc>do not send a finish signal to the CP</doc> -</value> -<value name="SEND_A_FINISH_SIGNAL_TO_THE_CP_AFTER_THE_END_OF_OPERATION" -value="1"> -<doc>send a finish signal to the CP after the end of -operation</doc> -</value> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="RB3D_ROPCNTL" offset="0x4E18"> -<doc>3D ROP Control. Stalls the 2d/3d datapath until it is -idle.</doc> -<bitfield high="2" low="2" name="ROP_ENABLE"> -<value name="DISABLE_ROP" value="0"> -<doc>Disable ROP. (Forces ROP2 to be 0xC).</doc> -</value> -<value name="ENABLED" value="1"> -<doc>Enabled</doc> -</value> -</bitfield> -<doc /> -<bitfield high="11" low="8" name="ROP" /> -<doc>ROP2 code for 3D fragments. This value is replicated into 2 -nibbles to form the equivalent ROP3 code to control the ROP3 logic. -These are the GDI ROP2 codes.</doc> -</reg32> -<reg32 access="rw" name="FG_DEPTH_SRC" offset="0x4BD8"> -<doc>Where does depth come from?</doc> -<bitfield high="0" low="0" name="DEPTH_SRC"> -<value name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE_EQUATION" -value="0"> -<doc>Depth comes from scan converter as plane equation.</doc> -</value> -<value name="DEPTH_COMES_FROM_SHADER_AS_FOUR_DISCRETE_VALUES" -value="1"> -<doc>Depth comes from shader as four discrete values.</doc> -</value> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="FG_FOG_BLEND" offset="0x4BC0"> -<doc>Fog Blending Enable</doc> -<bitfield high="0" low="0" name="ENABLE"> -<value name="DISABLES_FOG" value="0"> -<doc>Disables fog (output matches input color).</doc> -</value> -<value name="ENABLES_FOG" value="1"> -<doc>Enables fog.</doc> -</value> -</bitfield> -<doc>Enable for fog blending</doc> -<bitfield high="2" low="1" name="FN"> -<value name="FOG_FUNCTION_IS_LINEAR" value="0"> -<doc>Fog function is linear</doc> -</value> -<value name="FOG_FUNCTION_IS_EXPONENTIAL" value="1"> -<doc>Fog function is exponential</doc> -</value> -<value name="FOG_FUNCTION_IS_EXPONENTIAL_SQUARED" value="2"> -<doc>Fog function is exponential squared</doc> -</value> -<value name="FOG_IS_DERIVED_FROM_CONSTANT_FOG_FACTOR" value="3"> -<doc>Fog is derived from constant fog factor</doc> -</value> -</bitfield> -<doc>Fog generation function</doc> -</reg32> -<reg32 access="rw" name="GA_COLOR_CONTROL" offset="0x4278"> -<doc>Specifies per RGB or Alpha shading method.</doc> -<bitfield high="1" low="0" name="RGB0_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="3" low="2" name="ALPHA0_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="5" low="4" name="RGB1_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="7" low="6" name="ALPHA1_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="9" low="8" name="RGB2_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="11" low="10" name="ALPHA2_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="13" low="12" name="RGB3_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="15" low="14" name="ALPHA3_SHADING"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies solid, flat or Gouraud shading.</doc> -<bitfield high="17" low="16" name="PROVOKING_VERTEX"> -<value name="PROVOKING_IS_FIRST_VERTEX" value="0"> -<doc>Provoking is first vertex</doc> -</value> -<value name="PROVOKING_IS_SECOND_VERTEX" value="1"> -<doc>Provoking is second vertex</doc> -</value> -<value name="PROVOKING_IS_THIRD_VERTEX" value="2"> -<doc>Provoking is third vertex</doc> -</value> -<value name="PROVOKING_IS_ALWAYS_LAST_VERTEX" value="3"> -<doc>Provoking is always last vertex</doc> -</value> -</bitfield> -<doc>Specifies, for flat shaded polygons, which vertex holds the -polygon color.</doc> -</reg32> -<reg32 access="rw" name="GA_FOG_OFFSET" offset="0x4298"> -<doc>Specifies the offset to apply to fog.</doc> -</reg32> -<reg32 access="rw" name="GA_FOG_SCALE" offset="0x4294"> -<doc>Specifies the scale to apply to fog.</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_S0" offset="0x4264"> -<doc>S Texture Coordinate Value for Vertex 0 of Line (stuff -textures -- i.e. AA)</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_S1" offset="0x4268"> -<doc>S Texture Coordinate Value for Vertex 1 of Lines (V2 of -parallelogram -- stuff textures -- i.e. AA)</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_STIPPLE_CONFIG" offset="0x4238"> -<doc>Line Stipple configuration information.</doc> -<bitfield high="1" low="0" name="LINE_RESET"> -<value name="NO_RESETING" value="0"> -<doc>No reseting</doc> -</value> -<value name="RESET_PER_LINE" value="1"> -<doc>Reset per line</doc> -</value> -<value name="RESET_PER_PACKET" value="2"> -<doc>Reset per packet</doc> -</value> -</bitfield> -<doc>Specify type of reset to use for stipple accumulation.</doc> -<bitfield high="31" low="2" name="STIPPLE_SCALE" /> -<doc>Specifies, in truncated (30b) floating point, scale to apply -to generated texture coordinates.</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_STIPPLE_VALUE" offset="0x4260"> -<doc>Current value of stipple accumulator.</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_MINMAX" offset="0x4230"> -<doc>Specifies maximum and minimum point & sprite sizes for per -vertex size specification.</doc> -<bitfield high="15" low="0" name="MIN_SIZE" /> -<doc>Minimum point & sprite radius (in subsamples) size to -allow.</doc> -<bitfield high="31" low="16" name="MAX_SIZE" /> -<doc>Maximum point & sprite radius (in subsamples) size to -allow.</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_S0" offset="0x4200"> -<doc>S Texture Coordinate of Vertex 0 for Point texture stuffing -(LLC)</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_S1" offset="0x4208"> -<doc>S Texture Coordinate of Vertex 2 for Point texture stuffing -(URC)</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_T0" offset="0x4204"> -<doc>T Texture Coordinate of Vertex 0 for Point texture stuffing -(LLC)</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_T1" offset="0x420C"> -<doc>T Texture Coordinate of Vertex 2 for Point texture stuffing -(URC)</doc> -</reg32> -<reg32 access="rw" name="GA_POLY_MODE" offset="0x4288"> -<doc>Polygon Mode</doc> -<bitfield high="1" low="0" name="POLY_MODE"> -<value name="DISABLE_POLY_MODE" value="0"> -<doc>Disable poly mode (render triangles).</doc> -</value> -<value name="DUAL_MODE" value="1"> -<doc>Dual mode (send 2 sets of 3 polys with specified poly -type).</doc> -</value> -</bitfield> -<doc>Polygon mode enable.</doc> -<bitfield high="6" low="4" name="FRONT_PTYPE"> -<use-enum ref="ENUM37" /> -</bitfield> -<doc>Specifies how to render front-facing polygons.</doc> -<bitfield high="9" low="7" name="BACK_PTYPE"> -<use-enum ref="ENUM37" /> -</bitfield> -<doc>Specifies how to render back-facing polygons.</doc> -</reg32> -<reg32 access="rw" name="GA_TRIANGLE_STIPPLE" offset="0x4214"> -<doc>Specifies amount to shift integer position of vertex (screen -space) before converting to float for triangle stipple.</doc> -<bitfield high="3" low="0" name="X_SHIFT" /> -<doc>Amount to shift x position before conversion to SPFP.</doc> -<bitfield high="19" low="16" name="Y_SHIFT" /> -<doc>Amount to shift y position before conversion to SPFP.</doc> -</reg32> -<reg32 access="rw" name="GB_AA_CONFIG" offset="0x4020"> -<doc>Specifies the graphics pipeline configuration for -antialiasing.</doc> -<bitfield high="0" low="0" name="AA_ENABLE"> -<value name="ANTIALIASING_DISABLED" value="0"> -<doc>Antialiasing disabled(def)</doc> -</value> -<value name="ANTIALIASING_ENABLED" value="1"> -<doc>Antialiasing enabled</doc> -</value> -</bitfield> -<doc>Enables antialiasing.</doc> -<bitfield high="2" low="1" name="NUM_AA_SUBSAMPLES"> -<value name="2_SUBSAMPLES" value="0"> -<doc>2 subsamples</doc> -</value> -<value name="3_SUBSAMPLES" value="1"> -<doc>3 subsamples</doc> -</value> -<value name="4_SUBSAMPLES" value="2"> -<doc>4 subsamples</doc> -</value> -<value name="6_SUBSAMPLES" value="3"> -<doc>6 subsamples</doc> -</value> -</bitfield> -<doc>Specifies the number of subsamples to use while -antialiasing.</doc> -</reg32> -<reg32 access="rw" name="SC_CLIP_0_A" offset="0x43B0"> -<doc>OpenGL Clip rectangles</doc> -<bitfield high="12" low="0" name="XS0" /> -<doc>Left hand edge of clip rectangle</doc> -<bitfield high="25" low="13" name="YS0" /> -<doc>Upper edge of clip rectangle</doc> -</reg32> -<reg32 access="rw" name="SC_CLIP_0_B" offset="0x43B4"> -<doc>OpenGL Clip rectangles</doc> -<bitfield high="12" low="0" name="XS1" /> -<doc>Right hand edge of clip rectangle</doc> -<bitfield high="25" low="13" name="YS1" /> -<doc>Lower edge of clip rectangle</doc> -</reg32> -<reg32 access="rw" name="SC_CLIP_1_A" offset="0x43B8" /> -<reg32 access="rw" name="SC_CLIP_1_B" offset="0x43BC" /> -<reg32 access="rw" name="SC_CLIP_2_A" offset="0x43C0" /> -<reg32 access="rw" name="SC_CLIP_2_B" offset="0x43C4" /> -<reg32 access="rw" name="SC_CLIP_3_A" offset="0x43C8" /> -<reg32 access="rw" name="SC_CLIP_3_B" offset="0x43CC" /> -<reg32 access="rw" name="SC_CLIP_RULE" offset="0x43D0"> -<doc>OpenGL Clip boolean function</doc> -<bitfield high="15" low="0" name="CLIP_RULE" /> -<doc>OpenGL Clip boolean function. The `inside` flags for each of -the four clip rectangles form a 4-bit binary number. The -corresponding bit in this 16-bit number specifies whether the pixel -is visible.</doc> -</reg32> -<reg32 access="rw" name="SC_HYPERZ_EN" offset="0x43A4"> -<doc>Hierarchical Z Enable</doc> -<bitfield high="0" low="0" name="HZ_EN"> -<value name="DISABLES_HYPER" value="0"> -<doc>Disables Hyper-Z.</doc> -</value> -<value name="ENABLES_HYPER" value="1"> -<doc>Enables Hyper-Z.</doc> -</value> -</bitfield> -<doc>Enable for hierarchical Z.</doc> -<bitfield high="1" low="1" name="HZ_MAX"> -<value name="HZ_BLOCK_COMPUTES_MINIMUM_Z_VALUE" value="0"> -<doc>HZ block computes minimum z value</doc> -</value> -<value name="HZ_BLOCK_COMPUTES_MAXIMUM_Z_VALUE" value="1"> -<doc>HZ block computes maximum z value</doc> -</value> -</bitfield> -<doc>Specifies whether to compute min or max z value</doc> -<bitfield high="4" low="2" name="HZ_ADJ"> -<value name="ADD_OR_SUBTRACT_1" value="0"> -<doc>Add or Subtract 1/256 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="1"> -<doc>Add or Subtract 1/128 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="2"> -<doc>Add or Subtract 1/64 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="3"> -<doc>Add or Subtract 1/32 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="4"> -<doc>Add or Subtract 1/16 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="5"> -<doc>Add or Subtract 1/8 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="6"> -<doc>Add or Subtract 1/4 << ze</doc> -</value> -<value name="ADD_OR_SUBTRACT_1" value="7"> -<doc>Add or Subtract 1/2 << ze</doc> -</value> -</bitfield> -<doc>Specifies adjustment to get added or subtracted from computed -z value</doc> -<bitfield high="5" low="5" name="HZ_Z0MIN"> -<value name="VERTEX_0_DOES_NOT_CONTAIN_MINIMUM_Z_VALUE" value="0"> -<doc>Vertex 0 does not contain minimum z value</doc> -</value> -<value name="VERTEX_0_DOES_CONTAIN_MINIMUM_Z_VALUE" value="1"> -<doc>Vertex 0 does contain minimum z value</doc> -</value> -</bitfield> -<doc>Specifies whether vertex 0 z contains minimum z value</doc> -<bitfield high="6" low="6" name="HZ_Z0MAX"> -<value name="VERTEX_0_DOES_NOT_CONTAIN_MAXIMUM_Z_VALUE" value="0"> -<doc>Vertex 0 does not contain maximum z value</doc> -</value> -<value name="VERTEX_0_DOES_CONTAIN_MAXIMUM_Z_VALUE" value="1"> -<doc>Vertex 0 does contain maximum z value</doc> -</value> -</bitfield> -<doc>Specifies whether vertex 0 z contains maximum z value</doc> -</reg32> -<reg32 access="rw" name="SC_SCISSOR0" offset="0x43E0"> -<doc>Scissor rectangle specification</doc> -<bitfield high="12" low="0" name="XS0" /> -<doc>Left hand edge of scissor rectangle</doc> -<bitfield high="25" low="13" name="YS0" /> -<doc>Upper edge of scissor rectangle</doc> -</reg32> -<reg32 access="rw" name="SC_SCISSOR1" offset="0x43E4"> -<doc>Scissor rectangle specification</doc> -<bitfield high="12" low="0" name="XS1" /> -<doc>Right hand edge of scissor rectangle</doc> -<bitfield high="25" low="13" name="YS1" /> -<doc>Lower edge of scissor rectangle</doc> -</reg32> -<reg32 access="rw" name="SC_SCREENDOOR" offset="0x43E8"> -<doc>Screen door sample mask</doc> -<bitfield high="23" low="0" name="SCREENDOOR" /> -<doc>Screen door sample mask - 1 means sample may be covered, 0 -means sample is not covered</doc> -</reg32> -<reg32 access="rw" name="SU_CULL_MODE" offset="0x42B8"> -<doc>Culling Enables</doc> -<bitfield high="0" low="0" name="CULL_FRONT"> -<value name="DO_NOT_CULL_FRONT" value="0"> -<doc>Do not cull front-facing triangles.</doc> -</value> -<value name="CULL_FRONT" value="1"> -<doc>Cull front-facing triangles.</doc> -</value> -</bitfield> -<doc>Enable for front-face culling.</doc> -<bitfield high="1" low="1" name="CULL_BACK"> -<value name="DO_NOT_CULL_BACK" value="0"> -<doc>Do not cull back-facing triangles.</doc> -</value> -<value name="CULL_BACK" value="1"> -<doc>Cull back-facing triangles.</doc> -</value> -</bitfield> -<doc>Enable for back-face culling.</doc> -<bitfield high="2" low="2" name="FACE"> -<value name="POSITIVE_CROSS_PRODUCT_IS_FRONT" value="0"> -<doc>Positive cross product is front (CCW).</doc> -</value> -<value name="NEGATIVE_CROSS_PRODUCT_IS_FRONT" value="1"> -<doc>Negative cross product is front (CW).</doc> -</value> -</bitfield> -<doc>X-Ored with cross product sign to determine positive -facing</doc> -</reg32> -<reg32 access="rw" name="SU_DEPTH_OFFSET" offset="0x42C4"> -<doc>SU Depth Offset value</doc> -</reg32> -<reg32 access="rw" name="SU_DEPTH_SCALE" offset="0x42C0"> -<doc>SU Depth Scale value</doc> -</reg32> -<reg32 access="rw" name="SU_POLY_OFFSET_BACK_OFFSET" -offset="0x42B0"> -<doc>Back-Facing Polygon Offset Offset</doc> -</reg32> -<reg32 access="rw" name="SU_POLY_OFFSET_BACK_SCALE" -offset="0x42AC"> -<doc>Back-Facing Polygon Offset Scale</doc> -</reg32> -<reg32 access="rw" name="SU_POLY_OFFSET_ENABLE" offset="0x42B4"> -<doc>Enables for polygon offset</doc> -<bitfield high="0" low="0" name="FRONT_ENABLE"> -<value name="DISABLE_FRONT_OFFSET" value="0"> -<doc>Disable front offset.</doc> -</value> -<value name="ENABLE_FRONT_OFFSET" value="1"> -<doc>Enable front offset.</doc> -</value> -</bitfield> -<doc>Enables front facing polygon`s offset.</doc> -<bitfield high="1" low="1" name="BACK_ENABLE"> -<value name="DISABLE_BACK_OFFSET" value="0"> -<doc>Disable back offset.</doc> -</value> -<value name="ENABLE_BACK_OFFSET" value="1"> -<doc>Enable back offset.</doc> -</value> -</bitfield> -<doc>Enables back facing polygon`s offset.</doc> -<bitfield high="2" low="2" name="PARA_ENABLE"> -<value name="DISABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS" value="0"> -<doc>Disable front offset for parallelograms.</doc> -</value> -<value name="ENABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS" value="1"> -<doc>Enable front offset for parallelograms.</doc> -</value> -</bitfield> -<doc>Forces all parallelograms to have FRONT_FACING for poly offset --- Need to have FRONT_ENABLE also set to have Z offset for -parallelograms.</doc> -</reg32> -<reg32 access="rw" name="SU_POLY_OFFSET_FRONT_OFFSET" -offset="0x42A8"> -<doc>Front-Facing Polygon Offset Offset</doc> -</reg32> -<reg32 access="rw" name="SU_POLY_OFFSET_FRONT_SCALE" -offset="0x42A4"> -<doc>Front-Facing Polygon Offset Scale</doc> -</reg32> -<reg32 access="rw" name="TX_INVALTAGS" offset="0x4100"> -<doc>Invalidate texture cache tags</doc> -</reg32> -<reg32 access="rw" name="VAP_GB_HORZ_CLIP_ADJ" offset="0x2228"> -<doc>Horizontal Guard Band Clip Adjust Register</doc> -</reg32> -<reg32 access="rw" name="VAP_GB_HORZ_DISC_ADJ" offset="0x222C"> -<doc>Horizontal Guard Band Discard Adjust Register</doc> -</reg32> -<reg32 access="rw" name="VAP_GB_VERT_CLIP_ADJ" offset="0x2220"> -<doc>Vertical Guard Band Clip Adjust Register</doc> -</reg32> -<reg32 access="rw" name="VAP_GB_VERT_DISC_ADJ" offset="0x2224"> -<doc>Vertical Guard Band Discard Adjust Register</doc> -</reg32> -<reg32 access="rw" name="VAP_OUT_VTX_FMT_0" offset="0x2090"> -<doc>VAP Out/GA Vertex Format Register 0</doc> -<bitfield high="0" low="0" name="VTX_POS_PRESENT" /> -<doc>Output the Position Vector</doc> -<bitfield high="1" low="1" name="VTX_COLOR_0_PRESENT" /> -<doc>Output Color 0 Vector</doc> -<bitfield high="2" low="2" name="VTX_COLOR_1_PRESENT" /> -<doc>Output Color 1 Vector</doc> -<bitfield high="3" low="3" name="VTX_COLOR_2_PRESENT" /> -<doc>Output Color 2 Vector</doc> -<bitfield high="4" low="4" name="VTX_COLOR_3_PRESENT" /> -<doc>Output Color 3 Vector</doc> -<bitfield high="16" low="16" name="VTX_PT_SIZE_PRESENT" /> -<doc>Output Point Size Vector</doc> -</reg32> -<reg32 access="rw" name="VAP_OUT_VTX_FMT_1" offset="0x2094"> -<doc>VAP Out/GA Vertex Format Register 1</doc> -<bitfield high="2" low="0" name="TEX_0_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="5" low="3" name="TEX_1_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="8" low="6" name="TEX_2_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="11" low="9" name="TEX_3_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="14" low="12" name="TEX_4_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="17" low="15" name="TEX_5_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="20" low="18" name="TEX_6_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -<bitfield high="23" low="21" name="TEX_7_COMP_CNT" /> -<doc>Number of words in texture 0 = Not Present 1 = 1 component 2 = -2 components 3 = 3 components 4 = 4 components</doc> -</reg32> -<stripe length="16" offset="0x2000" stride="0x0004"> -<reg32 access="w" name="VAP_PORT_DATA" offset="0x0"> -<doc>Setup Engine Data Port 0 through 15.</doc> -</reg32> -</stripe> -<reg32 access="w" name="VAP_PORT_DATA_IDX_128" offset="0x20B8"> -<doc>128-bit Data Port for Indexed Primitives.</doc> -</reg32> -<stripe length="16" offset="0x2040" stride="0x0004"> -<reg32 access="w" name="VAP_PORT_IDX" offset="0x0"> -<doc>Setup Engine Index Port 0 through 15.</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x21E0" stride="0x0004"> -<reg32 access="rw" name="VAP_PROG_STREAM_CNTL_EXT" offset="0x0"> -<doc>Programmable Stream Control Extension Word 0</doc> -<bitfield high="2" low="0" name="SWIZZLE_SELECT_X_0" /> -<doc>X-Component Swizzle Select 0 = SELECT_X 1 = SELECT_Y 2 = -SELECT_Z 3 = SELECT_W 4 = SELECT_FP_ZERO (Floating Point 0.0) 5 = -SELECT_FP_ONE (Floating Point 1.0) 6,7 RESERVED</doc> -<bitfield high="5" low="3" name="SWIZZLE_SELECT_Y_0" /> -<doc>Y-Component Swizzle Select (See Above)</doc> -<bitfield high="8" low="6" name="SWIZZLE_SELECT_Z_0" /> -<doc>Z-Component Swizzle Select (See Above)</doc> -<bitfield high="11" low="9" name="SWIZZLE_SELECT_W_0" /> -<doc>W-Component Swizzle Select (See Above)</doc> -<bitfield high="15" low="12" name="WRITE_ENA_0" /> -<doc>4-bit write enable. Bit 0 maps to X Bit 1 maps to Y Bit 2 maps -to Z Bit 3 maps to W</doc> -<bitfield high="18" low="16" name="SWIZZLE_SELECT_X_1" /> -<doc>See SWIZZLE_SELECT_X_0</doc> -<bitfield high="21" low="19" name="SWIZZLE_SELECT_Y_1" /> -<doc>See SWIZZLE_SELECT_Y_0</doc> -<bitfield high="24" low="22" name="SWIZZLE_SELECT_Z_1" /> -<doc>See SWIZZLE_SELECT_Z_0</doc> -<bitfield high="27" low="25" name="SWIZZLE_SELECT_W_1" /> -<doc>See SWIZZLE_SELECT_W_0</doc> -<bitfield high="31" low="28" name="WRITE_ENA_1" /> -<doc>See WRITE_ENA_0</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_PSC_SGN_NORM_CNTL" offset="0x21DC"> -<doc>Programmable Stream Control Signed Normalize Control</doc> -<bitfield high="1" low="0" name="SGN_NORM_METHOD_0"> -<value name="SGN_NORM_ZERO" value="0"> -<doc>SGN_NORM_ZERO : value / (2^(n-1)-1), so - 128/127 will be less -that -1.0, -127/127 will yeild -1.0, 0/127 will yield 0, and -127/127 will yield 1.0 for 8-bit numbers.</doc> -</value> -<value name="SGN_NORM_ZERO_CLAMP_MINUS_ONE" value="1"> -<doc>SGN_NORM_ZERO_CLAMP_MINUS_ONE: Same as SGN_NORM_ZERO except --128/127 will yield -1.0 for 8-bit numbers.</doc> -</value> -<value name="SGN_NORM_NO_ZERO" value="2"> -<doc>SGN_NORM_NO_ZERO: (2 * value + 1)/2^n, so - 128 will yield --255/255 = -1.0, 127 will yield 255/255 = 1.0, but 0 will yield -1/255 != 0.</doc> -</value> -</bitfield> -<doc>There are 3 methods of normalizing signed numbers:</doc> -<bitfield high="3" low="2" name="SGN_NORM_METHOD_1" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="5" low="4" name="SGN_NORM_METHOD_2" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="7" low="6" name="SGN_NORM_METHOD_3" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="9" low="8" name="SGN_NORM_METHOD_4" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="11" low="10" name="SGN_NORM_METHOD_5" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="13" low="12" name="SGN_NORM_METHOD_6" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="15" low="14" name="SGN_NORM_METHOD_7" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="17" low="16" name="SGN_NORM_METHOD_8" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="19" low="18" name="SGN_NORM_METHOD_9" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="21" low="20" name="SGN_NORM_METHOD_10" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="23" low="22" name="SGN_NORM_METHOD_11" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="25" low="24" name="SGN_NORM_METHOD_12" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="27" low="26" name="SGN_NORM_METHOD_13" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="29" low="28" name="SGN_NORM_METHOD_14" /> -<doc>See SGN_NORM_METHOD_0</doc> -<bitfield high="31" low="30" name="SGN_NORM_METHOD_15" /> -<doc>See SGN_NORM_METHOD_0</doc> -</reg32> -<reg32 access="rw" name="VAP_PVS_CODE_CNTL_0" offset="0x22D0"> -<doc>Programmable Vertex Shader Code Control Register 0</doc> -<bitfield high="9" low="0" name="PVS_FIRST_INST" /> -<doc>First Instruction to Execute in PVS.</doc> -<bitfield high="19" low="10" name="PVS_XYZW_VALID_INST" /> -<doc>The PVS Instruction which updates the clip coordinate position -for the last time. This value is used to lower the processing -priority while trivial clip and back-face culling decisions are -made. This field must be set to valid instruction.</doc> -<bitfield high="29" low="20" name="PVS_LAST_INST" /> -<doc>Last Instruction (Inclusive) for the PVS to execute.</doc> -</reg32> -<reg32 access="rw" name="VAP_PVS_CODE_CNTL_1" offset="0x22D8"> -<doc>Programmable Vertex Shader Code Control Register 1</doc> -<bitfield high="9" low="0" name="PVS_LAST_VTX_SRC_INST" /> -<doc>The PVS Instruction which uses the Input Vertex Memory for the -last time. This value is used to free up the Input Vertex Slots -ASAP. This field must be set to a valid instruction.</doc> -</reg32> -<reg32 access="rw" name="VAP_PVS_CONST_CNTL" offset="0x22D4"> -<doc>Programmable Vertex Shader Constant Control Register</doc> -<bitfield high="7" low="0" name="PVS_CONST_BASE_OFFSET" /> -<doc>Vector Offset into PVS constant memory to the start of the -constants for the current shader</doc> -<bitfield high="23" low="16" name="PVS_MAX_CONST_ADDR" /> -<doc>The maximum constant address which should be generated by the -shader (Inst Const Addr + Addr Register). If the address which is -generated by the shader is outside the range of 0 to -PVS_MAX_CONST_ADDR, then (0,0,0,0) is returned as the source -operand data.</doc> -</reg32> -<stripe length="16" offset="0x2230" stride="0x0004"> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS" offset="0x0"> -<doc>Programmable Vertex Shader Flow Control Addresses Register -0</doc> -<bitfield high="7" low="0" name="PVS_FC_ACT_ADRS_0" /> -<doc>This field defines the last PVS instruction to execute prior -to the control flow redirection. JUMP - The last instruction -executed prior to the jump LOOP - The last instruction executed -prior to the loop (init loop counter/inc) JSR - The last -instruction executed prior to the jump to the subroutine.</doc> -<bitfield high="15" low="8" name="PVS_FC_LOOP_CNT_JMP_INST_0" /> -<doc>This field has multiple definitions as follows: JUMP - The -instruction address to jump to. LOOP - The loop count. *Note loop -count of 0 must be replaced by a jump. JSR - The instruction -address to jump to (first inst of subroutine).</doc> -<bitfield high="23" low="16" name="PVS_FC_LAST_INST_0" /> -<doc>This field has multiple definitions as follows: JUMP - Not -Applicable LOOP - The last instruction of the loop. JSR - The last -instruction of the subroutine.</doc> -<bitfield high="31" low="24" name="PVS_FC_RTN_INST_0" /> -<doc>This field has multiple definitions as follows: JUMP - Not -Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS + -1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1)</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_OPC" offset="0x22DC"> -<doc>Programmable Vertex Shader Flow Control Opcode Register</doc> -<bitfield high="1" low="0" name="PVS_FC_OPC_0" /> -<doc>This opcode field determines what type of control flow -instruction to execute. 0 = NO_OP 1 = JUMP 2 = LOOP 3 = JSR (Jump -to Subroutine)</doc> -<bitfield high="3" low="2" name="PVS_FC_OPC_1" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="5" low="4" name="PVS_FC_OPC_2" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="7" low="6" name="PVS_FC_OPC_3" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="9" low="8" name="PVS_FC_OPC_4" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="11" low="10" name="PVS_FC_OPC_5" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="13" low="12" name="PVS_FC_OPC_6" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="15" low="14" name="PVS_FC_OPC_7" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="17" low="16" name="PVS_FC_OPC_8" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="19" low="18" name="PVS_FC_OPC_9" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="21" low="20" name="PVS_FC_OPC_10" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="23" low="22" name="PVS_FC_OPC_11" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="25" low="24" name="PVS_FC_OPC_12" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="27" low="26" name="PVS_FC_OPC_13" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="29" low="28" name="PVS_FC_OPC_14" /> -<doc>See PVS_FC_OPC_0.</doc> -<bitfield high="31" low="30" name="PVS_FC_OPC_15" /> -<doc>See PVS_FC_OPC_0.</doc> -</reg32> -<reg32 access="rw" name="VAP_PVS_STATE_FLUSH_REG" -offset="0x2284" /> -<reg32 access="rw" name="VAP_PVS_VECTOR_DATA_REG" -offset="0x2204" /> -<reg32 access="w" name="VAP_PVS_VECTOR_DATA_REG_128" -offset="0x2208" /> -<reg32 access="rw" name="VAP_PVS_VECTOR_INDX_REG" offset="0x2200"> -<bitfield high="10" low="0" name="OCTWORD_OFFSET" /> -<doc>Octword offset to begin writing.</doc> -</reg32> -<reg32 access="rw" name="VAP_PVS_VTX_TIMEOUT_REG" -offset="0x2288" /> -<reg32 access="rw" name="VAP_VF_MAX_VTX_INDX" offset="0x2134"> -<doc>Maximum Vertex Indx Clamp</doc> -<bitfield high="23" low="0" name="MAX_INDX" /> -<doc>If index to be fetched is larger than this value, the fetch -indx is set to MAX_INDX</doc> -</reg32> -<reg32 access="rw" name="VAP_VF_MIN_VTX_INDX" offset="0x2138"> -<doc>Minimum Vertex Indx Clamp</doc> -<bitfield high="23" low="0" name="MIN_INDX" /> -<doc>If index to be fetched is smaller than this value, the fetch -indx is set to MIN_INDX</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_XOFFSET" offset="0x209C"> -<doc>Viewport Transform X Offset</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_XSCALE" offset="0x2098"> -<doc>Viewport Transform X Scale Factor</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_YOFFSET" offset="0x20A4"> -<doc>Viewport Transform Y Offset</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_YSCALE" offset="0x20A0"> -<doc>Viewport Transform Y Scale Factor</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_ZOFFSET" offset="0x20AC"> -<doc>Viewport Transform Z Offset</doc> -</reg32> -<reg32 access="rw" name="VAP_VPORT_ZSCALE" offset="0x20A8"> -<doc>Viewport Transform Z Scale Factor</doc> -</reg32> -<reg32 access="rw" name="VAP_VTE_CNTL" offset="0x20B0"> -<doc>Viewport Transform Engine Control</doc> -<bitfield high="0" low="0" name="VPORT_X_SCALE_ENA" /> -<doc>Viewport Transform Scale Enable for X component</doc> -<bitfield high="1" low="1" name="VPORT_X_OFFSET_ENA" /> -<doc>Viewport Transform Offset Enable for X component</doc> -<bitfield high="2" low="2" name="VPORT_Y_SCALE_ENA" /> -<doc>Viewport Transform Scale Enable for Y component</doc> -<bitfield high="3" low="3" name="VPORT_Y_OFFSET_ENA" /> -<doc>Viewport Transform Offset Enable for Y component</doc> -<bitfield high="4" low="4" name="VPORT_Z_SCALE_ENA" /> -<doc>Viewport Transform Scale Enable for Z component</doc> -<bitfield high="5" low="5" name="VPORT_Z_OFFSET_ENA" /> -<doc>Viewport Transform Offset Enable for Z component</doc> -<bitfield high="8" low="8" name="VTX_XY_FMT" /> -<doc>Indicates that the incoming X, Y have already been multiplied -by 1/W0. If OFF, the Setup Engine will bultiply the X, Y -coordinates by 1/W0.,</doc> -<bitfield high="9" low="9" name="VTX_Z_FMT" /> -<doc>Indicates that the incoming Z has already been multiplied by -1/W0. If OFF, the Setup Engine will multiply the Z coordinate by -1/W0.</doc> -<bitfield high="10" low="10" name="VTX_W0_FMT" /> -<doc>Indicates that the incoming W0 is not 1/W0. If ON, the Setup -Engine will perform the reciprocal to get 1/W0.</doc> -<bitfield high="11" low="11" name="SERIAL_PROC_ENA" /> -<doc>If set, x,y,z viewport transform are performed serially -through a single pipeline instead of in parallel. Used to mimic -RL300 design.</doc> -</reg32> -<stripe length="16" offset="0x20C8" stride="0x0005"> -<reg32 access="rw" name="VAP_VTX_AOS_ADDR" offset="0x0"> -<doc>Array-of-Structures Address 0</doc> -<bitfield high="31" low="2" name="VTX_AOS_ADDR0" /> -<doc>Base Address of the Array of Structures.</doc> -</reg32> -</stripe> -<stripe length="1415" offset="0x20C4" stride="0x0000"> -<reg32 access="rw" name="VAP_VTX_AOS_ATTR" offset="0x0"> -<doc>Array-of-Structures Attributes 0 & 1</doc> -<bitfield high="6" low="0" name="VTX_AOS_COUNT0" /> -<doc>Number of dwords in this structure.</doc> -<bitfield high="14" low="8" name="VTX_AOS_STRIDE0" /> -<doc>Number of dwords from one array element to the next.</doc> -<bitfield high="22" low="16" name="VTX_AOS_COUNT1" /> -<doc>Number of dwords in this structure.</doc> -<bitfield high="30" low="24" name="VTX_AOS_STRIDE1" /> -<doc>Number of dwords from one array element to the next.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_VTX_SIZE" offset="0x20B4"> -<doc>Vertex Size Specification Register</doc> -<bitfield high="6" low="0" name="DWORDS_PER_VTX" /> -<doc>This field specifies the number of DWORDS per vertex to expect -when VAP_VF_CNTL.PRIM_WALK is set to Vertex Data (vertex data -embedded in command stream). This field is not used for any other -PRIM_WALK settings. This field replaces the usage of the -VAP_VTX_FMT_0/1 for this purpose in prior implementations.</doc> -</reg32> -<reg32 access="rw" name="ZB_DEPTHCLEARVALUE" offset="0x4F28"> -<doc>Z Buffer Clear Value</doc> -</reg32> -<reg32 access="rw" name="ZB_DEPTHOFFSET" offset="0x4F20"> -<doc>Z Buffer Address Offset</doc> -<bitfield high="31" low="5" name="DEPTHOFFSET" /> -<doc>2K aligned Z buffer address offset for macro tiles.</doc> -</reg32> -<reg32 access="rw" name="ZB_DEPTHPITCH" offset="0x4F24"> -<doc>Z Buffer Pitch and Endian Control</doc> -<bitfield high="13" low="2" name="DEPTHPITCH" /> -<doc>Z buffer pitch in multiples of 4 pixels.</doc> -<bitfield high="16" low="16" name="DEPTHMACROTILE"> -<value name="MACRO_TILING_DISABLED" value="0"> -<doc>macro tiling disabled</doc> -</value> -<value name="MACRO_TILING_ENABLED" value="1"> -<doc>macro tiling enabled</doc> -</value> -</bitfield> -<doc>Specifies whether Z buffer is macro-tiled. macro-tiles are 2K -aligned</doc> -<bitfield high="18" low="17" name="DEPTHMICROTILE"> -<value name="32_BYTE_CACHE_LINE_IS_LINEAR" value="0"> -<doc>32 byte cache line is linear</doc> -</value> -<value name="32_BYTE_CACHE_LINE_IS_TILED" value="1"> -<doc>32 byte cache line is tiled</doc> -</value> -<value name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE" value="2"> -<doc>32 byte cache line is tiled square (only applies to 16-bit -pixels)</doc> -</value> -</bitfield> -<doc>Specifies whether Z buffer is micro-tiled. micro-tiles is 32 -bytes</doc> -<bitfield high="20" low="19" name="DEPTHENDIAN"> -<value name="NO_SWAP" value="0"> -<doc>No swap</doc> -</value> -<value name="WORD_SWAP" value="1"> -<doc>Word swap</doc> -</value> -<value name="DWORD_SWAP" value="2"> -<doc>Dword swap</doc> -</value> -<value name="HALF_DWORD_SWAP" value="3"> -<doc>Half Dword swap</doc> -</value> -</bitfield> -<doc>Specifies endian control for the Z buffer.</doc> -</reg32> -<reg32 access="rw" name="ZB_DEPTHXY_OFFSET" offset="0x4F60"> -<doc>Depth buffer X and Y coordinate offset</doc> -<bitfield high="11" low="1" name="DEPTHX_OFFSET" /> -<doc>X coordinate offset. multiple of 32 . Bits 4:0 have to be -zero</doc> -<bitfield high="27" low="17" name="DEPTHY_OFFSET" /> -<doc>Y coordinate offset. multiple of 32 . Bits 4:0 have to be -zero</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_DWORD" offset="0x4F4C"> -<doc>Hierarchical Z Data</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_PITCH" offset="0x4F54"> -<doc>Hierarchical Z Pitch</doc> -<bitfield high="13" low="4" name="HIZ_PITCH" /> -<doc>Pitch used in HiZ address computation.</doc> -</reg32> -<reg32 access="rw" name="ZB_STENCILREFMASK" offset="0x4F08"> -<doc>Stencil Reference Value and Mask</doc> -<bitfield high="7" low="0" name="STENCILREF" /> -<doc>Specifies the reference stencil value.</doc> -<bitfield high="15" low="8" name="STENCILMASK" /> -<doc>This value is ANDed with both the reference and the current -stencil value prior to the stencil test.</doc> -<bitfield high="23" low="16" name="STENCILWRITEMASK" /> -<doc>Specifies the write mask for the stencil planes.</doc> -</reg32> -<reg32 access="rw" name="ZB_ZCACHE_CTLSTAT" offset="0x4F18"> -<doc>Z Buffer Cache Control/Status</doc> -<bitfield high="0" low="0" name="ZC_FLUSH"> -<value name="NO_EFFECT" value="0"> -<doc>No effect</doc> -</value> -<value name="FLUSH_AND_FREE_Z_CACHE_LINES" value="1"> -<doc>Flush and Free Z cache lines</doc> -</value> -</bitfield> -<doc>Setting this bit flushes the dirty data from the Z cache. -Unless ZC_FREE bit is also set, the tags in the cache remain valid. -A purge is achieved by setting both ZC_FLUSH and ZC_FREE. This is a -sticky bit and it clears itself at the end of the operation.</doc> -<bitfield high="1" low="1" name="ZC_FREE"> -<value name="NO_EFFECT" value="0"> -<doc>No effect</doc> -</value> -<value name="FREE_Z_CACHE_LINES" value="1"> -<doc>Free Z cache lines (invalidate)</doc> -</value> -</bitfield> -<doc>Setting this bit invalidates the Z cache tags. Unless ZC_FLUSH -bit is also set, the cachelines are not written to memory. A purge -is achieved by setting both ZC_FLUSH and ZC_FREE. This is a sticky -bit that clears itself at the end of the operation.</doc> -<bitfield high="31" low="31" name="ZC_BUSY"> -<value name="IDLE" value="0"> -<doc>Idle</doc> -</value> -<value name="BUSY" value="1"> -<doc>Busy</doc> -</value> -</bitfield> -<doc>This bit is unused ...</doc> -</reg32> -<reg32 access="rw" name="ZB_ZPASS_ADDR" offset="0x4F5C"> -<doc>Z Buffer Z Pass Counter Address</doc> -<bitfield high="31" low="2" name="ZPASS_ADDR" /> -<doc>Writing this location with a DWORD address causes the value in -ZB_ZPASS_DATA to be written to main memory at the location pointed -to by this address. NOTE: R300 has 2 pixel pipes. Broadcasting this -address causes both pipes to write their ZPASS value to the same -address. There is no guarantee which pipe will write last. So when -writing to this register, the GA needs to be programmed to send the -write command to pipe 0. Then a different address needs to be -written to pipe 1. Then both pipes should be enabled for further -register writes.</doc> -</reg32> -<reg32 access="rw" name="ZB_ZPASS_DATA" offset="0x4F58"> -<doc>Z Buffer Z Pass Counter Data</doc> -</reg32> -<reg32 access="rw" name="ZB_ZTOP" offset="0x4F14"> -<bitfield high="0" low="0" name="ZTOP"> -<value name="Z_IS_AT_THE_BOTTOM_OF_THE_PIPE" value="0"> -<doc>Z is at the bottom of the pipe, after the fog unit.</doc> -</value> -<value name="Z_IS_AT_THE_TOP_OF_THE_PIPE" value="1"> -<doc>Z is at the top of the pipe, after the scan unit.</doc> -</value> -</bitfield> -<doc /> -</reg32> -</group> -<group name="r300_regs"> -<reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88"> -<doc>Resolve Buffer Control. Unpipelined</doc> -<bitfield high="0" low="0" name="AARESOLVE_MODE" /> -<doc>Specifies if the color buffer is in resolve mode. The cache -must be empty before changing this register.</doc> -<bitfield high="1" low="1" name="AARESOLVE_GAMMA"> -<use-enum ref="ENUM1" /> -</bitfield> -<doc>Specifies the gamma and degamma to be applied to the samples -before and after filtering, respectively.</doc> -</reg32> -<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04"> -<doc>Alpha Blend Control for Color Channels. Pipelined through the -blender.</doc> -<bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Allow alpha blending with the destination.</doc> -<bitfield high="1" low="1" name="SEPARATE_ALPHA_ENABLE"> -<use-enum ref="ENUM6" /> -</bitfield> -<doc>Enables use of RB3D_ABLENDCNTL</doc> -<bitfield high="2" low="2" name="READ_ENABLE"> -<use-enum ref="ENUM7" /> -</bitfield> -<doc>When blending is enabled, this enables memory reads. Memory -reads will still occur when this is disabled if they are for -reasons not related to blending.</doc> -<bitfield high="5" low="3" name="DISCARD_SRC_PIXELS"> -<value name="DISABLE" value="0"> -<doc>Disable</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="1"> -<doc>Discard pixels if src alpha == 0</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_COLOR" value="2"> -<doc>Discard pixels if src color == 0</doc> -</value> -<value name="DISCARD_PIXELS_IF" value="3"> -<doc>Discard pixels if (src alpha == 0) && (src color == -0)</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="4"> -<doc>Discard pixels if src alpha == 1</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_COLOR" value="5"> -<doc>Discard pixels if src color == 1</doc> -</value> -<value name="DISCARD_PIXELS_IF" value="6"> -<doc>Discard pixels if (src alpha == 1) && (src color == -1)</doc> -</value> -</bitfield> -<doc>Discard pixels when blending is enabled based on the src -color.</doc> -<bitfield high="14" low="12" name="COMB_FCN"> -<use-enum ref="ENUM2" /> -</bitfield> -<doc>Combine Function , Allows modification of how the SRCBLEND and -DESTBLEND are combined.</doc> -<bitfield high="21" low="16" name="SRCBLEND"> -<use-enum ref="ENUM3" /> -</bitfield> -<doc>Source Blend Function , Alpha blending function (SRC).</doc> -<bitfield high="29" low="24" name="DESTBLEND"> -<use-enum ref="ENUM4" /> -</bitfield> -<doc>Destination Blend Function , Alpha blending function -(DST).</doc> -</reg32> -<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00"> -<doc>Unpipelined.</doc> -<bitfield high="6" low="5" name="NUM_MULTIWRITES"> -<use-enum ref="ENUM9" /> -</bitfield> -<doc>A quad is replicated and written to this many buffers.</doc> -<bitfield high="7" low="7" name="CLRCMP_FLIPE_ENABLE"> -<use-enum ref="ENUM10" /> -</bitfield> -<doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. -This is used to ensure 3D data does not get chromakeyed away by -logic in the backend.</doc> -<bitfield high="9" low="9" name="AA_COMPRESSION_ENABLE"> -<use-enum ref="ENUM11" /> -</bitfield> -<doc>Enables AA color compression. The cache must be empty before -this is changed.</doc> -<bitfield high="10" low="10" name="Reserved" /> -<doc>Set to 0</doc> -</reg32> -<stripe length="4" offset="0x4E38" stride="0x0004"> -<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0"> -<doc>Color buffer format and tiling control for all the -multibuffers and the pitch of multibuffer 0. Unpipelined. The cache -must be empty before any of the registers are changed.</doc> -<bitfield high="13" low="1" name="COLORPITCH" /> -<doc>3D destination pitch in multiples of 2-pixels.</doc> -<bitfield high="16" low="16" name="COLORTILE"> -<use-enum ref="ENUM12" /> -</bitfield> -<doc>Denotes whether the 3D destination is in macrotiled -format.</doc> -<bitfield high="18" low="17" name="COLORMICROTILE"> -<use-enum ref="ENUM13" /> -</bitfield> -<doc>Denotes whether the 3D destination is in microtiled -format.</doc> -<bitfield high="20" low="19" name="COLORENDIAN"> -<use-enum ref="ENUM14" /> -</bitfield> -<doc>Specifies endian control for the color buffer.</doc> -<bitfield high="24" low="21" name="COLORFORMAT"> -<value name="ARGB1555" value="3"> -<doc>ARGB1555</doc> -</value> -<value name="RGB565" value="4"> -<doc>RGB565</doc> -</value> -<value name="ARGB8888" value="6"> -<doc>ARGB8888</doc> -</value> -<value name="ARGB32323232" value="7"> -<doc>ARGB32323232</doc> -</value> -<value name="I8" value="9"> -<doc>I8</doc> -</value> -<value name="ARGB16161616" value="10"> -<doc>ARGB16161616</doc> -</value> -<value name="YUV422_PACKED" value="11"> -<doc>YUV422 packed (VYUY)</doc> -</value> -<value name="YUV422_PACKED" value="12"> -<doc>YUV422 packed (YVYU)</doc> -</value> -<value name="UV88" value="13"> -<doc>UV88</doc> -</value> -<value name="ARGB4444" value="15"> -<doc>ARGB4444</doc> -</value> -</bitfield> -<doc>3D destination color format.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" offset="0x4E0C"> -<doc>3D Color Channel Mask. If all the channels used in the current -color format are disabled, then the cb will discard all the -incoming quads. Pipelined through the blender.</doc> -<bitfield high="0" low="0" name="BLUE_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for blue channel</doc> -<bitfield high="1" low="1" name="GREEN_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for green channel</doc> -<bitfield high="2" low="2" name="RED_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for red channel</doc> -<bitfield high="3" low="3" name="ALPHA_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for alpha channel</doc> -</reg32> -<reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" offset="0x4E14"> -<doc>Clear color that is used when the color mask is set to 00. -Unpipelined.</doc> -</reg32> -<reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10"> -<doc>Constant color used by the blender. Pipelined through the -blender.</doc> -<bitfield high="7" low="0" name="BLUE" /> -<doc>blue constant color</doc> -<bitfield high="15" low="8" name="GREEN" /> -<doc>green constant color</doc> -<bitfield high="23" low="16" name="RED" /> -<doc>red constant color</doc> -<bitfield high="31" low="24" name="ALPHA" /> -<doc>alpha constant color</doc> -</reg32> -<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4"> -<doc>Alpha Function</doc> -<bitfield high="7" low="0" name="AF_VAL" /> -<doc>Specifies the alpha compare value.</doc> -<bitfield high="10" low="8" name="AF_FUNC"> -<use-enum ref="ENUM22" /> -</bitfield> -<doc>Specifies the alpha compare function.</doc> -<bitfield high="11" low="11" name="AF_EN"> -<use-enum ref="ENUM23" /> -</bitfield> -<doc>Enables/Disables alpha compare function.</doc> -<bitfield high="16" low="16" name="AM_EN"> -<use-enum ref="ENUM24" /> -</bitfield> -<doc>Enables/Disables alpha-to-mask function.</doc> -<bitfield high="17" low="17" name="AM_CFG"> -<use-enum ref="ENUM25" /> -</bitfield> -<doc>Specfies number of sub-pixel samples for alpha-to-mask -function.</doc> -<bitfield high="20" low="20" name="DITH_EN"> -<use-enum ref="ENUM26" /> -</bitfield> -<doc>Enables/Disables RGB Dithering.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0"> -<doc>Blue Component of Fog Color</doc> -<bitfield high="9" low="0" name="BLUE" /> -<doc>Blue component of fog color; (0.9) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC"> -<doc>Green Component of Fog Color</doc> -<bitfield high="9" low="0" name="GREEN" /> -<doc>Green component of fog color; (0.9) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8"> -<doc>Red Component of Fog Color</doc> -<bitfield high="9" low="0" name="RED" /> -<doc>Red component of fog color; (0.9) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4"> -<doc>Constant Factor for Fog Blending</doc> -<bitfield high="9" low="0" name="FACTOR" /> -<doc>Constant fog factor; fixed (0.9) format.</doc> -</reg32> -<reg32 access="rw" name="GA_ENHANCE" offset="0x4274"> -<doc>GA Enhancement Register</doc> -<bitfield high="0" low="0" name="DEADLOCK_CNTL"> -<use-enum ref="ENUM32" /> -</bitfield> -<doc>TCL/GA Deadlock control.</doc> -<bitfield high="1" low="1" name="FASTSYNC_CNTL"> -<use-enum ref="ENUM33" /> -</bitfield> -<doc>Enables Fast register/primitive switching</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234"> -<doc>Line control</doc> -<bitfield high="15" low="0" name="WIDTH" /> -<doc>1/2 width of line, in subpixels; (16.0) fixed format.</doc> -<bitfield high="17" low="16" name="END_TYPE"> -<use-enum ref="ENUM34" /> -</bitfield> -<doc>Specifies how ends of lines should be drawn.</doc> -</reg32> -<reg32 access="rw" name="GA_OFFSET" offset="0x4290"> -<doc>Specifies x & y offsets for vertex data after conversion -to FP.</doc> -<bitfield high="15" low="0" name="X_OFFSET" /> -<doc>Specifies X offset in S15 format (subpixels).</doc> -<bitfield high="31" low="16" name="Y_OFFSET" /> -<doc>Specifies Y offset in S15 format (subpixels).</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C"> -<doc>Dimensions for Points</doc> -<bitfield high="15" low="0" name="HEIGHT" /> -<doc>1/2 Height of point; fixed (16.0), subpixel format.</doc> -<bitfield high="31" low="16" name="WIDTH" /> -<doc>1/2 Width of point; fixed (16.0), subpixel format.</doc> -</reg32> -<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C"> -<doc>Specifies the rouding mode for geometry & color SPFP to FP -conversions.</doc> -<bitfield high="1" low="0" name="GEOMETRY_ROUND"> -<use-enum ref="ENUM38" /> -</bitfield> -<doc>Trunc (0) or round to nearest (1) for geometry (XY).</doc> -<bitfield high="3" low="2" name="COLOR_ROUND"> -<use-enum ref="ENUM38" /> -</bitfield> -<doc>Trunc (0) or round to nearest (1) for colors (RGBA).</doc> -<bitfield high="4" low="4" name="RGB_CLAMP"> -<value name="CLAMP_TO" value="0"> -<doc>Clamp to [0,1.0] for RGB</doc> -</value> -<value name="CLAMP_TO" value="1"> -<doc>Clamp to [-7.9999, 7.9999] for RGB</doc> -</value> -</bitfield> -<doc>Specifies SPFP color clamp range of [0,1] or [-8,8] for -RGB.</doc> -<bitfield high="5" low="5" name="ALPHA_CLAMP"> -<value name="CLAMP_TO" value="0"> -<doc>Clamp to [0,1.0] for Alpha</doc> -</value> -<value name="CLAMP_TO" value="1"> -<doc>Clamp to [-7.9999, 7.9999] for Alpha</doc> -</value> -</bitfield> -<doc>Specifies SPFP alpha clamp range of [0,1] or [-8,8].</doc> -</reg32> -<reg32 access="rw" name="GA_SOFT_RESET" offset="0x429C"> -<doc>Specifies number of cycles to assert reset, and also causes -RB3D soft reset to assert.</doc> -<bitfield high="15" low="0" name="SOFT_RESET_COUNT" /> -<doc>Count in cycles (def 256).</doc> -</reg32> -<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280"> -<doc>Specifies blue & alpha components of fill color.</doc> -<bitfield high="15" low="0" name="COLOR_ALPHA" /> -<doc>Component alpha value. (S3.12)</doc> -<bitfield high="31" low="16" name="COLOR_BLUE" /> -<doc>Component blue value. (S3.12)</doc> -</reg32> -<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C"> -<doc>Specifies red & green components of fill color.</doc> -<bitfield high="15" low="0" name="COLOR_GREEN" /> -<doc>Component green value (S3.12).</doc> -<bitfield high="31" low="16" name="COLOR_RED" /> -<doc>Component red value (S3.12).</doc> -</reg32> -<reg32 access="rw" name="GB_ENABLE" offset="0x4008"> -<doc>Specifies top of Raster pipe specific enable controls.</doc> -<bitfield high="0" low="0" name="POINT_STUFF_ENABLE"> -<use-enum ref="ENUM43" /> -</bitfield> -<doc>Specifies if points will have stuffed texture -coordinates.</doc> -<bitfield high="1" low="1" name="LINE_STUFF_ENABLE"> -<use-enum ref="ENUM44" /> -</bitfield> -<doc>Specifies if lines will have stuffed texture -coordinates.</doc> -<bitfield high="2" low="2" name="TRIANGLE_STUFF_ENABLE"> -<use-enum ref="ENUM45" /> -</bitfield> -<doc>Specifies if triangles will have stuffed texture -coordinates.</doc> -<bitfield high="5" low="4" name="STENCIL_AUTO"> -<use-enum ref="ENUM46" /> -</bitfield> -<doc>Specifies if the auto dec/inc stencil mode should be enabled, -and how.</doc> -<bitfield high="17" low="16" name="TEX0_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_0" value="0"> -<doc>Replicate VAP source texture coordinates 0 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="19" low="18" name="TEX1_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_1" value="0"> -<doc>Replicate VAP source texture coordinates 1 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="21" low="20" name="TEX2_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_2" value="0"> -<doc>Replicate VAP source texture coordinates 2 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="23" low="22" name="TEX3_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_3" value="0"> -<doc>Replicate VAP source texture coordinates 3 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="25" low="24" name="TEX4_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_4" value="0"> -<doc>Replicate VAP source texture coordinates 4 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="27" low="26" name="TEX5_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_5" value="0"> -<doc>Replicate VAP source texture coordinates 5 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="29" low="28" name="TEX6_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_6" value="0"> -<doc>Replicate VAP source texture coordinates 6 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -<bitfield high="31" low="30" name="TEX7_SOURCE"> -<value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_7" value="0"> -<doc>Replicate VAP source texture coordinates 7 (S,T,[R,Q]).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> -<doc>Stuff with source texture coordinates (S,T).</doc> -</value> -<value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> -<doc>Stuff with source texture coordinates (S,T,R).</doc> -</value> -</bitfield> -<doc>Specifies the source of the texture coordinates for this -texture.</doc> -</reg32> -<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024"> -<doc>Specifies the sizes of the various FIFO`s in the sc/rs/us. -This register must be the first one written</doc> -<bitfield high="1" low="0" name="SC_IFIFO_SIZE"> -<use-enum ref="ENUM55" /> -</bitfield> -<doc>Size of scan converter input FIFO (XYZ)</doc> -<bitfield high="3" low="2" name="SC_TZFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of scan converter top-of-pipe Z FIFO</doc> -<bitfield high="5" low="4" name="SC_BFIFO_SIZE"> -<use-enum ref="ENUM55" /> -</bitfield> -<doc>Size of scan converter input FIFO (B)</doc> -<bitfield high="7" low="6" name="RS_TFIFO_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of ras input FIFO (Texture)</doc> -<bitfield high="9" low="8" name="RS_CFIFO_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of ras input FIFO (Color)</doc> -<bitfield high="11" low="10" name="US_RAM_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of us RAM</doc> -<bitfield high="13" low="12" name="US_OFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of us output FIFO (RGBA)</doc> -<bitfield high="15" low="14" name="US_WFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of us output FIFO (W)</doc> -<bitfield high="18" low="16" name="RS_HIGHWATER_COL" /> -<doc>High water mark for RS color FIFO (0-7, default 7)</doc> -<bitfield high="21" low="19" name="RS_HIGHWATER_TEX" /> -<doc>High water mark for RS texture FIFO (0-7, default 7)</doc> -<bitfield high="23" low="22" name="US_OFIFO_HIGHWATER"> -<use-enum ref="ENUM58" /> -</bitfield> -<doc>High water mark for US output FIFO (0-12, default 4)</doc> -<bitfield high="27" low="24" name="US_CUBE_FIFO_HIGHWATER" /> -<doc>High water mark for US texture output FIFO (0-15, default -11)</doc> -</reg32> -<reg32 access="rw" name="GB_MSPOS0" offset="0x4010"> -<doc>Specifies the position of multisamples 0 through 2</doc> -<bitfield high="3" low="0" name="MS_X0" /> -<doc>Specifies the x and y position (in subpixels) of multisample -0</doc> -<bitfield high="7" low="4" name="MS_Y0" /> -<doc>Specifies the x and y position (in subpixels) of multisample -0</doc> -<bitfield high="11" low="8" name="MS_X1" /> -<doc>Specifies the x and y position (in subpixels) of multisample -1</doc> -<bitfield high="15" low="12" name="MS_Y1" /> -<doc>Specifies the x and y position (in subpixels) of multisample -1</doc> -<bitfield high="19" low="16" name="MS_X2" /> -<doc>Specifies the x and y position (in subpixels) of multisample -2</doc> -<bitfield high="23" low="20" name="MS_Y2" /> -<doc>Specifies the x and y position (in subpixels) of multisample -2</doc> -<bitfield high="27" low="24" name="MSBD0_Y" /> -<doc>Specifies the minimum y distance (in subpixels) between the -pixel edge and the multisample bounding box. This value is used in -the tile scan converter</doc> -<bitfield high="31" low="28" name="MSBD0_X" /> -<doc>msbd0_x[2:0] specifies the minimum x distance (in subpixels) -between the pixel edge and the multisample bounding box. This value -is used in the tile scan converter. The special case value of 8 is -represented by msbd0_x[2:0]=7. msbd0_x[3] is used to force a -bounding box based tile scan conversion instead of an intercept -based one. This value should always be set to 0.</doc> -</reg32> -<reg32 access="rw" name="GB_MSPOS1" offset="0x4014"> -<doc>Specifies the position of multisamples 3 through 5</doc> -<bitfield high="3" low="0" name="MS_X3" /> -<doc>Specifies the x and y position (in subpixels) of multisample -3</doc> -<bitfield high="7" low="4" name="MS_Y3" /> -<doc>Specifies the x and y position (in subpixels) of multisample -3</doc> -<bitfield high="11" low="8" name="MS_X4" /> -<doc>Specifies the x and y position (in subpixels) of multisample -4</doc> -<bitfield high="15" low="12" name="MS_Y4" /> -<doc>Specifies the x and y position (in subpixels) of multisample -4</doc> -<bitfield high="19" low="16" name="MS_X5" /> -<doc>Specifies the x and y position (in subpixels) of multisample -5</doc> -<bitfield high="23" low="20" name="MS_Y5" /> -<doc>Specifies the x and y position (in subpixels) of multisample -5</doc> -<bitfield high="27" low="24" name="MSBD1" /> -<doc>Specifies the minimum distance (in subpixels) between the -pixel edge and the multisample bounding box. This value is used in -the quad scan converter</doc> -</reg32> -<reg32 access="rw" name="GB_SELECT" offset="0x401C"> -<doc>Specifies various polygon specific selects (fog, depth, -perspective).</doc> -<bitfield high="2" low="0" name="FOG_SELECT"> -<use-enum ref="ENUM59" /> -</bitfield> -<doc>Specifies source for outgoing (GA to SU) fog value.</doc> -<bitfield high="3" low="3" name="DEPTH_SELECT"> -<use-enum ref="ENUM60" /> -</bitfield> -<doc>Specifies source for outgoing (GA/SU & SU/RAS) depth -value.</doc> -<bitfield high="4" low="4" name="W_SELECT"> -<use-enum ref="ENUM61" /> -</bitfield> -<doc>Specifies source for outgoing (1/W) value, used to disable -perspective correct colors/textures.</doc> -</reg32> -<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018"> -<doc>Specifies the graphics pipeline configuration for -rasterization</doc> -<bitfield high="0" low="0" name="ENABLE"> -<use-enum ref="ENUM62" /> -</bitfield> -<doc>Enables tiling, otherwise all tiles receive all -polygons.</doc> -<bitfield high="3" low="1" name="PIPE_COUNT"> -<value name="RV350" value="0"> -<doc>RV350</doc> -</value> -<value name="R300" value="3"> -<doc>R300</doc> -</value> -</bitfield> -<doc>Specifies the number of active pipes and contexts.</doc> -<bitfield high="5" low="4" name="TILE_SIZE"> -<value name="8_PIXELS" value="0"> -<doc>8 pixels (not supported by zb/cb)</doc> -</value> -<value name="16_PIXELS" value="1"> -<doc>16 pixels</doc> -</value> -<value name="32_PIXELS" value="2"> -<doc>32 pixels (not supported by zb/cb)</doc> -</value> -</bitfield> -<doc>Specifies width & height (square), in pixels.</doc> -<bitfield high="8" low="6" name="SUPER_SIZE"> -<use-enum ref="ENUM65" /> -</bitfield> -<doc>Specifies number of tiles and config in super chip -configuration.</doc> -<bitfield high="11" low="9" name="SUPER_X" /> -<doc>X Location of chip within super tile.</doc> -<bitfield high="14" low="12" name="SUPER_Y" /> -<doc>Y Location of chip within super tile.</doc> -<bitfield high="15" low="15" name="SUPER_TILE"> -<use-enum ref="ENUM66" /> -</bitfield> -<doc>Tile location of chip in a multi super tile config (Super size -of 2,8,32 or 128).</doc> -<bitfield high="16" low="16" name="SUBPIXEL"> -<use-enum ref="ENUM67" /> -</bitfield> -<doc>Specifies the subpixel precision.</doc> -<bitfield high="18" low="17" name="QUADS_PER_RAS" /> -<doc>unused</doc> -<bitfield high="19" low="19" name="BB_SCAN" /> -<doc>unused</doc> -</reg32> -<reg32 access="rw" name="RS_COUNT" offset="0x4300"> -<doc>This register specifies the rasterizer input packet -configuration</doc> -<bitfield high="6" low="0" name="IT_COUNT" /> -<doc>Specifies the total number of texture address components -contained in the rasterizer input packet (0:32).</doc> -<bitfield high="10" low="7" name="IC_COUNT" /> -<doc>Specifies the total number of colors contained in the -rasterizer input packet (0:4).</doc> -<bitfield high="11" low="11" name="W_COUNT" /> -<doc>Specifies the total number of w values contained in the -rasterizer input packet (0 or 1).</doc> -<bitfield high="17" low="12" name="W_ADDR" /> -<doc>Specifies the relative rasterizer input packet location of w -(if w_count==1)</doc> -<bitfield high="18" low="18" name="HIRES_EN" /> -<doc>Enable high resolution texture coordinate output when q is -equal to 1</doc> -</reg32> -<stripe length="16" offset="0x4330" stride="0x0004"> -<reg32 access="rw" name="RS_INST" offset="0x0"> -<doc>This table specifies what happens during each rasterizer -instruction</doc> -<bitfield high="2" low="0" name="TEX_ID" /> -<doc>Specifies the index (into the RS_IP table) of the texture -address output during this rasterizer instruction</doc> -<bitfield high="5" low="3" name="TEX_CN"> -<use-enum ref="ENUM68" /> -</bitfield> -<doc>Write enable for texture address</doc> -<bitfield high="10" low="6" name="TEX_ADDR" /> -<doc>Specifies the destination address (within the current pixel -stack frame) of the texture address output during this rasterizer -instruction</doc> -<bitfield high="13" low="11" name="COL_ID" /> -<doc>Specifies the index (into the RS_IP table) of the color output -during this rasterizer instruction</doc> -<bitfield high="16" low="14" name="COL_CN"> -<value name="NO_WRITE" value="0"> -<doc>No write - color not valid</doc> -</value> -<value name="WRITE" value="1"> -<doc>write - color valid</doc> -</value> -</bitfield> -<doc>Write enable for color</doc> -<bitfield high="21" low="17" name="COL_ADDR" /> -<doc>Specifies the destination address (within the current pixel -stack frame) of the color output during this rasterizer -instruction</doc> -<bitfield high="22" low="22" name="TEX_ADJ"> -<use-enum ref="ENUM70" /> -</bitfield> -<doc>Specifies whether to sample texture coordinates at the real or -adjusted pixel centers</doc> -<bitfield high="24" low="23" name="COL_BIAS" /> -<doc>unused</doc> -</reg32> -</stripe> -<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304"> -<doc>This register specifies the number of rasterizer -instructions</doc> -<bitfield high="3" low="0" name="INST_COUNT" /> -<doc>Number of rasterizer instructions (1:16)</doc> -<bitfield high="4" low="4" name="W_EN" /> -<doc>Specifies that the rasterizer needs to generate w</doc> -<bitfield high="7" low="5" name="TX_OFFSET"> -<value name="0" value="0"> -<doc>0.0</doc> -</value> -<value name="RANGE" value="1"> -<doc>range/8K</doc> -</value> -<value name="RANGE" value="2"> -<doc>range/16K</doc> -</value> -<value name="RANGE" value="3"> -<doc>range/32K</doc> -</value> -<value name="RANGE" value="4"> -<doc>range/64K</doc> -</value> -<value name="RANGE" value="5"> -<doc>range/128K</doc> -</value> -<value name="RANGE" value="6"> -<doc>range/256K</doc> -</value> -<value name="RANGE" value="7"> -<doc>range/512K</doc> -</value> -</bitfield> -<doc>Defines texture coordinate offset (based on min/max coordinate -range of triangle) used to minimize or eliminate peroidic errors on -texels sampled right on their edges</doc> -</reg32> -<stripe length="8" offset="0x4310" stride="0x0000"> -<reg32 access="rw" name="RS_IP" offset="0x0"> -<doc>This table specifies the source location and format for up to -8 texture addresses (i[0]:i[7]) and four colors (c[0]:c[3])</doc> -<bitfield high="5" low="0" name="TEX_PTR" /> -<doc>Specifies the relative rasterizer input packet location of -texture address (i[i]).</doc> -<bitfield high="8" low="6" name="COL_PTR" /> -<doc>Specifies the relative rasterizer input packet location of the -color (c[i]).</doc> -<bitfield high="12" low="9" name="COL_FMT"> -<use-enum ref="ENUM72" /> -</bitfield> -<doc>Specifies the format of the color (c[i]).</doc> -<bitfield high="15" low="13" name="SEL_S"> -<use-enum ref="ENUM73" /> -</bitfield> -<doc>Source select for S, T, R, and Q</doc> -<bitfield high="18" low="16" name="SEL_T"> -<use-enum ref="ENUM73" /> -</bitfield> -<doc>Source select for S, T, R, and Q</doc> -<bitfield high="21" low="19" name="SEL_R"> -<use-enum ref="ENUM73" /> -</bitfield> -<doc>Source select for S, T, R, and Q</doc> -<bitfield high="24" low="22" name="SEL_Q"> -<use-enum ref="ENUM73" /> -</bitfield> -<doc>Source select for S, T, R, and Q</doc> -</reg32> -</stripe> -<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8"> -<doc>Edge rules - what happens when an edge falls exactly on a -sample point</doc> -<bitfield high="4" low="0" name="ER_TRI"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="9" low="5" name="ER_POINT"> -<use-enum ref="ENUM75" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="14" low="10" name="ER_LINE_LR"> -<use-enum ref="ENUM75" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="19" low="15" name="ER_LINE_RL"> -<use-enum ref="ENUM75" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="24" low="20" name="ER_LINE_TB"> -<use-enum ref="ENUM75" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="29" low="25" name="ER_LINE_BT"> -<use-enum ref="ENUM75" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -</reg32> -<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8"> -<doc>SU Raster pipe destination select for registers</doc> -<bitfield high="3" low="0" name="SELECT"> -<value name="P0_ENABLE" value="0"> -<doc>P0 enable, b</doc> -</value> -<value name="P1_ENABLE" value="3"> -<doc>P1 enable</doc> -</value> -</bitfield> -<doc>Select which of the 2 pipes (enable per pipe) to send register -read/write to. b0: P0 enable, b3: P1 enable</doc> -</reg32> -<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0"> -<doc>Enables for Cylindrical Wrapping</doc> -<bitfield high="0" low="0" name="T0C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 0 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 0 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="1" low="1" name="T0C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 0 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 0 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="2" low="2" name="T0C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 0 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 0 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="3" low="3" name="T0C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 0 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 0 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="4" low="4" name="T1C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 1 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 1 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="5" low="5" name="T1C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 1 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 1 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="6" low="6" name="T1C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 1 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 1 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="7" low="7" name="T1C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 1 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 1 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="8" low="8" name="T2C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 2 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 2 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="9" low="9" name="T2C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 2 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 2 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="10" low="10" name="T2C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 2 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 2 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="11" low="11" name="T2C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 2 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 2 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="12" low="12" name="T3C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 3 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 3 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="13" low="13" name="T3C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 3 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 3 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="14" low="14" name="T3C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 3 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 3 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="15" low="15" name="T3C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 3 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 3 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="16" low="16" name="T4C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 4 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 4 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="17" low="17" name="T4C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 4 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 4 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="18" low="18" name="T4C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 4 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 4 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="19" low="19" name="T4C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 4 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 4 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="20" low="20" name="T5C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 5 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 5 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="21" low="21" name="T5C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 5 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 5 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="22" low="22" name="T5C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 5 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 5 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="23" low="23" name="T5C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 5 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 5 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="24" low="24" name="T6C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 6 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 6 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="25" low="25" name="T6C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 6 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 6 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="26" low="26" name="T6C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 6 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 6 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="27" low="27" name="T6C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 6 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 6 comp 3.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="28" low="28" name="T7C0"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0" -value="0"> -<doc>Disable cylindrical wrapping for tex 7 comp 0.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0" -value="1"> -<doc>Enable cylindrical wrapping for tex 7 comp 0.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="29" low="29" name="T7C1"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1" -value="0"> -<doc>Disable cylindrical wrapping for tex 7 comp 1.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1" -value="1"> -<doc>Enable cylindrical wrapping for tex 7 comp 1.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="30" low="30" name="T7C2"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2" -value="0"> -<doc>Disable cylindrical wrapping for tex 7 comp 2.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2" -value="1"> -<doc>Enable cylindrical wrapping for tex 7 comp 2.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="31" low="31" name="T7C3"> -<value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3" -value="0"> -<doc>Disable cylindrical wrapping for tex 7 comp 3.</doc> -</value> -<value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3" -value="1"> -<doc>Enable cylindrical wrapping for tex 7 comp 3.</doc> -</value> -</bitfield> -<doc /> -</reg32> -<stripe length="16" offset="0x45C0" stride="0x0004"> -<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0"> -<doc>Border Color for Map 0</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4580" stride="0x0004"> -<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0"> -<doc>Texture Chroma Key for Map 0</doc> -</reg32> -</stripe> -<reg32 access="rw" name="TX_ENABLE" offset="0x4104"> -<doc>Texture Enables for Maps 0 to 15</doc> -<bitfield high="0" low="0" name="TEX_0_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T0(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 0 Enable.</doc> -<bitfield high="1" low="1" name="TEX_1_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T1(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 1 Enable.</doc> -<bitfield high="2" low="2" name="TEX_2_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T2(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 2 Enable.</doc> -<bitfield high="3" low="3" name="TEX_3_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T3(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 3 Enable.</doc> -<bitfield high="4" low="4" name="TEX_4_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T4(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 4 Enable.</doc> -<bitfield high="5" low="5" name="TEX_5_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T5(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 5 Enable.</doc> -<bitfield high="6" low="6" name="TEX_6_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T6(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 6 Enable.</doc> -<bitfield high="7" low="7" name="TEX_7_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T7(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 7 Enable.</doc> -<bitfield high="8" low="8" name="TEX_8_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T8(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 8 Enable.</doc> -<bitfield high="9" low="9" name="TEX_9_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T9(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 9 Enable.</doc> -<bitfield high="10" low="10" name="TEX_10_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T10(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 10 Enable.</doc> -<bitfield high="11" low="11" name="TEX_11_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T11(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 11 Enable.</doc> -<bitfield high="12" low="12" name="TEX_12_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T12(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 12 Enable.</doc> -<bitfield high="13" low="13" name="TEX_13_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T13(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 13 Enable.</doc> -<bitfield high="14" low="14" name="TEX_14_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T14(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 14 Enable.</doc> -<bitfield high="15" low="15" name="TEX_15_ENABLE"> -<value name="DISABLE" value="0"> -<doc>Disable, T15(ARGB) = 1,0,0,0</doc> -</value> -<value name="ENABLE" value="1"> -<doc>Enable</doc> -</value> -</bitfield> -<doc>Texture Map 15 Enable.</doc> -</reg32> -<stripe length="16" offset="0x4400" stride="0x0004"> -<reg32 access="rw" name="TX_FILTER0" offset="0x0"> -<doc>Texture Filter State for Map 0</doc> -<bitfield high="2" low="0" name="CLAMP_S"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for first texture coordinate</doc> -<bitfield high="5" low="3" name="CLAMP_T"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for second texture coordinate</doc> -<bitfield high="8" low="6" name="CLAMP_R"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for third texture coordinate</doc> -<bitfield high="10" low="9" name="MAG_FILTER"> -<use-enum ref="ENUM137" /> -</bitfield> -<doc>Filter used when texture is magnified</doc> -<bitfield high="12" low="11" name="MIN_FILTER"> -<use-enum ref="ENUM137" /> -</bitfield> -<doc>Filter used when texture is minified</doc> -<bitfield high="14" low="13" name="MIP_FILTER"> -<use-enum ref="ENUM138" /> -</bitfield> -<doc>Filter used between mipmap levels</doc> -<bitfield high="16" low="15" name="VOL_FILTER"> -<use-enum ref="ENUM139" /> -</bitfield> -<doc>Filter used between layers of a volume</doc> -<bitfield high="20" low="17" name="MAX_MIP_LEVEL" /> -<doc>LOD index of largest (finest) mipmap to use (0 is largest). -Ranges from 0 to NUM_LEVELS.</doc> -<bitfield high="31" low="28" name="ID" /> -<doc>Logical id for this physical texture</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4440" stride="0x0004"> -<reg32 access="rw" name="TX_FILTER1" offset="0x0"> -<doc>Texture Filter State for Map 0</doc> -<bitfield high="1" low="0" name="CHROMA_KEY_MODE"> -<use-enum ref="ENUM140" /> -</bitfield> -<doc>Chroma Key Mode</doc> -<bitfield high="2" low="2" name="MC_ROUND"> -<use-enum ref="ENUM141" /> -</bitfield> -<doc>Bilinear rounding mode</doc> -<bitfield high="12" low="3" name="LOD_BIAS" /> -<doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias measured -in mipmap levels. Added to the signed, computed LOD before the LOD -is clamped.</doc> -<bitfield high="14" low="14" name="MC_COORD_TRUNCATE"> -<use-enum ref="ENUM142" /> -</bitfield> -<doc>MPEG coordinate truncation mode</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4480" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT0" offset="0x0"> -<doc>Texture Format State for Map 0</doc> -<bitfield high="10" low="0" name="TXWIDTH" /> -<doc>Image width - 1. The largest image is 2048 texels. When -wrapping or mirroring, must be a power of 2. When mipmapping, must -be a power of 2 or padded to a power of 2 in memory. Can always be -non-square, except for cube maps which must be square.</doc> -<bitfield high="21" low="11" name="TXHEIGHT" /> -<doc>Image height - 1. The largest image is 2048 texels. When -wrapping or mirroring, must be a power of 2. When mipmapping, must -be a power of 2 or padded to a power of 2 in memory. Can always be -non-square, except for cube maps which must be square.</doc> -<bitfield high="25" low="22" name="TXDEPTH" /> -<doc>LOG2(depth) of volume texture</doc> -<bitfield high="29" low="26" name="NUM_LEVELS" /> -<doc>Number of mipmap levels minus 1. Ranges from 0 to 11. -Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc> -<bitfield high="30" low="30" name="PROJECTED"> -<use-enum ref="ENUM143" /> -</bitfield> -<doc>Specifies whether texture coords are projected.</doc> -<bitfield high="31" low="31" name="TXPITCH_EN"> -<use-enum ref="ENUM144" /> -</bitfield> -<doc>Indicates when TXPITCH should be used instead of TXWIDTH for -image addressing</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x44C0" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT1" offset="0x0"> -<doc>Texture Format State for Map 0</doc> -<bitfield high="4" low="0" name="TXFORMAT"> -<value name="TX_FMT_8" value="0"> -<doc>TX_FMT_8</doc> -</value> -<value name="TX_FMT_16" value="1"> -<doc>TX_FMT_16</doc> -</value> -<value name="TX_FMT_4_4" value="2"> -<doc>TX_FMT_4_4</doc> -</value> -<value name="TX_FMT_8_8" value="3"> -<doc>TX_FMT_8_8</doc> -</value> -<value name="TX_FMT_16_16" value="4"> -<doc>TX_FMT_16_16</doc> -</value> -<value name="TX_FMT_3_3_2" value="5"> -<doc>TX_FMT_3_3_2</doc> -</value> -<value name="TX_FMT_5_6_5" value="6"> -<doc>TX_FMT_5_6_5</doc> -</value> -<value name="TX_FMT_6_5_5" value="7"> -<doc>TX_FMT_6_5_5</doc> -</value> -<value name="TX_FMT_11_11_10" value="8"> -<doc>TX_FMT_11_11_10</doc> -</value> -<value name="TX_FMT_10_11_11" value="9"> -<doc>TX_FMT_10_11_11</doc> -</value> -<value name="TX_FMT_4_4_4_4" value="10"> -<doc>TX_FMT_4_4_4_4</doc> -</value> -<value name="TX_FMT_1_5_5_5" value="11"> -<doc>TX_FMT_1_5_5_5</doc> -</value> -<value name="TX_FMT_8_8_8_8" value="12"> -<doc>TX_FMT_8_8_8_8</doc> -</value> -<value name="TX_FMT_2_10_10_10" value="13"> -<doc>TX_FMT_2_10_10_10</doc> -</value> -<value name="TX_FMT_16_16_16_16" value="14"> -<doc>TX_FMT_16_16_16_16</doc> -</value> -<value name="TX_FMT_Y8" value="18"> -<doc>TX_FMT_Y8</doc> -</value> -<value name="TX_FMT_AVYU444" value="19"> -<doc>TX_FMT_AVYU444</doc> -</value> -<value name="TX_FMT_VYUY422" value="20"> -<doc>TX_FMT_VYUY422</doc> -</value> -<value name="TX_FMT_YVYU422" value="21"> -<doc>TX_FMT_YVYU422</doc> -</value> -<value name="TX_FMT_16_MPEG" value="22"> -<doc>TX_FMT_16_MPEG</doc> -</value> -<value name="TX_FMT_16_16_MPEG" value="23"> -<doc>TX_FMT_16_16_MPEG</doc> -</value> -<value name="TX_FMT_16F" value="24"> -<doc>TX_FMT_16f</doc> -</value> -<value name="TX_FMT_16F_16F" value="25"> -<doc>TX_FMT_16f_16f</doc> -</value> -<value name="TX_FMT_16F_16F_16F_16F" value="26"> -<doc>TX_FMT_16f_16f_16f_16f</doc> -</value> -<value name="TX_FMT_32F" value="27"> -<doc>TX_FMT_32f</doc> -</value> -<value name="TX_FMT_32F_32F" value="28"> -<doc>TX_FMT_32f_32f</doc> -</value> -<value name="TX_FMT_32F_32F_32F_32F" value="29"> -<doc>TX_FMT_32f_32f_32f_32f</doc> -</value> -<value name="TX_FMT_W24_FP" value="30"> -<doc>TX_FMT_W24_FP</doc> -</value> -</bitfield> -<doc>Texture Format. Components are numbered right to left. -Parenthesis indicate typical uses of each format.</doc> -<bitfield high="5" low="5" name="SIGNED_COMP0"> -<value name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" -value="0"> -<doc>Component0 filter should interpret texel data as -unsigned</doc> -</value> -<value name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" -value="1"> -<doc>Component0 filter should interpret texel data as signed</doc> -</value> -</bitfield> -<doc>Component0 filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="6" low="6" name="SIGNED_COMP1"> -<value name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" -value="0"> -<doc>Component1 filter should interpret texel data as -unsigned</doc> -</value> -<value name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" -value="1"> -<doc>Component1 filter should interpret texel data as signed</doc> -</value> -</bitfield> -<doc>Component1 filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="7" low="7" name="SIGNED_COMP2"> -<value name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" -value="0"> -<doc>Component2 filter should interpret texel data as -unsigned</doc> -</value> -<value name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" -value="1"> -<doc>Component2 filter should interpret texel data as signed</doc> -</value> -</bitfield> -<doc>Component2 filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="8" low="8" name="SIGNED_COMP3"> -<value name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" -value="0"> -<doc>Component3 filter should interpret texel data as -unsigned</doc> -</value> -<value name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" -value="1"> -<doc>Component3 filter should interpret texel data as signed</doc> -</value> -</bitfield> -<doc>Component3 filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="11" low="9" name="SEL_ALPHA"> -<value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_ALPHA_CHANNEL" -value="0"> -<doc>Select Texture Component0 for the Alpha Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_ALPHA_CHANNEL" -value="1"> -<doc>Select Texture Component1 for the Alpha Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_ALPHA_CHANNEL" -value="2"> -<doc>Select Texture Component2 for the Alpha Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_ALPHA_CHANNEL" -value="3"> -<doc>Select Texture Component3 for the Alpha Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_0_FOR_THE_ALPHA_CHANNEL" value="4"> -<doc>Select the value 0 for the Alpha Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_1_FOR_THE_ALPHA_CHANNEL" value="5"> -<doc>Select the value 1 for the Alpha Channel.</doc> -</value> -</bitfield> -<doc>Specifies swizzling for alpha channel at the input of the -pixel shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="14" low="12" name="SEL_RED"> -<value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_RED_CHANNEL" -value="0"> -<doc>Select Texture Component0 for the Red Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_RED_CHANNEL" -value="1"> -<doc>Select Texture Component1 for the Red Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_RED_CHANNEL" -value="2"> -<doc>Select Texture Component2 for the Red Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_RED_CHANNEL" -value="3"> -<doc>Select Texture Component3 for the Red Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_0_FOR_THE_RED_CHANNEL" value="4"> -<doc>Select the value 0 for the Red Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_1_FOR_THE_RED_CHANNEL" value="5"> -<doc>Select the value 1 for the Red Channel.</doc> -</value> -</bitfield> -<doc>Specifies swizzling for red channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="17" low="15" name="SEL_GREEN"> -<value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_GREEN_CHANNEL" -value="0"> -<doc>Select Texture Component0 for the Green Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_GREEN_CHANNEL" -value="1"> -<doc>Select Texture Component1 for the Green Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_GREEN_CHANNEL" -value="2"> -<doc>Select Texture Component2 for the Green Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_GREEN_CHANNEL" -value="3"> -<doc>Select Texture Component3 for the Green Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_0_FOR_THE_GREEN_CHANNEL" value="4"> -<doc>Select the value 0 for the Green Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_1_FOR_THE_GREEN_CHANNEL" value="5"> -<doc>Select the value 1 for the Green Channel.</doc> -</value> -</bitfield> -<doc>Specifies swizzling for green channel at the input of the -pixel shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="20" low="18" name="SEL_BLUE"> -<value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_BLUE_CHANNEL" -value="0"> -<doc>Select Texture Component0 for the Blue Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_BLUE_CHANNEL" -value="1"> -<doc>Select Texture Component1 for the Blue Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_BLUE_CHANNEL" -value="2"> -<doc>Select Texture Component2 for the Blue Channel.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_BLUE_CHANNEL" -value="3"> -<doc>Select Texture Component3 for the Blue Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_0_FOR_THE_BLUE_CHANNEL" value="4"> -<doc>Select the value 0 for the Blue Channel.</doc> -</value> -<value name="SELECT_THE_VALUE_1_FOR_THE_BLUE_CHANNEL" value="5"> -<doc>Select the value 1 for the Blue Channel.</doc> -</value> -</bitfield> -<doc>Specifies swizzling for blue channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="21" low="21" name="GAMMA"> -<use-enum ref="ENUM154" /> -</bitfield> -<doc>Optionally remove gamma from texture before passing to shader. -Only apply to 8bit or less components.</doc> -<bitfield high="23" low="22" name="YUV_TO_RGB"> -<use-enum ref="ENUM155" /> -</bitfield> -<doc>YUV to RGB conversion mode</doc> -<bitfield high="24" low="24" name="SWAP_YUV"> -<use-enum ref="ENUM156" /> -</bitfield> -<doc /> -<bitfield high="26" low="25" name="TEX_COORD_TYPE"> -<use-enum ref="ENUM157" /> -</bitfield> -<doc>Specifies coordinate type.</doc> -<bitfield high="31" low="27" name="CACHE"> -<use-enum ref="ENUM158" /> -</bitfield> -<doc>Multi-texture performance can be optimized and made -deterministic by assigning textures to separate regions under sw -control.</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4500" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT2" offset="0x0"> -<doc>Texture Format State for Map 0</doc> -<bitfield high="13" low="0" name="TXPITCH" /> -<doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN -is asserted. Pitch is given as number of texels minus one. Maximum -pitch is 16K texels.</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4540" stride="0x0004"> -<reg32 access="rw" name="TX_OFFSET" offset="0x0"> -<doc>Texture Offset State for Map 0</doc> -<bitfield high="1" low="0" name="ENDIAN_SWAP"> -<use-enum ref="ENUM159" /> -</bitfield> -<doc>Endian Control</doc> -<bitfield high="2" low="2" name="MACRO_TILE"> -<use-enum ref="ENUM160" /> -</bitfield> -<doc>Macro Tile Control</doc> -<bitfield high="4" low="3" name="MICRO_TILE"> -<use-enum ref="ENUM161" /> -</bitfield> -<doc>Micro Tile Control</doc> -<bitfield high="31" low="5" name="TXOFFSET" /> -<doc>32-byte aligned pointer to base map</doc> -</reg32> -</stripe> -<stripe length="64" offset="0x47C0" stride="0x0004"> -<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0"> -<doc>This table specifies the Alpha source addresses for up to 64 -ALU instruction. The ALU expects 6 source operands - three for -color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> -<bitfield high="5" low="0" name="ADDR0" /> -<doc>Specifies the identity of source operands a0, a1, and a2. -Values 0 through 31 specify a location within the current pixel -stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="11" low="6" name="ADDR1" /> -<doc>Specifies the identity of source operands a0, a1, and a2. -Values 0 through 31 specify a location within the current pixel -stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="17" low="12" name="ADDR2" /> -<doc>Specifies the identity of source operands a0, a1, and a2. -Values 0 through 31 specify a location within the current pixel -stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="22" low="18" name="ADDRD" /> -<doc>Specifies the address of the pixel stack frame register to -which the Alpha result of this instruction is to be written.</doc> -<bitfield high="23" low="23" name="WMASK"> -<value name="NONE" value="0"> -<doc>NONE: No not write register.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only.</doc> -</value> -</bitfield> -<doc>Specifies whether or not to write the Alpha component of the -result for this instruction to the pixel stack frame.</doc> -<bitfield high="24" low="24" name="OMASK"> -<value name="NONE" value="0"> -<doc>NONE: No not write output.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only.</doc> -</value> -</bitfield> -<doc>Specifies whether or not to write the Alpha component of the -result of this instruction to the output fifo.</doc> -<bitfield high="26" low="25" name="TARGET"> -<use-enum ref="ENUM164" /> -</bitfield> -<doc>Specifies which frame buffer target to write to.</doc> -<bitfield high="27" low="27" name="OMASK_W"> -<value name="NONE" value="0"> -<doc>NONE: No not write output to w.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only.</doc> -</value> -</bitfield> -<doc>Specifies whether or not to write the Alpha component of the -result of this instuction to the depth output fifo.</doc> -<bitfield high="31" low="28" name="STAT_WE" /> -<doc>Specifies which components (R,G,B,A) contribute to the stat -count (see performance counter field in US_CONFIG).</doc> -</reg32> -</stripe> -<stripe length="64" offset="0x49C0" stride="0x0004"> -<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0"> -<doc>ALU Alpha Instruction</doc> -<bitfield high="4" low="0" name="SEL_A"> -<use-enum ref="ENUM166" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="6" low="5" name="MOD_A"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="11" low="7" name="SEL_B"> -<use-enum ref="ENUM166" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="13" low="12" name="MOD_B"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="18" low="14" name="SEL_C"> -<use-enum ref="ENUM166" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="20" low="19" name="MOD_C"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="22" low="21" name="SRCP_OP"> -<use-enum ref="ENUM168" /> -</bitfield> -<doc>Specifies how the pre-subtract value (SRCP) is computed</doc> -<bitfield high="26" low="23" name="OP"> -<value name="OP_MAD" value="0"> -<doc>OP_MAD: Result = A*B + C</doc> -</value> -<value name="OP_DP" value="1"> -<doc>OP_DP: Result = dot product from RGB ALU</doc> -</value> -<value name="OP_MIN" value="2"> -<doc>OP_MIN: Result = min(A,B)</doc> -</value> -<value name="OP_MAX" value="3"> -<doc>OP_MAX: Result = max(A,B)</doc> -</value> -<value name="OP_CND" value="5"> -<doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> -</value> -<value name="OP_CMP" value="6"> -<doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc> -</value> -<value name="OP_FRC" value="7"> -<doc>OP_FRC: Result = fractional(A)</doc> -</value> -<value name="OP_EX" value="8"> -<doc>OP_EX</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result = 2^^A</doc> -</value> -<value name="OP_LN" value="9"> -<doc>OP_LN</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result = log2(A)</doc> -</value> -<value name="OP_RCP" value="10"> -<doc>OP_RCP: Result = 1/A</doc> -</value> -<value name="OP_RSQ" value="11"> -<doc>OP_RSQ: Result = 1/sqrt(A)</doc> -</value> -</bitfield> -<doc>Specifies the operand for this instruction.</doc> -<bitfield high="29" low="27" name="OMOD"> -<use-enum ref="ENUM170" /> -</bitfield> -<doc>Specifies the output modifier for this instruction.</doc> -<bitfield high="30" low="30" name="CLAMP"> -<use-enum ref="ENUM171" /> -</bitfield> -<doc>Specifies clamp mode for this instruction.</doc> -</reg32> -</stripe> -<stripe length="64" offset="0x46C0" stride="0x0004"> -<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0"> -<doc>This table specifies the RGB source and destination addresses -for up to 64 ALU instructions. The ALU expects 6 source operands - -three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, -a2).</doc> -<bitfield high="5" low="0" name="ADDR0" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. Values 0 through 31 specify a location within the current -pixel stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="11" low="6" name="ADDR1" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. Values 0 through 31 specify a location within the current -pixel stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="17" low="12" name="ADDR2" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. Values 0 through 31 specify a location within the current -pixel stack frame. Values 32 through 63 specify a constant.</doc> -<bitfield high="22" low="18" name="ADDRD" /> -<doc>Specifies the address of the pixel stack frame register to -which the RGB result of this instruction is to be written.</doc> -<bitfield high="25" low="23" name="WMASK"> -<use-enum ref="ENUM172" /> -</bitfield> -<doc>Specifies which of the R, G, and B components of the result of -this instruction are written to the pixel stack frame.</doc> -<bitfield high="28" low="26" name="OMASK"> -<use-enum ref="ENUM172" /> -</bitfield> -<doc>Specifies which of the R, G, and B components of the result of -this instruction are written to the output fifo.</doc> -<bitfield high="30" low="29" name="TARGET"> -<use-enum ref="ENUM164" /> -</bitfield> -<doc>Specifies which frame buffer target to write to.</doc> -</reg32> -</stripe> -<stripe length="64" offset="0x48C0" stride="0x0004"> -<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0"> -<doc>ALU RGB Instruction</doc> -<bitfield high="4" low="0" name="SEL_A"> -<use-enum ref="ENUM173" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="6" low="5" name="MOD_A"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="11" low="7" name="SEL_B"> -<use-enum ref="ENUM173" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="13" low="12" name="MOD_B"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="18" low="14" name="SEL_C"> -<use-enum ref="ENUM173" /> -</bitfield> -<doc>Specifies the operand and component select for inputs A, B, -and C.</doc> -<bitfield high="20" low="19" name="MOD_C"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the modifier for inputs A, B, and C.</doc> -<bitfield high="22" low="21" name="SRCP_OP"> -<use-enum ref="ENUM174" /> -</bitfield> -<doc>Specifies how the pre-subtract value (SRCP) is computed</doc> -<bitfield high="26" low="23" name="OP"> -<value name="OP_MAD" value="0"> -<doc>OP_MAD: Result = A*B + C</doc> -</value> -<value name="OP_DP" value="1"> -<doc>OP_DP</doc> -</value> -<value name="RESULT" value="3"> -<doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc> -</value> -<value name="OP_DP" value="2"> -<doc>OP_DP</doc> -</value> -<value name="RESULT" value="4"> -<doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc> -</value> -<value name="OP_D2A" value="3"> -<doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc> -</value> -<value name="OP_MIN" value="4"> -<doc>OP_MIN: Result = min(A,B)</doc> -</value> -<value name="OP_MAX" value="5"> -<doc>OP_MAX: Result = max(A,B)</doc> -</value> -<value name="OP_CND" value="7"> -<doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> -</value> -<value name="OP_CMP" value="8"> -<doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc> -</value> -<value name="OP_FRC" value="9"> -<doc>OP_FRC: Result = frac(A)</doc> -</value> -<value name="OP_SOP" value="10"> -<doc>OP_SOP: Result = ex2,ln2,rcp,rsq from Alpha ALU</doc> -</value> -</bitfield> -<doc>Specifies the operand for this instruction.</doc> -<bitfield high="29" low="27" name="OMOD"> -<use-enum ref="ENUM170" /> -</bitfield> -<doc>Specifies the output modifier for this instruction.</doc> -<bitfield high="30" low="30" name="CLAMP"> -<use-enum ref="ENUM171" /> -</bitfield> -<doc>Specifies clamp mode for this instruction.</doc> -<bitfield high="31" low="31" name="NOP"> -<value name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE" -value="0"> -<doc>Do not insert NOP instruction after this one</doc> -</value> -<value name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE" value="1"> -<doc>Insert a NOP instruction after this one</doc> -</value> -</bitfield> -<doc>Specifies whether to insert a NOP instruction after this. This -would get specified in order to meet dependency requirements for -the pre-subtract inputs.</doc> -</reg32> -</stripe> -<stripe length="4" offset="0x4610" stride="0x0004"> -<reg32 access="rw" name="US_CODE_ADDR" offset="0x0"> -<doc>Code Address for Indirection Levels 0 to 3</doc> -<bitfield high="5" low="0" name="ALU_START" /> -<doc>Specifies the start address of the ALU microcode segment -associated with the current indirection level (0:63)</doc> -<bitfield high="11" low="6" name="ALU_SIZE" /> -<doc>Specifies the size of the ALU microcode segment associated -with the current indirection level (1:64)</doc> -<bitfield high="16" low="12" name="TEX_START" /> -<doc>Specifies the start address of the texture microcode segment -associated with the current indirection level (0:31)</doc> -<bitfield high="21" low="17" name="TEX_SIZE" /> -<doc>Specifies the size of the texture microcode segment associated -with the current indirection level (1:32)</doc> -<bitfield high="22" low="22" name="RGBA_OUT" /> -<doc>Indicates at least one RGBA output instruction at this -level</doc> -<bitfield high="23" low="23" name="W_OUT" /> -<doc>Indicates at least one W output instruction at this -level</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4608"> -<doc>Specifies the offset and size for the ALU and Texture -micrcode. These values are used to support relocatable code, and to -support register writes to the code store without requiring a -pipeline flush.</doc> -<bitfield high="5" low="0" name="ALU_OFFSET" /> -<doc>Specifies the offset for the ALU code. This value is added to -the ALU_START field in the US_CODE_ADDR registers (0:63)</doc> -<bitfield high="12" low="6" name="ALU_SIZE" /> -<doc>Specifies the total size for the ALU code for all levels -(0:64)</doc> -<bitfield high="17" low="13" name="TEX_OFFSET" /> -<doc>Specifies the offset for the Texture code. This value is added -to the TEX_START field in the US_CODE_ADDR registers (0:31)</doc> -<bitfield high="23" low="18" name="TEX_SIZE" /> -<doc>Specifies the total size for the Texture code for all levels -(0:32)</doc> -</reg32> -<reg32 access="rw" name="US_CONFIG" offset="0x4600"> -<doc>Shader Configuration</doc> -<bitfield high="2" low="0" name="NLEVEL"> -<value name="LEVEL_3_ONLY" value="0"> -<doc>Level 3 only (normal DX7-style texturing)</doc> -</value> -<value name="LEVELS_2_AND_3" value="1"> -<doc>Levels 2 and 3 (DX8-style bump mapping)</doc> -</value> -<value name="LEVELS_1" value="2"> -<doc>Levels 1, 2, and 3</doc> -</value> -<value name="LEVELS_0" value="3"> -<doc>Levels 0, 1, 2, and 3</doc> -</value> -</bitfield> -<doc>Specifies the valid indirection levels.</doc> -<bitfield high="3" low="3" name="FIRST_TEX"> -<use-enum ref="ENUM178" /> -</bitfield> -<doc>Specifies whether or not the texture code for the first valid -level is enabled</doc> -</reg32> -<stripe length="4" offset="0x46A4" stride="0x0004"> -<reg32 access="rw" name="US_OUT_FMT" offset="0x0"> -<doc>Specifies how the shader output is written to the fog unit for -each of up to four render targets</doc> -<bitfield high="4" low="0" name="OUT_FMT"> -<use-enum ref="ENUM179" /> -</bitfield> -<doc>Specifies the number and size of components</doc> -<bitfield high="9" low="8" name="C0_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc>Specifies the source for components C0, C1, C2, C3</doc> -<bitfield high="11" low="10" name="C1_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc>Specifies the source for components C0, C1, C2, C3</doc> -<bitfield high="13" low="12" name="C2_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc>Specifies the source for components C0, C1, C2, C3</doc> -<bitfield high="15" low="14" name="C3_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc>Specifies the source for components C0, C1, C2, C3</doc> -<bitfield high="19" low="16" name="OUT_SIGN" /> -<doc>Mask specifying whether components C3, C2, C1 and C0 are -signed (C4_8, C_16, C2_16 and C4_16 formats only)</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_PIXSIZE" offset="0x4604"> -<doc>Shader pixel size. This register specifies the size and -partitioning of the current pixel stack frame</doc> -<bitfield high="4" low="0" name="PIX_SIZE" /> -<doc>Specifies the total size of the current pixel stack frame -(1:32)</doc> -</reg32> -<stripe length="32" offset="0x4620" stride="0x0004"> -<reg32 access="rw" name="US_TEX_INST" offset="0x0"> -<doc>Texture Instruction</doc> -<bitfield high="4" low="0" name="SRC_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the texture address for this instruction</doc> -<bitfield high="10" low="6" name="DST_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the returned texture data for this instruction</doc> -<bitfield high="14" low="11" name="TEX_ID" /> -<doc>Specifies the id of the texture map used for this -instruction</doc> -<bitfield high="17" low="15" name="INST"> -<value name="NOP" value="0"> -<doc>NOP: Do nothing</doc> -</value> -<value name="LD" value="1"> -<doc>LD: Do Texture Lookup (S,T,R)</doc> -</value> -<value name="TEXKILL" value="2"> -<doc>TEXKILL: Kill pixel if any component is < 0</doc> -</value> -<value name="PROJ" value="3"> -<doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc> -</value> -<value name="LODBIAS" value="4"> -<doc>LODBIAS: Do texture lookup with lod bias</doc> -</value> -</bitfield> -<doc>Specifies the operation taking place for this -instruction</doc> -<bitfield high="18" low="18" name="OMOD" /> -<doc>unused</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_W_FMT" offset="0x46B4"> -<doc>Specifies the source and format for the Depth (W) value output -by the shader</doc> -<bitfield high="1" low="0" name="W_FMT"> -<value name="W" value="0"> -<doc>W</doc> -</value> -<value name="W_IS_ALWAYS_ZERO" value="0"> -<doc>W is always zero</doc> -</value> -<value name="W" value="1"> -<doc>W</doc> -</value> -<value name="24" value="24"> -<doc>24-bit fixed point</doc> -</value> -<value name="W24_FP" value="2"> -<doc>W24_FP - 24-bit floating point</doc> -</value> -</bitfield> -<doc>Format for W</doc> -<bitfield high="2" low="2" name="W_SRC"> -<use-enum ref="ENUM183" /> -</bitfield> -<doc>Source for W</doc> -</reg32> -<stripe length="32" offset="0x4C0C" stride="0x0010"> -<reg32 access="rw" name="US_ALU_CONST_A" offset="0x0"> -<doc>Shader Constant Color 0 Alpha Component</doc> -<bitfield high="23" low="0" name="KA" /> -<doc>Specifies the alpha component; (S16E7) fixed format.</doc> -</reg32> -</stripe> -<stripe length="32" offset="0x4C08" stride="0x0010"> -<reg32 access="rw" name="US_ALU_CONST_B" offset="0x0"> -<doc>Shader Constant Color 0 Blue Component</doc> -<bitfield high="23" low="0" name="KB" /> -<doc>Specifies the blue component; (S16E7) fixed format.</doc> -</reg32> -</stripe> -<stripe length="32" offset="0x4C04" stride="0x0010"> -<reg32 access="rw" name="US_ALU_CONST_G" offset="0x0"> -<doc>Shader Constant Color 0 Green Component</doc> -<bitfield high="23" low="0" name="KG" /> -<doc>Specifies the green component; (S16E7) fixed format.</doc> -</reg32> -</stripe> -<stripe length="32" offset="0x4C00" stride="0x0010"> -<reg32 access="rw" name="US_ALU_CONST_R" offset="0x0"> -<doc>Shader Constant Color 0 Red Component</doc> -<bitfield high="23" low="0" name="KR" /> -<doc>Specifies the red component; (S16E7) fixed format.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C"> -<doc>Control Bits for User Clip Planes and Clipping</doc> -<bitfield high="0" low="0" name="UCP_ENA_0" /> -<doc>Enable User Clip Plane 0</doc> -<bitfield high="1" low="1" name="UCP_ENA_1" /> -<doc>Enable User Clip Plane 1</doc> -<bitfield high="2" low="2" name="UCP_ENA_2" /> -<doc>Enable User Clip Plane 2</doc> -<bitfield high="3" low="3" name="UCP_ENA_3" /> -<doc>Enable User Clip Plane 3</doc> -<bitfield high="4" low="4" name="UCP_ENA_4" /> -<doc>Enable User Clip Plane 4</doc> -<bitfield high="5" low="5" name="UCP_ENA_5" /> -<doc>Enable User Clip Plane 5</doc> -<bitfield high="15" low="14" name="PS_UCP_MODE" /> -<doc>0 = Cull using distance from center of point 1 = Cull using -radius-based distance from center of point 2 = Cull using -radius-based distance from center of point, Expand and Clip on -intersection 3 = Always expand and clip as trifan</doc> -<bitfield high="16" low="16" name="CLIP_DISABLE" /> -<doc>Disables clip code generation and clipping process for -TCL</doc> -<bitfield high="17" low="17" name="UCP_CULL_ONLY_ENA" /> -<doc>Cull Primitives against UCPS, but don`t clip</doc> -<bitfield high="18" low="18" name="BOUNDARY_EDGE_FLAG_ENA" /> -<doc>If set, boundary edges are highlighted, else they are not -highlighted</doc> -</reg32> -<reg32 access="rw" name="VAP_CNTL" offset="0x2080"> -<doc>Vertex Assembler/Processor Control Register</doc> -<bitfield high="3" low="0" name="PVS_NUM_SLOTS" /> -<doc>Specifies the number of vertex slots to be used in the VAP PVS -process. A slot represents a single vertex storage location1 across -multiple engines (one vertex per engine). By decreasing the number -of slots, there is more memory for each vertex, but less parallel -processing. Similarly, by increasing the number of slots, thre is -less memory per vertex but more vertices being processed in -parallel.</doc> -<bitfield high="7" low="4" name="PVS_NUM_CNTLRS" /> -<doc>Specifies the maximum number of controllers to be processing -in parallel. In general should be set to max value of TBD. Can be -changed for performance analysis.</doc> -<bitfield high="11" low="8" name="PVS_NUM_FPUS" /> -<doc>Specifies the number of Floating Point Units (Vector/Math -Engines) to use when processing vertices.</doc> -<bitfield high="21" low="18" name="VF_MAX_VTX_NUM" /> -<doc>This field controls the number of vertices that the vertex -fetcher manages for the TCL and Setup Vertex Storage memories (and -therefore the number of vertices that can be re-used). This value -should be set to 12 for most operation, This number may be modified -for performance evaluation. The value is the maximum vertex number -used which is one less than the number of vertices (i.e. a 12 means -13 vertices will be used)</doc> -<bitfield high="22" low="22" name="DX_CLIP_SPACE_DEF"> -<use-enum ref="ENUM184" /> -</bitfield> -<doc>Clip space is defined as:</doc> -</reg32> -<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140"> -<doc>Vertex Assemblen/Processor Control Status</doc> -<bitfield high="1" low="0" name="VC_SWAP" /> -<doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD -becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 -= Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB Default = 0</doc> -<bitfield high="8" low="8" name="PVS_BYPASS" /> -<doc>The TCL engine is logically or physically removed from the -circuit.</doc> -<bitfield high="11" low="11" name="PVS_BUSY" /> -<doc>Transform/Clip/Light (TCL) Engine is Busy. Read-only.</doc> -<bitfield high="24" low="24" name="VS_BUSY" /> -<doc>Vertex Store is Busy. Read-only.</doc> -<bitfield high="25" low="25" name="RCP_BUSY" /> -<doc>Reciprocal Engine is Busy. Read-only.</doc> -<bitfield high="26" low="26" name="VTE_BUSY" /> -<doc>ViewPort Transform Engine is Busy. Read-only.</doc> -<bitfield high="27" low="27" name="MIU_BUSY" /> -<doc>Memory Interface Unit is Busy. Read-only.</doc> -<bitfield high="28" low="28" name="VC_BUSY" /> -<doc>Vertex Cache is Busy. Read-only.</doc> -<bitfield high="29" low="29" name="VF_BUSY" /> -<doc>Vertex Fetcher is Busy. Read-only.</doc> -<bitfield high="30" low="30" name="REGPIPE_BUSY" /> -<doc>Register Pipeline is Busy. Read-only.</doc> -<bitfield high="31" low="31" name="VAP_BUSY" /> -<doc>VAP Engine is Busy. Read-only.</doc> -</reg32> -<stripe length="8" offset="0x2150" stride="0x0004"> -<reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0"> -<doc>Programmable Stream Control Word 0</doc> -<bitfield high="3" low="0" name="DATA_TYPE_0" /> -<doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 -= FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 -(4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) -(X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * -(Same as BYTE except has X->Z,Z- >X swap for D3D color def) -(Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 -DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z -= 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit -fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 -[15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit -fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) -9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point -values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) * These -data types use the SIGNED and NORMALIZE flags described -below.</doc> -<bitfield high="7" low="4" name="SKIP_DWORDS_0" /> -<doc>The number of DWORDS to skip (discard) after processing the -current element.</doc> -<bitfield high="12" low="8" name="DST_VEC_LOC_0" /> -<doc>The vector address in the input memory to write this -element</doc> -<bitfield high="13" low="13" name="LAST_VEC_0" /> -<doc>If set, indicates the last vector of the current vertex -stream</doc> -<bitfield high="14" low="14" name="SIGNED_0" /> -<doc>Determines whether fixed point data types are unsigned (0) or -2`s complement signed (1) data types. See NORMALIZE for complete -description of affect</doc> -<bitfield high="15" low="15" name="NORMALIZE_0"> -<use-enum ref="ENUM185" /> -</bitfield> -<doc>Determines whether the fixed to floating point conversion will -normalize the value (i.e. fixed point value is all fractional bits) -or not (i.e. fixed point value is all integer bits). This table -describes the fixed to float conversion results SIGNED NORMALIZE -FLT RANGE 0 0 0.0 - (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 -0.0 - 1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - -127.0) 1 1 -1.0 - 1.0 where n is the number of bits in the -associated fixed point value For signed, normalize conversion, -since the fixed point range is not evenly distributed around 0, -there are 3 different methods supported by R300. See the -VAP_PSC_SGN_NORM_CNTL description for details.</doc> -<bitfield high="23" low="20" name="SKIP_DWORDS_1" /> -<doc>See SKIP_DWORDS_0</doc> -<bitfield high="28" low="24" name="DST_VEC_LOC_1" /> -<doc>See DST_VEC_LOC_0</doc> -<bitfield high="29" low="29" name="LAST_VEC_1" /> -<doc>See LAST_VEC_0</doc> -<bitfield high="30" low="30" name="SIGNED_1" /> -<doc>See SIGNED_0</doc> -<bitfield high="31" low="31" name="NORMALIZE_1" /> -<doc>See NORMALIZE_0</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x2290" stride="0x0004"> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" -offset="0x0"> -<doc>Programmable Vertex Shader Flow Control Loop Index Register -0</doc> -<bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" /> -<doc>This field stores the automatic loop index register init -value. This is an 8-bit unsigned value 0-255. This field is only -used if the corresponding control flow instruction is a loop.</doc> -<bitfield high="15" low="8" name="PVS_FC_LOOP_STEP_VAL_0" /> -<doc>This field stores the automatic loop index register step -value. This is an 8-bit 2`s comp signed value -128-127. This field -is only used if the corresponding control flow instruction is a -loop.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084"> -<doc>Vertex Fetcher Control</doc> -<bitfield high="3" low="0" name="PRIM_TYPE" /> -<doc>Primitive Type 0 : None (will not trigger Setup Engine to run) -1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 : -Triangle Fan 6 : Triangle Strip 7 : Triangle with wFlags (aka, -Rage128 `Type-2` triangles) * 8-11 : Unused 12 : Line Loop 13 : -Quad List 14 : Quad Strip 15 : Polygon *Encoding 7 indicates -whether a 16-bit word of wFlags is present in the stream of indices -arriving when the VTX_AMODE is programmed as a `0`. The Setup -Engine just steps over the wFlags word; ignoring it. 0 = Stream -contains just indices, as: [ Index1, Index0] [ Index3, Index2] [ -Index5, Index4 ] etc... 1 = Stream contains indices and wFlags: [ -Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ wFlags, -Index5 ] etc...</doc> -<bitfield high="5" low="4" name="PRIM_WALK" /> -<doc>Method of Passing Vertex Data. 0 : State-Based Vertex Data. -(Vertex data and tokens embedded in command stream.) 1 = Indexes -(Indices embedded in command stream; vertex data to be fetched from -memory.) 2 = Vertex List (Vertex data to be fetched from memory.) 3 -= Vertex Data (Vertex data embedded in command stream.)</doc> -<bitfield high="11" low="11" name="INDEX_SIZE" /> -<doc>When set, vertex indices are 32-bits/indx, otherwise, 16- -bits/indx.</doc> -<bitfield high="12" low="12" name="VTX_REUSE_DIS" /> -<doc>When set, vertex reuse is disabled. DO NOT SET unless -PRIM_WALK is Indexes.</doc> -<bitfield high="13" low="13" name="DUAL_INDEX_MODE" /> -<doc>When set, the incoming index is treated as two separate -indices. Bits 23-16 are used as the index for AOS 0 (These are 0 -for 16-bit indices) Bits 15-0 are used as the index for AOS 1-15. -This mode was added specifically for HOS usage</doc> -<bitfield high="31" low="16" name="NUM_VERTICES" /> -<doc>Number of vertices in the command packet.</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0"> -<doc>Vertex Array of Structures Control</doc> -<bitfield high="4" low="0" name="VTX_NUM_ARRAYS" /> -<doc>The number of arrays required to represent the current vertex -type. Each Array is described by the following three fields: -VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> -<bitfield high="5" low="5" name="VC_FORCE_PREFETCH" /> -<doc>Force Vertex Data Pre-fetching. If this bit is set, then a -256-bit word will always be fetched, regardless of which dwords are -needed. Typically useful when VAP_VF_CNTL.PRIM_WALK is set to -Vertex List (Auto-incremented indices).</doc> -<bitfield high="16" low="16" name="AOS_0_FETCH_SIZE" /> -<doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule size 1 = -256-bit granule size This allows the driver to program the fetch -size based on DWORDS/VTX/AOS combined with AGP vs. LOC Memory. The -general belief is that the granule size should always be 256-bits -for LOC memory and AGP8X data, but should be 128-bit for AGP2X/4X -data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc> -<bitfield high="17" low="17" name="AOS_1_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="18" low="18" name="AOS_2_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="19" low="19" name="AOS_3_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="20" low="20" name="AOS_4_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="21" low="21" name="AOS_5_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="22" low="22" name="AOS_6_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="23" low="23" name="AOS_7_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="24" low="24" name="AOS_8_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="25" low="25" name="AOS_9_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="26" low="26" name="AOS_10_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="27" low="27" name="AOS_11_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="28" low="28" name="AOS_12_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="29" low="29" name="AOS_13_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180"> -<doc>VAP Vertex State Control Register</doc> -<bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="3" low="2" name="COLOR_1_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 1 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="5" low="4" name="COLOR_2_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 2 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="7" low="6" name="COLOR_3_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 3 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="9" low="8" name="COLOR_4_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 4 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="11" low="10" name="COLOR_5_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 5 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="13" low="12" name="COLOR_6_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 6 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="15" low="14" name="COLOR_7_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 7 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="16" low="16" name="UPDATE_USER_COLOR_0_ENA" /> -<doc>0 : User Color 0 State is NOT updated when User Color 0 is -written. 1 : User Color 1 State IS updated when User Color 0 is -written.</doc> -<bitfield high="18" low="18" name="USE_ADDR_IND_TBL" /> -<doc>0 : Use vertex state addresses directly to write to vertex -state memory. 1 : Use Address Indirection table to write to vertex -state memory for lower 64 DWORD addresses.</doc> -</reg32> -<stripe length="4" offset="0x2430" stride="0x0004"> -<reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x232C" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x2328" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x2324" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x2470" stride="0x0004"> -<reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x2320" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0" /> -</stripe> -<reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424" /> -<reg32 access="rw" name="VAP_VTX_ST_EDGE_FLAGS" offset="0x245C" /> -<reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" offset="0x24AC" /> -<reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" offset="0x2498" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" offset="0x2310" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" offset="0x2314" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" offset="0x2318" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" offset="0x2450" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" offset="0x2454" /> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" offset="0x2458" /> -<reg32 access="rw" name="VAP_VTX_ST_PNT_SPRT_SZ" offset="0x2420" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" offset="0x230C" /> -<reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" offset="0x2490" /> -<reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" offset="0x24A0" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" offset="0x2300" /> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" offset="0x2494" /> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" offset="0x24A4" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" offset="0x2304" /> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" offset="0x24A8" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" offset="0x2308" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444" /> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448" /> -<reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C" /> -<reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" offset="0x2428" /> -<reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" offset="0x242C" /> -<stripe length="8" offset="0x23AC" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x23A8" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x23A0" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0" /> -</stripe> -<stripe length="8" offset="0x23A4" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0" /> -</stripe> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C" /> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" offset="0x2468" /> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464" /> -<reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" offset="0x249C" /> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460" /> -<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C"> -<doc>Z Buffer Band-Width Control Bit Defa</doc> -<bitfield high="0" low="0" name="HIZ_ENABLE"> -<use-enum ref="ENUM187" /> -</bitfield> -<doc>Enables hierarchical Z.</doc> -<bitfield high="1" low="1" name="HIZ_MIN"> -<use-enum ref="ENUM188" /> -</bitfield> -<doc /> -<bitfield high="2" low="2" name="FAST_FILL"> -<use-enum ref="ENUM189" /> -</bitfield> -<doc /> -<bitfield high="3" low="3" name="RD_COMP_ENABLE"> -<use-enum ref="ENUM190" /> -</bitfield> -<doc>Enables reading of compressed Z data from memory to the -cache.</doc> -<bitfield high="4" low="4" name="WR_COMP_ENABLE"> -<use-enum ref="ENUM191" /> -</bitfield> -<doc>Enables writing of compressed Z data from cache to -memory,</doc> -<bitfield high="5" low="5" name="ZB_CB_CLEAR"> -<use-enum ref="ENUM192" /> -</bitfield> -<doc>This bit is set when the Z buffer is used to help the CB in -clearing a region. Part of the region is cleared by the color -buffer and part will be cleared by the Z buffer. Since the Z buffer -does not have any write masks in the cache, full micro-tiles need -to be written. If a partial micro-tile is touched , then the -un-touched part will be unknowns. The cache will operate in -write-allocate mode and quads will be accumulated in the cache and -then evicted to main memory. The color value is supplied through -the ZB_DEPTHCLEARVALUE register.</doc> -<bitfield high="6" low="6" name="FORCE_COMPRESSED_STENCIL" /> -<doc>Enabling this bit will force all the compressed stencil values -to be</doc> -</reg32> -<reg32 access="rw" name="ZB_CNTL" offset="0x4F00"> -<doc>Z Buffer Control</doc> -<bitfield high="0" low="0" name="STENCIL_ENABLE"> -<use-enum ref="ENUM178" /> -</bitfield> -<doc>Enables stenciling.</doc> -<bitfield high="1" low="1" name="Z_ENABLE"> -<use-enum ref="ENUM178" /> -</bitfield> -<doc>Enables Z functions.</doc> -<bitfield high="2" low="2" name="ZWRITEENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables writing of the Z buffer.</doc> -<bitfield high="3" low="3" name="ZSIGNED_COMPARE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enable signed Z buffer comparison , for W-buffering.</doc> -<bitfield high="4" low="4" name="STENCIL_FRONT_BACK"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK bit to -one specifies that -stencilfunc/stencilfail/stencilzpass/stencilzfail registers are -used if the quad is generated from front faced primitive and -stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf are -used if the quad is generated from a back faced primitive. If the -STENCIL_FRONT_BACK is not set, then -stencilfunc/stencilfail/stencilzpass/stencilzfail registers -determine the operation independent of the front/back face state of -the quad.</doc> -</reg32> -<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10"> -<doc>Format of the Data in the Z buffer</doc> -<bitfield high="3" low="0" name="DEPTHFORMAT"> -<use-enum ref="ENUM196" /> -</bitfield> -<doc>Specifies the format of the Z buffer.</doc> -<bitfield high="4" low="4" name="INVERT"> -<value name="IN_13E3_FORMAT" value="0"> -<doc>in 13E3 format , count leading 0`s</doc> -</value> -<value name="IN_13E3_FORMAT" value="1"> -<doc>in 13E3 format , count leading 1`s.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="5" low="5" name="PEQ8"> -<value name="7_BYTES_PER_PLANE_EQUATION" value="0"> -<doc>7 bytes per plane equation, 1 byte for stencil</doc> -</value> -<value name="8_BYTES_PER_PLANE_EQUATION" value="1"> -<doc>8 bytes per plane equation, no bytes for stencil</doc> -</value> -</bitfield> -<doc>This bit is unused</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44"> -<doc>Hierarchical Z Memory Offset</doc> -<bitfield high="16" low="2" name="HIZ_OFFSET" /> -<doc>DWORD offset into HiZ RAM. A DWORD can hold an 8-bit HiZ value -for 4 blocks, so this offset is aligned on 4 4x4 blocks. In each -pipe, the HIZ RAM DWORD address is generated from a pixel x[11:0] , -y[11:0] as follows: HIZ_DWORD_ADDRESS[13:0] = HIZ_OFFSET[16:3] + -Y[11:3] * HIZ_PITCH[13:5] + X[11:5].</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50"> -<doc>Hierarchical Z Read Index</doc> -<bitfield high="16" low="2" name="HIZ_RDINDEX" /> -<doc>Read index into HiZ RAM. The index must start on a DWORD -boundary. RDINDEX words much like WRINDEX. Every read from -HIZ_DWORD will increment the register by 2.</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48"> -<doc>Hierarchical Z Write Index</doc> -<bitfield high="16" low="2" name="HIZ_WRINDEX" /> -<doc>Self-incrementing write index into the HiZ RAM. Starting write -index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is -written, this index will increment by two DWORD, this due to the -fact that there are 2 pipes and the data is broadcasted to both -pipes. HIZ_OFFSET and HIZ_PITCH are not used to compute read/write -address to HIZ ram, when it is accessed through WRINDEX and -DWORD</doc> -</reg32> -<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04"> -<doc>Z and Stencil Function Control</doc> -<bitfield high="2" low="0" name="ZFUNC"> -<use-enum ref="ENUM202" /> -</bitfield> -<doc>Specifies the Z function.</doc> -<bitfield high="5" low="3" name="STENCILFUNC"> -<use-enum ref="ENUM203" /> -</bitfield> -<doc>Specifies the stencil function.</doc> -<bitfield high="8" low="6" name="STENCILFAIL"> -<use-enum ref="ENUM204" /> -</bitfield> -<doc>Specifies the stencil value to be written if the stencil test -fails.</doc> -<bitfield high="11" low="9" name="STENCILZPASS" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test passes (or is -not enabled).</doc> -<bitfield high="14" low="12" name="STENCILZFAIL" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test fails.</doc> -<bitfield high="17" low="15" name="STENCILFUNC_BF" /> -<doc>Same encoding as STENCILFUNC. Specifies the stencil function -for back faced quads , if STENCIL_FRONT_BACK = 1.</doc> -<bitfield high="20" low="18" name="STENCILFAIL_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test fails for back faced quads, if -STENCIL_FRONT_BACK = 1</doc> -<bitfield high="23" low="21" name="STENCILZPASS_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test passes (or is -not enabled) for back faced quads, if STENCIL_FRONT_BACK = 1</doc> -<bitfield high="26" low="24" name="STENCILZFAIL_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test fails for back -faced quads, if STENCIL_FRONT_BACK =1</doc> -</reg32> -</group> -<group name="r500_regs"> -<reg32 access="r" name="CP_CSQ2_STAT" offset="0x07FC"> -<doc>(RO) Command Stream Indirect Queue 2 Status</doc> -<bitfield high="9" low="0" name="CSQ_WPTR_INDIRECT" /> -<doc>Current Write Pointer into the Indirect Queue. Default = -0.</doc> -<bitfield high="19" low="10" name="CSQ_RPTR_INDIRECT2" /> -<doc>Current Read Pointer into the Indirect Queue. Default = -0.</doc> -<bitfield high="29" low="20" name="CSQ_WPTR_INDIRECT2" /> -<doc>Current Write Pointer into the Indirect Queue. Default = -0.</doc> -</reg32> -<reg32 access="w" name="CP_CSQ_ADDR" offset="0x07F0"> -<doc>(WO) Command Stream Queue Address</doc> -<bitfield high="11" low="2" name="CSQ_ADDR" /> -<doc>Address into the Command Stream Queue which is to be read -from. Used for debug, to read the contents of the Command Stream -Queue.</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_APER_INDIRECT" offset="0x1300"> -<doc>IB1 Aperture map in RBBM - PIO</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_APER_INDIRECT2" offset="0x1200"> -<doc>IB2 Aperture map in RBBM - PIO</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_APER_PRIMARY" offset="0x1000"> -<doc>Primary Aperture map in RBBM - PIO</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_AVAIL" offset="0x07B8"> -<doc>Command Stream Queue Available Counts</doc> -<bitfield high="9" low="0" name="CSQ_CNT_PRIMARY" /> -<doc>Count of available dwords in the queue for the Primary Stream. -Read Only.</doc> -<bitfield high="19" low="10" name="CSQ_CNT_INDIRECT" /> -<doc>Count of available dwords in the queue for the Indirect -Stream. Read Only.</doc> -<bitfield high="29" low="20" name="CSQ_CNT_INDIRECT2" /> -<doc>Count of available dwords in the queue for the Indirect -Stream. Read Only.</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_CNTL" offset="0x0740"> -<doc>Command Stream Queue Control</doc> -<bitfield high="31" low="28" name="CSQ_MODE"> -<value name="PRIMARY_DISABLED" value="0"> -<doc>Primary Disabled, Indirect Disabled.</doc> -</value> -<value name="PRIMARY_PIO" value="1"> -<doc>Primary PIO, Indirect Disabled.</doc> -</value> -<value name="PRIMARY_BM" value="2"> -<doc>Primary BM, Indirect Disabled. 3,5,</doc> -</value> -<value name="PRIMARY_PIO" value="7"> -<doc>Primary PIO, Indirect BM. 4,6,</doc> -</value> -<value name="PRIMARY_BM" value="8"> -<doc>Primary BM, Indirect BM. 9-</doc> -</value> -<value name="PRIMARY_PIO" value="15"> -<doc>Primary PIO, Indirect PIO Default = 0</doc> -</value> -</bitfield> -<doc>Command Stream Queue Mode. Controls whether each command -stream is enabled, and whether it is in push mode (Programmed I/O), -or pull mode (Bus-Master). Encodings are chosen to be compatible -with Rage128. 0= Primary Disabled, Indirect Disabled. 1= Primary -PIO, Indirect Disabled. 2= Primary BM, Indirect Disabled. 3,5,7= -Primary PIO, Indirect BM. 4,6,8= Primary BM, Indirect BM. 9-14= -Reserved. 15= Primary PIO, Indirect PIO Default = 0</doc> -</reg32> -<reg32 access="r" name="CP_CSQ_DATA" offset="0x07F4"> -<doc>(RO) Command Stream Queue Data</doc> -</reg32> -<reg32 access="rw" name="CP_CSQ_MODE" offset="0x0744"> -<doc>Alternate Command Stream Queue Control</doc> -<bitfield high="6" low="0" name="INDIRECT2_START" /> -<doc>Start location of Indirect Queue #2 in the command cache. This -value also sets the size in double octwords of the Indirect Queue -#1 cache that will reside in locations INDIRECT1_START to -(INDIRECT2_START - 1). The Indirect Queue #2 will reside in -locations INDIRECT2_START to 0x5f. The minimum size of the Indirect -Queues must be at least twice the MAX_FETCH size as programmed in -the CP_RB_CNTL register.</doc> -<bitfield high="14" low="8" name="INDIRECT1_START" /> -<doc>Start location of Indirect Queue #1 in the command cache. This -value is also the size in double octwords of the Primary Queue -cache that will reside in locations 0 to (INDIRECT1_START - 1). The -minimum size of the Primary Queue cache must be at least twice the -MAX_FETCH size as programmed in the CP_RB_CNTL register.</doc> -<bitfield high="26" low="26" name="CSQ_INDIRECT2_MODE"> -<use-enum ref="ENUM207" /> -</bitfield> -<doc /> -<bitfield high="27" low="27" name="CSQ_INDIRECT2_ENABLE" /> -<doc>Enables Indirect Buffer #2. If this bit is set, the -CP_CSQ_MODE register overrides the operation of the CSQ_MODE -variable in the CP_CSQ_CNTL register.</doc> -<bitfield high="28" low="28" name="CSQ_INDIRECT1_MODE"> -<use-enum ref="ENUM207" /> -</bitfield> -<doc /> -<bitfield high="29" low="29" name="CSQ_INDIRECT1_ENABLE" /> -<doc>Enables Indirect Buffer #1. If this bit is set, the -CP_CSQ_MODE register overrides the operation of the CSQ_MODE -variable in the CP_CSQ_CNTL register.</doc> -<bitfield high="30" low="30" name="CSQ_PRIMARY_MODE"> -<use-enum ref="ENUM207" /> -</bitfield> -<doc /> -<bitfield high="31" low="31" name="CSQ_PRIMARY_ENABLE" /> -<doc>Enables Primary Buffer. If this bit is set, the CP_CSQ_MODE -register overrides the operation of the CSQ_MODE variable in the -CP_CSQ_CNTL register.</doc> -</reg32> -<reg32 access="r" name="CP_CSQ_STAT" offset="0x07F8"> -<doc>(RO) Command Stream Queue Status</doc> -<bitfield high="9" low="0" name="CSQ_RPTR_PRIMARY" /> -<doc>Current Read Pointer into the Primary Queue. Default = -0.</doc> -<bitfield high="19" low="10" name="CSQ_WPTR_PRIMARY" /> -<doc>Current Write Pointer into the Primary Queue. Default = -0.</doc> -<bitfield high="29" low="20" name="CSQ_RPTR_INDIRECT" /> -<doc>Current Read Pointer into the Indirect Queue. Default = -0.</doc> -</reg32> -<reg32 access="rw" name="CP_GUI_COMMAND" offset="0x0728"> -<doc>Command for PIO GUI DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_GUI_DST_ADDR" offset="0x0724"> -<doc>Destination Address for PIO GUI DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_GUI_SRC_ADDR" offset="0x0720"> -<doc>Source Address for PIO GUI DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_IB2_BASE" offset="0x0730"> -<doc>Indirect Buffer 2 Base</doc> -<bitfield high="31" low="2" name="IB2_BASE" /> -<doc>Indirect Buffer 2 Base. Address of the beginning of the -indirect buffer. Only DWORD access is allowed to this -register.</doc> -</reg32> -<reg32 access="rw" name="CP_IB2_BUFSZ" offset="0x0734"> -<doc>Indirect Buffer 2 Size</doc> -<bitfield high="22" low="0" name="IB2_BUFSZ" /> -<doc>Indirect Buffer 2 Size. This size is expressed in dwords. This -field is an initiator to begin fetching commands from the Indirect -Buffer. Only DWORD access is allowed to this register. Default = -0</doc> -</reg32> -<reg32 access="rw" name="CP_IB_BASE" offset="0x0738"> -<doc>Indirect Buffer Base</doc> -<bitfield high="31" low="2" name="IB_BASE" /> -<doc>Indirect Buffer Base. Address of the beginning of the indirect -buffer. Only DWORD access is allowed to this register.</doc> -</reg32> -<reg32 access="rw" name="CP_IB_BUFSZ" offset="0x073C"> -<doc>Indirect Buffer Size</doc> -<bitfield high="22" low="0" name="IB_BUFSZ" /> -<doc>Indirect Buffer Size. This size is expressed in dwords. This -field is an initiator to begin fetching commands from the Indirect -Buffer. Only DWORD access is allowed to this register. Default = -0</doc> -</reg32> -<reg32 access="rw" name="CP_ME_CNTL" offset="0x07D0"> -<doc>Micro Engine Control</doc> -<bitfield high="15" low="0" name="ME_STAT" /> -<doc>Status of MicroEngine internal registers. This value depends -on the current value of the ME_STATMUX field. Read Only.</doc> -<bitfield high="20" low="16" name="ME_STATMUX" /> -<doc>Selects which status is to be returned on the ME_STAT -field.</doc> -<bitfield high="29" low="29" name="ME_BUSY" /> -<doc>Busy indicator for the MicroEngine. 0 = MicroEngine not busy. -1 = MicroEngine is active. Read Only.</doc> -<bitfield high="30" low="30" name="ME_MODE" /> -<doc>Run-Mode of MicroEngine. 0 = Single-Step Mode. 1 = -Free-running Mode. Default = 1</doc> -<bitfield high="31" low="31" name="ME_STEP" /> -<doc>Step the MicroEngine by one instruction. Writing a `1` to this -field causes the MicroEngine to step by one instruction, if and -only if the ME_MODE bit is a `0`. Write Only.</doc> -</reg32> -<reg32 access="rw" name="CP_ME_RAM_ADDR" offset="0x07D4"> -<doc>MicroEngine RAM Address</doc> -<bitfield high="7" low="0" name="ME_RAM_ADDR" /> -<doc>MicroEngine RAM Address (Write Mode) Writing this</doc> -</reg32> -<reg32 access="rw" name="CP_ME_RAM_DATAH" offset="0x07DC"> -<doc>MicroEngine RAM Data High</doc> -<bitfield high="7" low="0" name="ME_RAM_DATAH" /> -<doc>MicroEngine RAM Data High Used to load the MicroEngine -RAM.</doc> -</reg32> -<reg32 access="rw" name="CP_ME_RAM_DATAL" offset="0x07E0"> -<doc>MicroEngine RAM Data Low</doc> -</reg32> -<reg32 access="rw" name="CP_ME_RAM_RADDR" offset="0x07D8"> -<doc>MicroEngine RAM Read Address</doc> -<bitfield high="7" low="0" name="ME_RAM_RADDR" /> -<doc>MicroEngine RAM Address (Read Mode) Writing</doc> -</reg32> -<reg32 access="rw" name="CP_RB_BASE" offset="0x0700"> -<doc>Ring Buffer Base</doc> -<bitfield high="31" low="2" name="RB_BASE" /> -<doc>Ring Buffer Base. Address of the beginning of the ring -buffer.</doc> -</reg32> -<reg32 access="rw" name="CP_RB_CNTL" offset="0x0704"> -<doc>Ring Buffer Control</doc> -<bitfield high="5" low="0" name="RB_BUFSZ" /> -<doc>Ring Buffer Size. This size is expressed in log2 of the actual -size. Values 0 and 1 are clamped to an 8 DWORD ring buffer. A value -of 2 to 22 will give a ring buffer: 2^(RB_BUFSZ+1). Values greater -than 22 will clamp to 22. Default = 0</doc> -<bitfield high="13" low="8" name="RB_BLKSZ" /> -<doc>Ring Buffer Block Size. This defines the number of quadwords -that the Command Processor will read between updates to the host`s -copy of the Read Pointer. This size is expressed in log2 of the -actual size (in 64-bit quadwords). For example, for a block of 1024 -quadwords, you would program this field to 10(decimal). Default = -0</doc> -<bitfield high="17" low="16" name="BUF_SWAP" /> -<doc>Endian Swap Control for Ring Buffer and Indirect Buffer. Only -affects the chip behavior if the buffer resides in system memory. 0 -= No swap 1 = 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit -swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD -becomes 0xCCDDAABB Default = 0</doc> -<bitfield high="19" low="18" name="MAX_FETCH" /> -<doc>Maximum Fetch Size for any read request that the CP makes to -memory. 0 = 1 double octword. (32 bytes) 1 = 2 double octwords. (64 -bytes) 2 = 4 double octwords. (128 bytes) 3 = 8 double octwords. -(256 bytes). Default =0</doc> -<bitfield high="27" low="27" name="RB_NO_UPDATE"> -<value name="WRITE_TO_HOST" value="0"> -<doc>Write to Host`s copy of Read Pointer in system memory.</doc> -</value> -<value name="DO_NOT_WRITE_TO_HOST" value="1"> -<doc>Do not write to Host`s copy of Read pointer. The purpose of -this control bit is to have a fall-back position if the bus- -mastered write to system memory doesn`t work, in which case the -driver will have to read the Graphics Controller`s copy of the Read -Pointer directly, with some performance penalty. Default = 0</doc> -</value> -</bitfield> -<doc>Ring Buffer No Write to Read Pointer 0= Write to Host`s copy -of Read Pointer in system memory. 1= Do not write to Host`s copy of -Read pointer. The purpose of this control bit is to have a -fall-back position if the bus- mastered write to system memory -doesn`t work, in which case the driver will have to read the -Graphics Controller`s copy of the Read Pointer directly, with some -performance penalty. Default = 0</doc> -<bitfield high="31" low="31" name="RB_RPTR_WR_ENA" /> -<doc>Ring Buffer Read Pointer Write Transfer Enable. When set the -contents of the CP_RB_RPTR_WR register is transferred to the active -read pointer (CP_RB_RPTR) whenever the CP_RB_WPTR register is -written. Default =0</doc> -</reg32> -<reg32 access="rw" name="CP_RB_RPTR" offset="0x0710"> -<doc>Ring Buffer Read Pointer Address (RO)</doc> -<bitfield high="22" low="0" name="RB_RPTR" /> -<doc>Ring Buffer Read Pointer. This is an index (in dwords) of the -current element being read from the ring buffer.</doc> -</reg32> -<reg32 access="rw" name="CP_RB_RPTR_ADDR" offset="0x070C"> -<doc>Ring Buffer Read Pointer Address</doc> -<bitfield high="1" low="0" name="RB_RPTR_SWAP" /> -<doc>Swap control of the reported read pointer address. See -CP_RB_CNTL.BUF_SWAP for the encoding.</doc> -<bitfield high="31" low="2" name="RB_RPTR_ADDR" /> -<doc>Ring Buffer Read Pointer Address. Address of the Host`s copy -of the Read Pointer. CP_RB_RPTR (RO) Ring Buffer Read Pointer</doc> -</reg32> -<reg32 access="rw" name="CP_RB_RPTR_WR" offset="0x071C"> -<doc>Writable Ring Buffer Read Pointer Address</doc> -<bitfield high="22" low="0" name="RB_RPTR_WR" /> -<doc>Writable Ring Buffer Read Pointer. Writable for updating the -RB_RPTR after an ACPI.</doc> -</reg32> -<reg32 access="rw" name="CP_RB_WPTR" offset="0x0714"> -<doc>(RO) Ring Buffer Write Pointer</doc> -<bitfield high="22" low="0" name="RB_WPTR" /> -<doc>Ring Buffer Write Pointer. This is an index (in dwords) of the -last known element to be written to the ring buffer (by the -host).</doc> -</reg32> -<reg32 access="rw" name="CP_RB_WPTR_DELAY" offset="0x0718"> -<doc>Ring Buffer Write Pointer Delay</doc> -<bitfield high="27" low="0" name="PRE_WRITE_TIMER" /> -<doc>Pre-Write Timer. The number of clocks that a write to the -CP_RB_WPTR register will be delayed until actually taking effect. -Default = 0</doc> -<bitfield high="31" low="28" name="PRE_WRITE_LIMIT" /> -<doc>Pre-Write Limit. The number of times that the CP_RB_WPTR -register can be written (while the PRE_WRITE_TIMER has not expired) -before the CP_RB_WPTR register is forced to be updated with the -most recently written value. Default = 0</doc> -</reg32> -<reg32 access="rw" name="CP_RESYNC_ADDR" offset="0x0778"> -<doc>Raster Engine Sync Address (WO)</doc> -<bitfield high="2" low="0" name="RESYNC_ADDR" /> -<doc>Scratch Register Offset Address.</doc> -</reg32> -<reg32 access="rw" name="CP_RESYNC_DATA" offset="0x077C"> -<doc>Raster Engine Sync Data (WO)</doc> -</reg32> -<reg32 access="r" name="CP_STAT" offset="0x07C0"> -<doc>(RO) Busy Status Signals</doc> -<bitfield high="0" low="0" name="MRU_BUSY" /> -<doc>Memory Read Unit Busy.</doc> -<bitfield high="1" low="1" name="MWU_BUSY" /> -<doc>Memory Write Unit Busy.</doc> -<bitfield high="2" low="2" name="RSIU_BUSY" /> -<doc>Register Backbone Input Interface Busy.</doc> -<bitfield high="3" low="3" name="RCIU_BUSY" /> -<doc>RBBM Output Interface Busy.</doc> -<bitfield high="9" low="9" name="CSF_PRIMARY_BUSY" /> -<doc>Primary Command Stream Fetcher Busy.</doc> -<bitfield high="10" low="10" name="CSF_INDIRECT_BUSY" /> -<doc>Indirect #1 Command Stream Fetcher Busy.</doc> -<bitfield high="11" low="11" name="CSQ_PRIMARY_BUSY" /> -<doc>Data in Command Queue for Primary Stream.</doc> -<bitfield high="12" low="12" name="CSQ_INDIRECT_BUSY" /> -<doc>Data in Command Queue for Indirect #1 Stream.</doc> -<bitfield high="13" low="13" name="CSI_BUSY" /> -<doc>Command Stream Interpreter Busy.</doc> -<bitfield high="14" low="14" name="CSF_INDIRECT2_BUSY" /> -<doc>Indirect #2 Command Stream Fetcher Busy.</doc> -<bitfield high="15" low="15" name="CSQ_INDIRECT2_BUSY" /> -<doc>Data in Command Queue for Indirect #2 Stream.</doc> -<bitfield high="28" low="28" name="GUIDMA_BUSY" /> -<doc>GUI DMA Engine Busy.</doc> -<bitfield high="29" low="29" name="VIDDMA_BUSY" /> -<doc>VID DMA Engine Busy.</doc> -<bitfield high="30" low="30" name="CMDSTRM_BUSY" /> -<doc>Command Stream Busy.</doc> -<bitfield high="31" low="31" name="CP_BUSY" /> -<doc>CP Busy.</doc> -</reg32> -<reg32 access="rw" name="CP_VID_COMMAND" offset="0x07CC"> -<doc>Command for PIO VID DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_VID_DST_ADDR" offset="0x07C8"> -<doc>Destination Address for PIO VID DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_VID_SRC_ADDR" offset="0x07C4"> -<doc>Source Address for PIO VID DMAs</doc> -</reg32> -<reg32 access="rw" name="CP_VP_ADDR_CNTL" offset="0x07E8"> -<doc>Virtual vs Physical Address Control - Selects whether the -address corresponds to a physical or virtual address in -memory.</doc> -<bitfield high="0" low="0" name="SCRATCH_ALT_VP_WR"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="1" low="1" name="SCRATCH_VP_WR"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="2" low="2" name="RPTR_VP_UPDATE"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="3" low="3" name="VIDDMA_VP_WR"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="4" low="4" name="VIDDMA_VP_RD"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="5" low="5" name="GUIDMA_VP_WR"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="6" low="6" name="GUIDMA_VP_RD"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="7" low="7" name="INDR2_VP_FETCH"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="8" low="8" name="INDR1_VP_FETCH"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -<bitfield high="9" low="9" name="RING_VP_FETCH"> -<use-enum ref="ENUM209" /> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88"> -<doc>Resolve Buffer Control. Unpipelined</doc> -<bitfield high="0" low="0" name="AARESOLVE_MODE" /> -<doc>Specifies if the color buffer is in resolve mode. The cache -must be empty before changing this register.</doc> -<bitfield high="1" low="1" name="AARESOLVE_GAMMA"> -<use-enum ref="ENUM1" /> -</bitfield> -<doc>Specifies the gamma and degamma to be applied to the samples -before and after filtering, respectively.</doc> -<bitfield high="2" low="2" name="AARESOLVE_ALPHA"> -<value name="RESOLVED_ALPHA_VALUE_IS_TAKEN_FROM_SAMPLE_0" -value="0"> -<doc>Resolved alpha value is taken from sample 0.</doc> -</value> -<value name="RESOLVED_ALPHA_VALUE_IS_THE_AVERAGE_OF_THE_SAMPLES" -value="1"> -<doc>Resolved alpha value is the average of the samples. The -average is not gamma corrected.</doc> -</value> -</bitfield> -<doc>Controls whether alpha is averaged in the resolve. 0 => the -resolved alpha value is selected from the sample 0 value. 1=> -the resolved alpha value is a filtered (average) result of of the -samples.</doc> -</reg32> -<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04"> -<doc>Alpha Blend Control for Color Channels. Pipelined through the -blender.</doc> -<bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Allow alpha blending with the destination.</doc> -<bitfield high="1" low="1" name="SEPARATE_ALPHA_ENABLE"> -<use-enum ref="ENUM6" /> -</bitfield> -<doc>Enables use of RB3D_ABLENDCNTL</doc> -<bitfield high="2" low="2" name="READ_ENABLE"> -<use-enum ref="ENUM7" /> -</bitfield> -<doc>When blending is enabled, this enables memory reads. Memory -reads will still occur when this is disabled if they are for -reasons not related to blending.</doc> -<bitfield high="5" low="3" name="DISCARD_SRC_PIXELS"> -<value name="DISABLE" value="0"> -<doc>Disable</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="1"> -<doc>Discard pixels if src alpha <= -RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_COLOR" value="2"> -<doc>Discard pixels if src color <= -RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ARGB" value="3"> -<doc>Discard pixels if src argb <= -RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="4"> -<doc>Discard pixels if src alpha >= -RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_COLOR" value="5"> -<doc>Discard pixels if src color >= -RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> -</value> -<value name="DISCARD_PIXELS_IF_SRC_ARGB" value="6"> -<doc>Discard pixels if src argb >= -RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> -</value> -</bitfield> -<doc>Discard pixels when blending is enabled based on the src -color.</doc> -<bitfield high="14" low="12" name="COMB_FCN"> -<use-enum ref="ENUM2" /> -</bitfield> -<doc>Combine Function , Allows modification of how the SRCBLEND and -DESTBLEND are combined.</doc> -<bitfield high="21" low="16" name="SRCBLEND"> -<use-enum ref="ENUM3" /> -</bitfield> -<doc>Source Blend Function , Alpha blending function (SRC).</doc> -<bitfield high="29" low="24" name="DESTBLEND"> -<use-enum ref="ENUM4" /> -</bitfield> -<doc>Destination Blend Function , Alpha blending function -(DST).</doc> -<bitfield high="30" low="30" name="SRC_ALPHA_0_NO_READ"> -<value name="DISABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" -value="0"> -<doc>Disable source alpha zero performance optimization to skip -reads</doc> -</value> -<value name="ENABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" -value="1"> -<doc>Enable source alpha zero performance optimization to skip -reads</doc> -</value> -</bitfield> -<doc>Enables source alpha zero performance optimization to skip -reads.</doc> -<bitfield high="31" low="31" name="SRC_ALPHA_1_NO_READ"> -<value name="DISABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" -value="0"> -<doc>Disable source alpha one performance optimization to skip -reads</doc> -</value> -<value name="ENABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" -value="1"> -<doc>Enable source alpha one performance optimization to skip -reads</doc> -</value> -</bitfield> -<doc>Enables source alpha one performance optimization to skip -reads.</doc> -</reg32> -<reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD" -offset="0x4EA4"> -<doc>Discard src pixels greater than or equal to threshold.</doc> -<bitfield high="7" low="0" name="BLUE" /> -<doc>Blue</doc> -<bitfield high="15" low="8" name="GREEN" /> -<doc>Green</doc> -<bitfield high="23" low="16" name="RED" /> -<doc>Red</doc> -<bitfield high="31" low="24" name="ALPHA" /> -<doc>Alpha</doc> -</reg32> -<reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD" -offset="0x4EA0"> -<doc>Discard src pixels less than or equal to threshold.</doc> -<bitfield high="7" low="0" name="BLUE" /> -<doc>Blue</doc> -<bitfield high="15" low="8" name="GREEN" /> -<doc>Green</doc> -<bitfield high="23" low="16" name="RED" /> -<doc>Red</doc> -<bitfield high="31" low="24" name="ALPHA" /> -<doc>Alpha</doc> -</reg32> -<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00"> -<doc>Unpipelined.</doc> -<bitfield high="6" low="5" name="NUM_MULTIWRITES"> -<use-enum ref="ENUM9" /> -</bitfield> -<doc>A quad is replicated and written to this many buffers.</doc> -<bitfield high="7" low="7" name="CLRCMP_FLIPE_ENABLE"> -<use-enum ref="ENUM10" /> -</bitfield> -<doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. -This is used to ensure 3D data does not get chromakeyed away by -logic in the backend.</doc> -<bitfield high="9" low="9" name="AA_COMPRESSION_ENABLE"> -<use-enum ref="ENUM11" /> -</bitfield> -<doc>Enables AA color compression. Cmask must also be enabled when -aa compression is enabled. The cache must be empty before this is -changed.</doc> -<bitfield high="10" low="10" name="CMASK_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables use of the cmask ram. The cache must be empty before -this is changed.</doc> -<bitfield high="11" low="11" name="Reserved" /> -<doc>Set to 0</doc> -<bitfield high="12" low="12" -name="INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables indepedent color channel masks for the MRTs. Disabling -this feature will cause all the MRTs to use color channel mask -0.</doc> -<bitfield high="13" low="13" name="WRITE_COMPRESSION_DISABLE"> -<value name="ENABLE_WRITE_COMPRESSION" value="0"> -<doc>Enable write compression</doc> -</value> -<value name="DISABLE_WRITE_COMPRESSION" value="1"> -<doc>Disable write compression</doc> -</value> -</bitfield> -<doc>Disables write compression.</doc> -<bitfield high="14" low="14" name="INDEPENDENT_COLORFORMAT_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables independent color format for the MRTs. Disabling this -feature will cause all the MRTs to use color format 0.</doc> -</reg32> -<stripe length="4" offset="0x4E38" stride="0x0004"> -<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0"> -<doc>Color buffer format and tiling control for all the -multibuffers and the pitch of multibuffer 0. Unpipelined. The cache -must be empty before any of the registers are changed.</doc> -<bitfield high="13" low="1" name="COLORPITCH" /> -<doc>3D destination pitch in multiples of 2-pixels.</doc> -<bitfield high="16" low="16" name="COLORTILE"> -<use-enum ref="ENUM12" /> -</bitfield> -<doc>Denotes whether the 3D destination is in macrotiled -format.</doc> -<bitfield high="18" low="17" name="COLORMICROTILE"> -<use-enum ref="ENUM13" /> -</bitfield> -<doc>Denotes whether the 3D destination is in microtiled -format.</doc> -<bitfield high="20" low="19" name="COLORENDIAN"> -<use-enum ref="ENUM14" /> -</bitfield> -<doc>Specifies endian control for the color buffer.</doc> -<bitfield high="24" low="21" name="COLORFORMAT"> -<value name="ARGB10101010" value="0"> -<doc>ARGB10101010</doc> -</value> -<value name="UV1010" value="1"> -<doc>UV1010</doc> -</value> -<value name="CI8" value="2"> -<doc>CI8 (2D ONLY)</doc> -</value> -<value name="ARGB1555" value="3"> -<doc>ARGB1555</doc> -</value> -<value name="RGB565" value="4"> -<doc>RGB565</doc> -</value> -<value name="ARGB2101010" value="5"> -<doc>ARGB2101010</doc> -</value> -<value name="ARGB8888" value="6"> -<doc>ARGB8888</doc> -</value> -<value name="ARGB32323232" value="7"> -<doc>ARGB32323232</doc> -</value> -<value name="I8" value="9"> -<doc>I8</doc> -</value> -<value name="ARGB16161616" value="10"> -<doc>ARGB16161616</doc> -</value> -<value name="YUV422_PACKED" value="11"> -<doc>YUV422 packed (VYUY)</doc> -</value> -<value name="YUV422_PACKED" value="12"> -<doc>YUV422 packed (YVYU)</doc> -</value> -<value name="UV88" value="13"> -<doc>UV88</doc> -</value> -<value name="I10" value="14"> -<doc>I10</doc> -</value> -<value name="ARGB4444" value="15"> -<doc>ARGB4444</doc> -</value> -</bitfield> -<doc>3D destination color format.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" offset="0x4E0C"> -<doc>3D Color Channel Mask. If all the channels used in the current -color format are disabled, then the cb will discard all the -incoming quads. Pipelined through the blender.</doc> -<bitfield high="0" low="0" name="BLUE_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the blue channel</doc> -<bitfield high="1" low="1" name="GREEN_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the green channel</doc> -<bitfield high="2" low="2" name="RED_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the red channel</doc> -<bitfield high="3" low="3" name="ALPHA_MASK"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the alpha channel</doc> -<bitfield high="4" low="4" name="BLUE_MASK1"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the blue channel of MRT 1</doc> -<bitfield high="5" low="5" name="GREEN_MASK1"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the green channel of MRT 1</doc> -<bitfield high="6" low="6" name="RED_MASK1"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the red channel of MRT 1</doc> -<bitfield high="7" low="7" name="ALPHA_MASK1"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the alpha channel of MRT 1</doc> -<bitfield high="8" low="8" name="BLUE_MASK2"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the blue channel of MRT 2</doc> -<bitfield high="9" low="9" name="GREEN_MASK2"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the green channel of MRT 2</doc> -<bitfield high="10" low="10" name="RED_MASK2"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the red channel of MRT 2</doc> -<bitfield high="11" low="11" name="ALPHA_MASK2"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the alpha channel of MRT 2</doc> -<bitfield high="12" low="12" name="BLUE_MASK3"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the blue channel of MRT 3</doc> -<bitfield high="13" low="13" name="GREEN_MASK3"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the green channel of MRT 3</doc> -<bitfield high="14" low="14" name="RED_MASK3"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the red channel of MRT 3</doc> -<bitfield high="15" low="15" name="ALPHA_MASK3"> -<use-enum ref="ENUM16" /> -</bitfield> -<doc>mask bit for the alpha channel of MRT 3</doc> -</reg32> -<reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" offset="0x4E14"> -<doc>Clear color that is used when the color mask is set to 00. -Unpipelined. Program this register with a 32-bit value in ARGB8888 -or ARGB2101010 formats, ignoring the fields.</doc> -<bitfield high="7" low="0" name="BLUE" /> -<doc>blue clear color</doc> -<bitfield high="15" low="8" name="GREEN" /> -<doc>green clear color</doc> -<bitfield high="23" low="16" name="RED" /> -<doc>red clear color</doc> -<bitfield high="31" low="24" name="ALPHA" /> -<doc>alpha clear color</doc> -</reg32> -<reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_AR" -offset="0x46C0"> -<doc>Alpha and red clear color values that are used when the color -mask is set to 00 in FP16 per component mode. Unpipelined.</doc> -<bitfield high="15" low="0" name="RED" /> -<doc>red clear color</doc> -<bitfield high="31" low="16" name="ALPHA" /> -<doc>alpha clear color</doc> -</reg32> -<reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_GB" -offset="0x46C4"> -<doc>Green and blue clear color values that are used when the color -mask is set to 00 in FP16 per component mode. Unpipelined.</doc> -<bitfield high="15" low="0" name="BLUE" /> -<doc>blue clear color</doc> -<bitfield high="31" low="16" name="GREEN" /> -<doc>green clear color</doc> -</reg32> -<reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10"> -<doc>Constant color used by the blender. Pipelined through the -blender.</doc> -<bitfield high="7" low="0" name="BLUE" /> -<doc>blue constant color (For R520, this field is ignored, use -RB3D_CONSTANT_COLOR_GB__BLUE instead)</doc> -<bitfield high="15" low="8" name="GREEN" /> -<doc>green constant color (For R520, this field is ignored, use -RB3D_CONSTANT_COLOR_GB__GREEN instead)</doc> -<bitfield high="23" low="16" name="RED" /> -<doc>red constant color (For R520, this field is ignored, use -RB3D_CONSTANT_COLOR_AR__RED instead)</doc> -<bitfield high="31" low="24" name="ALPHA" /> -<doc>alpha constant color (For R520, this field is ignored, use -RB3D_CONSTANT_COLOR_AR__ALPHA instead)</doc> -</reg32> -<reg32 access="rw" name="RB3D_CONSTANT_COLOR_AR" offset="0x4EF8"> -<doc>Constant color used by the blender. Pipelined through the -blender.</doc> -<bitfield high="15" low="0" name="RED" /> -<doc>red constant color in 0.10 fixed or FP16 format</doc> -<bitfield high="31" low="16" name="ALPHA" /> -<doc>alpha constant color in 0.10 fixed or FP16 format</doc> -</reg32> -<reg32 access="rw" name="RB3D_CONSTANT_COLOR_GB" offset="0x4EFC"> -<doc>Constant color used by the blender. Pipelined through the -blender.</doc> -<bitfield high="15" low="0" name="BLUE" /> -<doc>blue constant color in 0.10 fixed or FP16 format</doc> -<bitfield high="31" low="16" name="GREEN" /> -<doc>green constant color in 0.10 fixed or FP16 format</doc> -</reg32> -<reg32 access="rw" name="RB3D_FIFO_SIZE" offset="0x4EF4"> -<doc>Sets the fifo sizes</doc> -<bitfield high="1" low="0" name="OP_FIFO_SIZE"> -<use-enum ref="ENUM216" /> -</bitfield> -<doc>Determines the size of the op fifo</doc> -</reg32> -<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4"> -<doc>Alpha Function</doc> -<bitfield high="7" low="0" name="AF_VAL" /> -<doc>Specifies the 8-bit alpha compare value when AF_EN_8BIT is -enabled</doc> -<bitfield high="10" low="8" name="AF_FUNC"> -<use-enum ref="ENUM22" /> -</bitfield> -<doc>Specifies the alpha compare function.</doc> -<bitfield high="11" low="11" name="AF_EN"> -<use-enum ref="ENUM23" /> -</bitfield> -<doc>Enables/Disables alpha compare function.</doc> -<bitfield high="12" low="12" name="AF_EN_8BIT"> -<value name="DEFAULT_10" value="0"> -<doc>Default 10-bit alpha compare.</doc> -</value> -<value name="ENABLE_8" value="1"> -<doc>Enable 8-bit alpha compare.</doc> -</value> -</bitfield> -<doc>Enable 8-bit alpha compare function.</doc> -<bitfield high="16" low="16" name="AM_EN"> -<use-enum ref="ENUM24" /> -</bitfield> -<doc>Enables/Disables alpha-to-mask function.</doc> -<bitfield high="17" low="17" name="AM_CFG"> -<use-enum ref="ENUM25" /> -</bitfield> -<doc>Specfies number of sub-pixel samples for alpha-to-mask -function.</doc> -<bitfield high="20" low="20" name="DITH_EN"> -<use-enum ref="ENUM26" /> -</bitfield> -<doc>Enables/Disables RGB Dithering (Not supported in R520)</doc> -<bitfield high="24" low="24" name="ALP_OFF_EN"> -<value name="DISABLES_ALPHA_OFFSET_OF_2" value="0"> -<doc>Disables alpha offset of 2 (default r300 & rv350 -behavior)</doc> -</value> -<value name="ENABLES_OFFSET_OF_2_ON_ALPHA_COMING_IN_FROM_THE_US" -value="1"> -<doc>Enables offset of 2 on alpha coming in from the US</doc> -</value> -</bitfield> -<doc>Alpha offset enable/disable (Not supported in R520)</doc> -<bitfield high="25" low="25" name="DISCARD_ZERO_MASK_QUAD"> -<value name="NO_DISCARD_OF_ZERO_COVERAGE_MASK_QUADS" value="0"> -<doc>No discard of zero coverage mask quads</doc> -</value> -<value name="DISCARD_ZERO_COVERAGE_MASK_QUADS" value="1"> -<doc>Discard zero coverage mask quads</doc> -</value> -</bitfield> -<doc>Enable/Disable discard zero mask coverage quad to ZB</doc> -<bitfield high="28" low="28" name="FP16_ENABLE"> -<value name="DEFAULT_10" value="0"> -<doc>Default 10-bit alpha compare and alpha-to-mask function</doc> -</value> -<value name="ENABLE_FP16_ALPHA_COMPARE_AND_ALPHA" value="1"> -<doc>Enable FP16 alpha compare and alpha-to-mask function</doc> -</value> -</bitfield> -<doc>Enables/Disables FP16 alpha function</doc> -</reg32> -<reg32 access="rw" name="FG_ALPHA_VALUE" offset="0x4BE0"> -<doc>Alpha Compare Value</doc> -<bitfield high="15" low="0" name="AF_VAL" /> -<doc>Specifies the alpha compare value, 0.10 fixed or FP16 -format</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0"> -<doc>Blue Component of Fog Color</doc> -<bitfield high="9" low="0" name="BLUE" /> -<doc>Blue component of fog color; (0.10) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC"> -<doc>Green Component of Fog Color</doc> -<bitfield high="9" low="0" name="GREEN" /> -<doc>Green component of fog color; (0.10) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8"> -<doc>Red Component of Fog Color</doc> -<bitfield high="9" low="0" name="RED" /> -<doc>Red component of fog color; (0.10) fixed format.</doc> -</reg32> -<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4"> -<doc>Constant Factor for Fog Blending</doc> -<bitfield high="9" low="0" name="FACTOR" /> -<doc>Constant fog factor; fixed (0.10) format.</doc> -</reg32> -<reg32 access="rw" name="GA_COLOR_CONTROL_PS3" offset="0x4258"> -<doc>Specifies color properties and mappings of textures.</doc> -<bitfield high="1" low="0" name="TEX0_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="3" low="2" name="TEX1_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="5" low="4" name="TEX2_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="7" low="6" name="TEX3_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="9" low="8" name="TEX4_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="11" low="10" name="TEX5_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="13" low="12" name="TEX6_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="15" low="14" name="TEX7_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="17" low="16" name="TEX8_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="19" low="18" name="TEX9_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -each texture.</doc> -<bitfield high="21" low="20" name="TEX10_SHADING_PS3"> -<use-enum ref="ENUM30" /> -</bitfield> -<doc>Specifies undefined(0), flat(1) and Gouraud(2/def) shading for -tex10 components.</doc> -<bitfield high="25" low="22" name="COLOR0_TEX_OVERRIDE"> -<use-enum ref="ENUM221" /> -</bitfield> -<doc>Specifies if each color should come from a texture and which -one.</doc> -<bitfield high="29" low="26" name="COLOR1_TEX_OVERRIDE"> -<use-enum ref="ENUM221" /> -</bitfield> -<doc>Specifies if each color should come from a texture and which -one.</doc> -</reg32> -<reg32 access="rw" name="GA_ENHANCE" offset="0x4274"> -<doc>GA Enhancement Register</doc> -<bitfield high="0" low="0" name="DEADLOCK_CNTL"> -<use-enum ref="ENUM32" /> -</bitfield> -<doc>TCL/GA Deadlock control.</doc> -<bitfield high="1" low="1" name="FASTSYNC_CNTL"> -<use-enum ref="ENUM33" /> -</bitfield> -<doc>Enables Fast register/primitive switching</doc> -<bitfield high="2" low="2" name="REG_READWRITE"> -<value name="NO_EFFECT" value="0"> -<doc>No effect.</doc> -</value> -<value name="ENABLES_GA_SUPPORT_OF_SIMULTANEOUS_REGISTER_READS_AND_WRITES" -value="1"> -<doc>Enables GA support of simultaneous register reads and -writes.</doc> -</value> -</bitfield> -<doc>R520+: When set, GA supports simultaneous register reads & -writes</doc> -<bitfield high="3" low="3" name="REG_NOSTALL"> -<value name="NO_EFFECT" value="0"> -<doc>No effect.</doc> -</value> -<value name="ENABLES_GA_SUPPORT_OF_NO" value="1"> -<doc>Enables GA support of no-stall reads for register read -back.</doc> -</value> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="GA_FIFO_CNTL" offset="0x4270"> -<doc>GA Input fifo high water marks</doc> -<bitfield high="2" low="0" name="VERTEX_FIFO" /> -<doc>Number of words remaining in input vertex fifo before -asserting nearly full</doc> -<bitfield high="5" low="3" name="INDEX_FIFO" /> -<doc>Number of words remaining in input primitive fifo before -asserting nearly full</doc> -<bitfield high="13" low="6" name="REG_FIFO" /> -<doc>Number of words remaining in input register fifo before -asserting nearly full</doc> -</reg32> -<reg32 access="rw" name="GA_FILL_A" offset="0x422C"> -<doc>Alpha fill color</doc> -</reg32> -<reg32 access="rw" name="GA_FILL_B" offset="0x4228"> -<doc>Blue fill color</doc> -</reg32> -<reg32 access="rw" name="GA_FILL_G" offset="0x4224"> -<doc>Green fill color</doc> -</reg32> -<reg32 access="rw" name="GA_FILL_R" offset="0x4220"> -<doc>Red fill color</doc> -</reg32> -<reg32 access="rw" name="GA_IDLE" offset="0x425C"> -<doc>Returns idle status of various G3D block, captured when -GA_IDLE written or when hard or soft reset asserted.</doc> -<bitfield high="0" low="0" name="PIPE3_Z_IDLE" /> -<doc>Idle status of physical pipe 3 Z unit</doc> -<bitfield high="1" low="1" name="PIPE2_Z_IDLE" /> -<doc>Idle status of physical pipe 2 Z unit</doc> -<bitfield high="2" low="2" name="PIPE3_CB_IDLE" /> -<doc>Idle status of physical pipe 3 CB unit</doc> -<bitfield high="3" low="3" name="PIPE2_CB_IDLE" /> -<doc>Idle status of physical pipe 2 CB unit</doc> -<bitfield high="4" low="4" name="PIPE3_FG_IDLE" /> -<doc>Idle status of physical pipe 3 FG unit</doc> -<bitfield high="5" low="5" name="PIPE2_FG_IDLE" /> -<doc>Idle status of physical pipe 2 FG unit</doc> -<bitfield high="6" low="6" name="PIPE3_US_IDLE" /> -<doc>Idle status of physical pipe 3 US unit</doc> -<bitfield high="7" low="7" name="PIPE2_US_IDLE" /> -<doc>Idle status of physical pipe 2 US unit</doc> -<bitfield high="8" low="8" name="PIPE3_SC_IDLE" /> -<doc>Idle status of physical pipe 3 SC unit</doc> -<bitfield high="9" low="9" name="PIPE2_SC_IDLE" /> -<doc>Idle status of physical pipe 2 SC unit</doc> -<bitfield high="10" low="10" name="PIPE3_RS_IDLE" /> -<doc>Idle status of physical pipe 3 RS unit</doc> -<bitfield high="11" low="11" name="PIPE2_RS_IDLE" /> -<doc>Idle status of physical pipe 2 RS unit</doc> -<bitfield high="12" low="12" name="PIPE1_Z_IDLE" /> -<doc>Idle status of physical pipe 1 Z unit</doc> -<bitfield high="13" low="13" name="PIPE0_Z_IDLE" /> -<doc>Idle status of physical pipe 0 Z unit</doc> -<bitfield high="14" low="14" name="PIPE1_CB_IDLE" /> -<doc>Idle status of physical pipe 1 CB unit</doc> -<bitfield high="15" low="15" name="PIPE0_CB_IDLE" /> -<doc>Idle status of physical pipe 0 CB unit</doc> -<bitfield high="16" low="16" name="PIPE1_FG_IDLE" /> -<doc>Idle status of physical pipe 1 FG unit</doc> -<bitfield high="17" low="17" name="PIPE0_FG_IDLE" /> -<doc>Idle status of physical pipe 0 FG unit</doc> -<bitfield high="18" low="18" name="PIPE1_US_IDLE" /> -<doc>Idle status of physical pipe 1 US unit</doc> -<bitfield high="19" low="19" name="PIPE0_US_IDLE" /> -<doc>Idle status of physical pipe 0 US unit</doc> -<bitfield high="20" low="20" name="PIPE1_SC_IDLE" /> -<doc>Idle status of physical pipe 1 SC unit</doc> -<bitfield high="21" low="21" name="PIPE0_SC_IDLE" /> -<doc>Idle status of physical pipe 0 SC unit</doc> -<bitfield high="22" low="22" name="PIPE1_RS_IDLE" /> -<doc>Idle status of physical pipe 1 RS unit</doc> -<bitfield high="23" low="23" name="PIPE0_RS_IDLE" /> -<doc>Idle status of physical pipe 0 RS unit</doc> -<bitfield high="24" low="24" name="SU_IDLE" /> -<doc>Idle status of SU unit</doc> -<bitfield high="25" low="25" name="GA_IDLE" /> -<doc>Idle status of GA unit</doc> -<bitfield high="26" low="26" name="GA_UNIT2_IDLE" /> -<doc>Idle status of GA unit2</doc> -</reg32> -<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234"> -<doc>Line control</doc> -<bitfield high="15" low="0" name="WIDTH" /> -<doc>1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b -subprecision); (16.0) fixed format.</doc> -<bitfield high="17" low="16" name="END_TYPE"> -<use-enum ref="ENUM34" /> -</bitfield> -<doc>Specifies how ends of lines should be drawn.</doc> -<bitfield high="18" low="18" name="SORT"> -<value name="NO_SORTING" value="0"> -<doc>No sorting (default)</doc> -</value> -<value name="SORT_ON_MINX_THAN_MINY" value="1"> -<doc>Sort on minX than MinY</doc> -</value> -</bitfield> -<doc>R520+: When enabled, all lines are sorted so that V0 is vertex -with smallest X, or if X equal, smallest Y.</doc> -</reg32> -<reg32 access="rw" name="GA_OFFSET" offset="0x4290"> -<doc>Specifies x & y offsets for vertex data after conversion -to FP.</doc> -<bitfield high="15" low="0" name="X_OFFSET" /> -<doc>Specifies X offset in S15 format (subpixels -- 1/12 or 1/16, -even in 8b subprecision).</doc> -<bitfield high="31" low="16" name="Y_OFFSET" /> -<doc>Specifies Y offset in S15 format (subpixels -- 1/12 or 1/16, -even in 8b subprecision).</doc> -</reg32> -<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C"> -<doc>Dimensions for Points</doc> -<bitfield high="15" low="0" name="HEIGHT" /> -<doc>1/2 Height of point; fixed (16.0), subpixel format (1/12 or -1/16, even if in 8b precision).</doc> -<bitfield high="31" low="16" name="WIDTH" /> -<doc>1/2 Width of point; fixed (16.0), subpixel format (1/12 or -1/16, even if in 8b precision)</doc> -</reg32> -<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C"> -<doc>Specifies the rouding mode for geometry & color SPFP to FP -conversions.</doc> -<bitfield high="1" low="0" name="GEOMETRY_ROUND"> -<use-enum ref="ENUM38" /> -</bitfield> -<doc>Trunc (0) or round to nearest (1) for geometry (XY).</doc> -<bitfield high="3" low="2" name="COLOR_ROUND"> -<use-enum ref="ENUM38" /> -</bitfield> -<doc>When set, FP32 to FP20 using round to nearest; otherwise -trunc</doc> -<bitfield high="4" low="4" name="RGB_CLAMP"> -<value name="CLAMP_TO" value="0"> -<doc>Clamp to [0,1.0] for RGB</doc> -</value> -<value name="RGB_IS_FP20" value="1"> -<doc>RGB is FP20</doc> -</value> -</bitfield> -<doc>Specifies SPFP color clamp range of [0,1] or FP20 for -RGB.</doc> -<bitfield high="5" low="5" name="ALPHA_CLAMP"> -<value name="CLAMP_TO" value="0"> -<doc>Clamp to [0,1.0] for Alpha</doc> -</value> -<value name="ALPHA_IS_FP20" value="1"> -<doc>Alpha is FP20</doc> -</value> -</bitfield> -<doc>Specifies SPFP alpha clamp range of [0,1] or FP20.</doc> -<bitfield high="9" low="6" name="GEOMETRY_MASK" /> -<doc>4b negative polarity mask for subpixel precision. Inverted -version gets ANDed with subpixel X, Y masks.</doc> -</reg32> -<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280"> -<doc>Specifies blue & alpha components of fill color -- S312 -format -- Backwards comp.</doc> -<bitfield high="15" low="0" name="COLOR_ALPHA" /> -<doc>Component alpha value. (S3.12)</doc> -<bitfield high="31" low="16" name="COLOR_BLUE" /> -<doc>Component blue value. (S3.12)</doc> -</reg32> -<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C"> -<doc>Specifies red & green components of fill color -- S312 -format -- Backwards comp.</doc> -<bitfield high="15" low="0" name="COLOR_GREEN" /> -<doc>Component green value (S3.12).</doc> -<bitfield high="31" low="16" name="COLOR_RED" /> -<doc>Component red value (S3.12).</doc> -</reg32> -<reg32 access="rw" name="GA_US_VECTOR_DATA" offset="0x4254"> -<doc>Data register for loading US instructions and constants</doc> -</reg32> -<reg32 access="rw" name="GA_US_VECTOR_INDEX" offset="0x4250"> -<doc>Used to load US instructions and constants</doc> -<bitfield high="8" low="0" name="INDEX" /> -<doc>Instruction (TYPE == GA_US_VECTOR_INST) or constant (TYPE == -GA_US_VECTOR_CONST) number at which to start loading. The GA will -then expect n*6 (instructions) or n*4 (constants) writes to -GA_US_VECTOR_DATA. The GA will self-increment until this register -is written again. For instructions, the GA expects the dwords in -the following order: US_CMN_INST, US_ALU_RGB_ADDR, -US_ALU_ALPHA_ADDR, US_ALU_ALPHA, US_RGB_INST, US_ALPHA_INST, -US_RGBA_INST. For constants, the GA expects the dwords in RGBA -order.</doc> -<bitfield high="16" low="16" name="TYPE"> -<value name="LOAD_INSTRUCTIONS" value="0"> -<doc>Load instructions - INDEX is an instruction index</doc> -</value> -<value name="LOAD_CONSTANTS" value="1"> -<doc>Load constants - INDEX is a constant index</doc> -</value> -</bitfield> -<doc>Specifies if the GA should load instructions or -constants.</doc> -<bitfield high="17" low="17" name="CLAMP"> -<value name="NO_CLAMPING_OF_DATA" value="0"> -<doc>No clamping of data - Default</doc> -</value> -<value name="CLAMP_TO" value="1"> -<doc>Clamp to [-1.0,1.0] constant data</doc> -</value> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="GB_ENABLE" offset="0x4008"> -<doc>Specifies top of Raster pipe specific enable controls.</doc> -<bitfield high="0" low="0" name="POINT_STUFF_ENABLE"> -<use-enum ref="ENUM43" /> -</bitfield> -<doc>Specifies if points will have stuffed texture -coordinates.</doc> -<bitfield high="1" low="1" name="LINE_STUFF_ENABLE"> -<use-enum ref="ENUM44" /> -</bitfield> -<doc>Specifies if lines will have stuffed texture -coordinates.</doc> -<bitfield high="2" low="2" name="TRIANGLE_STUFF_ENABLE"> -<use-enum ref="ENUM45" /> -</bitfield> -<doc>Specifies if triangles will have stuffed texture -coordinates.</doc> -<bitfield high="5" low="4" name="STENCIL_AUTO"> -<use-enum ref="ENUM46" /> -</bitfield> -<doc>Specifies if the auto dec/inc stencil mode should be enabled, -and how.</doc> -<bitfield high="17" low="16" name="TEX0_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="19" low="18" name="TEX1_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="21" low="20" name="TEX2_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="23" low="22" name="TEX3_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="25" low="24" name="TEX4_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="27" low="26" name="TEX5_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="29" low="28" name="TEX6_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -<bitfield high="31" low="30" name="TEX7_SOURCE"> -<use-enum ref="ENUM229" /> -</bitfield> -<doc>Specifies the sources of the texture coordinates for each -texture.</doc> -</reg32> -<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024"> -<doc>Specifies the sizes of the various FIFO`s in the sc/rs/us. -This register must be the first one written</doc> -<bitfield high="1" low="0" name="SC_IFIFO_SIZE"> -<use-enum ref="ENUM55" /> -</bitfield> -<doc>Size of scan converter input FIFO (XYZ)</doc> -<bitfield high="3" low="2" name="SC_TZFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of scan converter top-of-pipe Z FIFO</doc> -<bitfield high="5" low="4" name="SC_BFIFO_SIZE"> -<use-enum ref="ENUM55" /> -</bitfield> -<doc>Size of scan converter input FIFO (B)</doc> -<bitfield high="7" low="6" name="RS_TFIFO_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of ras input FIFO (Texture)</doc> -<bitfield high="9" low="8" name="RS_CFIFO_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of ras input FIFO (Color)</doc> -<bitfield high="11" low="10" name="US_RAM_SIZE"> -<use-enum ref="ENUM57" /> -</bitfield> -<doc>Size of us RAM</doc> -<bitfield high="13" low="12" name="US_OFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of us output FIFO (RGBA)</doc> -<bitfield high="15" low="14" name="US_WFIFO_SIZE"> -<use-enum ref="ENUM56" /> -</bitfield> -<doc>Size of us output FIFO (W)</doc> -<bitfield high="18" low="16" name="RS_HIGHWATER_COL" /> -<doc>High water mark for RS colors` fifo -- NOT USED</doc> -<bitfield high="21" low="19" name="RS_HIGHWATER_TEX" /> -<doc>High water mark for RS textures` fifo -- NOT USED</doc> -<bitfield high="23" low="22" name="US_OFIFO_HIGHWATER"> -<use-enum ref="ENUM58" /> -</bitfield> -<doc>High water mark for US output fifo</doc> -<bitfield high="28" low="24" name="US_CUBE_FIFO_HIGHWATER" /> -<doc>High water mark for US cube map fifo</doc> -</reg32> -<reg32 access="rw" name="GB_FIFO_SIZE1" offset="0x4070"> -<doc>Specifies the sizes of the various FIFO`s in the sc/rs.</doc> -<bitfield high="5" low="0" name="SC_HIGHWATER_IFIFO" /> -<doc>High water mark for SC input fifo</doc> -<bitfield high="11" low="6" name="SC_HIGHWATER_BFIFO" /> -<doc>High water mark for SC input fifo (B)</doc> -<bitfield high="17" low="12" name="RS_HIGHWATER_COL" /> -<doc>High water mark for RS colors` fifo</doc> -<bitfield high="23" low="18" name="RS_HIGHWATER_TEX" /> -<doc>High water mark for RS textures` fifo</doc> -</reg32> -<reg32 access="rw" name="GB_MSPOS0" offset="0x4010"> -<doc>Specifies the position of multisamples 0 through 2</doc> -<bitfield high="3" low="0" name="MS_X0" /> -<doc>Specifies the x and y position (in subpixels) of multisample -0</doc> -<bitfield high="7" low="4" name="MS_Y0" /> -<doc>Specifies the x and y position (in subpixels) of multisample -0</doc> -<bitfield high="11" low="8" name="MS_X1" /> -<doc>Specifies the x and y position (in subpixels) of multisample -1</doc> -<bitfield high="15" low="12" name="MS_Y1" /> -<doc>Specifies the x and y position (in subpixels) of multisample -1</doc> -<bitfield high="19" low="16" name="MS_X2" /> -<doc>Specifies the x and y position (in subpixels) of multisample -2</doc> -<bitfield high="23" low="20" name="MS_Y2" /> -<doc>Specifies the x and y position (in subpixels) of multisample -2</doc> -<bitfield high="27" low="24" name="MSBD0_Y" /> -<doc>Specifies the minimum x and y distance (in subpixels) between -the pixel edge and the multisamples. These values are used in the -first (coarse) scan converter</doc> -<bitfield high="31" low="28" name="MSBD0_X" /> -<doc>Specifies the minimum x and y distance (in subpixels) between -the pixel edge and the multisamples. These values are used in the -first (coarse) scan converter</doc> -</reg32> -<reg32 access="rw" name="GB_MSPOS1" offset="0x4014"> -<doc>Specifies the position of multisamples 3 through 5</doc> -<bitfield high="3" low="0" name="MS_X3" /> -<doc>Specifies the x and y position (in subpixels) of multisample -3</doc> -<bitfield high="7" low="4" name="MS_Y3" /> -<doc>Specifies the x and y position (in subpixels) of multisample -3</doc> -<bitfield high="11" low="8" name="MS_X4" /> -<doc>Specifies the x and y position (in subpixels) of multisample -4</doc> -<bitfield high="15" low="12" name="MS_Y4" /> -<doc>Specifies the x and y position (in subpixels) of multisample -4</doc> -<bitfield high="19" low="16" name="MS_X5" /> -<doc>Specifies the x and y position (in subpixels) of multisample -5</doc> -<bitfield high="23" low="20" name="MS_Y5" /> -<doc>Specifies the x and y position (in subpixels) of multisample -5</doc> -<bitfield high="27" low="24" name="MSBD1" /> -<doc>Specifies the minimum distance (in subpixels) between the -pixel edge and the multisamples. This value is used in the second -(quad) scan converter</doc> -</reg32> -<reg32 access="rw" name="GB_PIPE_SELECT" offset="0x402C"> -<doc>Selects which of 4 pipes are active.</doc> -<bitfield high="1" low="0" name="PIPE0_ID" /> -<doc>Maps physical pipe 0 to logical pipe ID (def 0).</doc> -<bitfield high="3" low="2" name="PIPE1_ID" /> -<doc>Maps physical pipe 1 to logical pipe ID (def 1).</doc> -<bitfield high="5" low="4" name="PIPE2_ID" /> -<doc>Maps physical pipe 2 to logical pipe ID (def 2).</doc> -<bitfield high="7" low="6" name="PIPE3_ID" /> -<doc>Maps physical pipe 3 to logical pipe ID (def 3).</doc> -<bitfield high="11" low="8" name="PIPE_MASK"> -<value name="P3" value="3"> -<doc>P3, B</doc> -</value> -<value name="P2" value="2"> -<doc>P2, B</doc> -</value> -<value name="P1" value="1"> -<doc>P1, B</doc> -</value> -<value name="P0" value="0"> -<doc>P0. -- 1: enabled,</doc> -</value> -<value name="DISABLED" value="0"> -<doc>disabled</doc> -</value> -</bitfield> -<doc>4b mask, indicates which physical pipes are enabled (def -none=0x0) -- B3=P3, B2=P2, B1=P1, B0=P0. -- 1: enabled, 0: -disabled</doc> -<bitfield high="13" low="12" name="MAX_PIPE" /> -<doc>2b, indicates, by the fuses, the max number of allowed pipes. -0 = 1 pipe ... 3 = 4 pipes -- Read Only</doc> -<bitfield high="17" low="14" name="BAD_PIPES"> -<value name="P3" value="3"> -<doc>P3, B</doc> -</value> -<value name="P2" value="2"> -<doc>P2, B</doc> -</value> -<value name="P1" value="1"> -<doc>P1, B</doc> -</value> -<value name="P0" value="0"> -<doc>P0 --</doc> -</value> -<value name="BAD" value="1"> -<doc>bad,</doc> -</value> -<value name="GOOD" value="0"> -<doc>good -- Read Only</doc> -</value> -</bitfield> -<doc>4b, indicates, by the fuses, the bad pipes: B3=P3, B2=P2, -B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only</doc> -<bitfield high="18" low="18" name="CONFIG_PIPES"> -<value name="DO_NOTHING" value="0"> -<doc>Do nothing</doc> -</value> -<value name="FORCE_SELF" value="1"> -<doc>Force self-configuration</doc> -</value> -</bitfield> -<doc>If this bit is set when writing this register, the logical -pipe ID values are assigned automatically based on the values that -are read back in the MAX_PIPE and BAD_PIPES fields. This field is -always read back as 0.</doc> -</reg32> -<reg32 access="rw" name="GB_SELECT" offset="0x401C"> -<doc>Specifies various polygon specific selects (fog, depth, -perspective).</doc> -<bitfield high="2" low="0" name="FOG_SELECT"> -<use-enum ref="ENUM59" /> -</bitfield> -<doc>Specifies source for outgoing (GA to SU) fog value.</doc> -<bitfield high="3" low="3" name="DEPTH_SELECT"> -<use-enum ref="ENUM60" /> -</bitfield> -<doc>Specifies source for outgoing (GA/SU & SU/RAS) depth -value.</doc> -<bitfield high="4" low="4" name="W_SELECT"> -<use-enum ref="ENUM61" /> -</bitfield> -<doc>Specifies source for outgoing (1/W) value, used to disable -perspective correct colors/textures.</doc> -<bitfield high="5" low="5" name="FOG_STUFF_ENABLE"> -<value name="DISABLE_FOG_TEXTURE_STUFFING" value="0"> -<doc>Disable fog texture stuffing</doc> -</value> -<value name="ENABLE_FOG_TEXTURE_STUFFING" value="1"> -<doc>Enable fog texture stuffing</doc> -</value> -</bitfield> -<doc>Controls enabling of fog stuffing into texture -coordinate.</doc> -<bitfield high="9" low="6" name="FOG_STUFF_TEX" /> -<doc>Controls which texture gets fog value</doc> -<bitfield high="11" low="10" name="FOG_STUFF_COMP" /> -<doc>Controls which component of texture gets fog value</doc> -</reg32> -<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018"> -<doc>Specifies the graphics pipeline configuration for -rasterization</doc> -<bitfield high="0" low="0" name="ENABLE"> -<use-enum ref="ENUM62" /> -</bitfield> -<doc>Enables tiling, otherwise all tiles receive all -polygons.</doc> -<bitfield high="3" low="1" name="PIPE_COUNT"> -<value name="RV350" value="0"> -<doc>RV350 (1 pipe, 1 ctx)</doc> -</value> -<value name="R300" value="3"> -<doc>R300 (2 pipes, 1 ctx) 06 – R420-3P (3 -pipes, 1 ctx) 07 – R420 (4 pipes, 1 ctx)</doc> -</value> -</bitfield> -<doc>Specifies the number of active pipes and contexts (up to 4 -pipes, 1 ctx). When this field is written, it is automatically -reduced by hardware so as not to use more pipes than the number -indicated in GB_PIPE_SELECT.MAX_PIPES or the number of pipes left -unmasked GB_PIPE_SELECT.BAD_PIPES. The potentially altered value is -read back, rather than the original value written by -software.</doc> -<bitfield high="5" low="4" name="TILE_SIZE"> -<value name="8_PIXELS" value="0"> -<doc>8 pixels.</doc> -</value> -<value name="16_PIXELS" value="1"> -<doc>16 pixels.</doc> -</value> -<value name="32_PIXELS" value="2"> -<doc>32 pixels.</doc> -</value> -</bitfield> -<doc>Specifies width & height (square), in pixels (only 16, 32 -available).</doc> -<bitfield high="8" low="6" name="SUPER_SIZE"> -<use-enum ref="ENUM65" /> -</bitfield> -<doc>Specifies number of tiles and config in super chip -configuration.</doc> -<bitfield high="11" low="9" name="SUPER_X" /> -<doc>X Location of chip within super tile.</doc> -<bitfield high="14" low="12" name="SUPER_Y" /> -<doc>Y Location of chip within super tile.</doc> -<bitfield high="15" low="15" name="SUPER_TILE"> -<use-enum ref="ENUM66" /> -</bitfield> -<doc>Tile location of chip in a multi super tile config (Super size -of 2,8,32 or 128).</doc> -<bitfield high="16" low="16" name="SUBPIXEL"> -<use-enum ref="ENUM67" /> -</bitfield> -<doc>Specifies the precision of subpixels wrt pixels (12 or -16).</doc> -<bitfield high="18" low="17" name="QUADS_PER_RAS"> -<value name="4_QUADS" value="0"> -<doc>4 Quads</doc> -</value> -<value name="8_QUADS" value="1"> -<doc>8 Quads</doc> -</value> -<value name="16_QUADS" value="2"> -<doc>16 Quads</doc> -</value> -<value name="32_QUADS" value="3"> -<doc>32 Quads</doc> -</value> -</bitfield> -<doc>Specifies the number of quads to be sent to each rasterizer in -turn when in RV300B or R300B mode</doc> -<bitfield high="19" low="19" name="BB_SCAN"> -<value name="USE_INTERCEPT_BASED_SCAN_CONVERTER" value="0"> -<doc>Use intercept based scan converter</doc> -</value> -<value name="USE_BOUNDING_BOX_BASED_SCAN_CONVERTER" value="1"> -<doc>Use bounding box based scan converter</doc> -</value> -</bitfield> -<doc>Specifies whether to use an intercept or bounding box based -calculation for the first (coarse) scan converter</doc> -<bitfield high="20" low="20" name="ALT_SCAN_EN"> -<value name="USE_NORMAL_LEFT" value="0"> -<doc>Use normal left-right scan</doc> -</value> -<value name="USE_ALTERNATE_LEFT" value="1"> -<doc>Use alternate left-right-left scan</doc> -</value> -</bitfield> -<doc>Specifies whether to use an altenate scan pattern for the -coarse scan converter</doc> -<bitfield high="21" low="21" name="ALT_OFFSET"> -<value name="NOT_USED" value="0"> -<doc>Not used</doc> -</value> -<value name="NOT_USED" value="1"> -<doc>Not used</doc> -</value> -</bitfield> -<doc>Not used -- should be 0</doc> -<bitfield high="22" low="22" name="SUBPRECISION" /> -<doc>Set to 0</doc> -<bitfield high="23" low="23" name="ALT_TILING"> -<value name="USE_DEFAULT_TILING_IN_ALL_TILING_MODES" value="0"> -<doc>Use default tiling in all tiling modes</doc> -</value> -<value name="USE_ALTERNATIVE_3X2_TILING_IN_3P_MODE" value="1"> -<doc>Use alternative 3x2 tiling in 3P mode</doc> -</value> -</bitfield> -<doc>Support for 3x2 tiling in 3P mode</doc> -<bitfield high="24" low="24" name="Z_EXTENDED"> -<value name="USE" value="0"> -<doc>Use (24.1) Z format, with vertex clamp to [1.0,0.0]</doc> -</value> -<value name="USE" value="1"> -<doc>Use (S25.1) format, with vertex clamp to [2.0,- 2.0] and per -pixel [1.0,0.0]</doc> -</value> -</bitfield> -<doc>Support for extended setup Z range from [0,1] to [-2,2] with -per pixel clamping</doc> -</reg32> -<reg32 access="rw" name="GB_Z_PEQ_CONFIG" offset="0x4028"> -<doc>Specifies the z plane equation configuration.</doc> -<bitfield high="0" low="0" name="Z_PEQ_SIZE"> -<value name="4X4_Z_PLANE_EQUATIONS" value="0"> -<doc>4x4 z plane equations (point-sampled or aa)</doc> -</value> -<value name="8X8_Z_PLANE_EQUATIONS" value="1"> -<doc>8x8 z plane equations (point-sampled only)</doc> -</value> -</bitfield> -<doc>Specifies the z plane equation size.</doc> -</reg32> -<reg32 access="rw" name="RS_COUNT" offset="0x4300"> -<doc>This register specifies the rasterizer input packet -configuration</doc> -<bitfield high="6" low="0" name="IT_COUNT" /> -<doc>Specifies the total number of texture address components -contained in the rasterizer input packet (0:32).</doc> -<bitfield high="10" low="7" name="IC_COUNT" /> -<doc>Specifies the total number of colors contained in the -rasterizer input packet (0:4).</doc> -<bitfield high="17" low="12" name="W_ADDR" /> -<doc>Specifies the relative rasterizer input packet location of w -(if w_count==1)</doc> -<bitfield high="18" low="18" name="HIRES_EN" /> -<doc>Enable high resolution texture coordinate output when q is -equal to 1</doc> -</reg32> -<stripe length="16" offset="0x4320" stride="0x0004"> -<reg32 access="rw" name="RS_INST" offset="0x0"> -<doc>This table specifies what happens during each rasterizer -instruction</doc> -<bitfield high="3" low="0" name="TEX_ID" /> -<doc>Specifies the index (into the RS_IP table) of the texture -address output during this rasterizer instruction</doc> -<bitfield high="4" low="4" name="TEX_CN"> -<use-enum ref="ENUM68" /> -</bitfield> -<doc>Write enable for texture address</doc> -<bitfield high="11" low="5" name="TEX_ADDR" /> -<doc>Specifies the destination address (within the current pixel -stack frame) of the texture address output during this rasterizer -instruction</doc> -<bitfield high="15" low="12" name="COL_ID" /> -<doc>Specifies the index (into the RS_IP table) of the color output -during this rasterizer instruction</doc> -<bitfield high="17" low="16" name="COL_CN"> -<value name="NO_WRITE" value="0"> -<doc>No write - color not valid</doc> -</value> -<value name="WRITE" value="1"> -<doc>write - color valid</doc> -</value> -<value name="WRITE_FBUFFER" value="2"> -<doc>write fbuffer - XY00->RGBA</doc> -</value> -<value name="WRITE_BACKFACE" value="3"> -<doc>write backface - B000->RGBA</doc> -</value> -</bitfield> -<doc>Write enable for color</doc> -<bitfield high="24" low="18" name="COL_ADDR" /> -<doc>Specifies the destination address (within the current pixel -stack frame) of the color output during this rasterizer -instruction</doc> -<bitfield high="25" low="25" name="TEX_ADJ"> -<use-enum ref="ENUM70" /> -</bitfield> -<doc>Specifies whether to sample texture coordinates at the real or -adjusted pixel centers</doc> -<bitfield high="26" low="26" name="W_CN"> -<value name="NO_WRITE" value="0"> -<doc>No write - w not valid</doc> -</value> -<value name="WRITE" value="1"> -<doc>write - w valid</doc> -</value> -</bitfield> -<doc>Specifies that the rasterizer should output w</doc> -</reg32> -</stripe> -<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304"> -<doc>This register specifies the number of rasterizer -instructions</doc> -<bitfield high="3" low="0" name="INST_COUNT" /> -<doc>Number of rasterizer instructions (1:16)</doc> -<bitfield high="7" low="5" name="TX_OFFSET" /> -<doc>Indicates range of texture offset to minimize peroidic errors -on texels sampled right on their edges</doc> -</reg32> -<stripe length="16" offset="0x4074" stride="0x0004"> -<reg32 access="rw" name="RS_IP" offset="0x0"> -<doc>This table specifies the source location and format for up to -16 texture addresses (i[0]:i[15]) and four colors (c[0]:c[3])</doc> -<bitfield high="5" low="0" name="TEX_PTR_S" /> -<doc>Specifies the relative rasterizer input packet location of -each component (S, T, R, and Q) of texture address (i[i]). The -values 62 and 63 select constant inputs for the component: 62 -selects K0 (0.0), and 63 selects K1 (1.0).</doc> -<bitfield high="11" low="6" name="TEX_PTR_T" /> -<doc>Specifies the relative rasterizer input packet location of -each component (S, T, R, and Q) of texture address (i[i]). The -values 62 and 63 select constant inputs for the component: 62 -selects K0 (0.0), and 63 selects K1 (1.0).</doc> -<bitfield high="17" low="12" name="TEX_PTR_R" /> -<doc>Specifies the relative rasterizer input packet location of -each component (S, T, R, and Q) of texture address (i[i]). The -values 62 and 63 select constant inputs for the component: 62 -selects K0 (0.0), and 63 selects K1 (1.0).</doc> -<bitfield high="23" low="18" name="TEX_PTR_Q" /> -<doc>Specifies the relative rasterizer input packet location of -each component (S, T, R, and Q) of texture address (i[i]). The -values 62 and 63 select constant inputs for the component: 62 -selects K0 (0.0), and 63 selects K1 (1.0).</doc> -<bitfield high="26" low="24" name="COL_PTR" /> -<doc>Specifies the relative rasterizer input packet location of the -color (c[i]).</doc> -<bitfield high="30" low="27" name="COL_FMT"> -<use-enum ref="ENUM72" /> -</bitfield> -<doc>Specifies the format of the color (c[i]).</doc> -<bitfield high="31" low="31" name="OFFSET_EN"> -<value name="DO_NOT_APPLY_THE_TX_OFFSET_IN_RS_INST_COUNT" -value="0"> -<doc>Do not apply the TX_OFFSET in RS_INST_COUNT</doc> -</value> -<value name="APPLY_THE_TX_OFFSET_SPECIFIED_BY_RS_INST_COUNT" -value="1"> -<doc>Apply the TX_OFFSET specified by RS_INST_COUNT</doc> -</value> -</bitfield> -<doc>Enable application of the TX_OFFSET in RS_INST_COUNT</doc> -</reg32> -</stripe> -<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8"> -<doc>Edge rules - what happens when an edge falls exactly on a -sample point</doc> -<bitfield high="4" low="0" name="ER_TRI"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="9" low="5" name="ER_POINT"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="14" low="10" name="ER_LINE_LR"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="19" low="15" name="ER_LINE_RL"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="24" low="20" name="ER_LINE_TB"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -<bitfield high="29" low="25" name="ER_LINE_BT"> -<use-enum ref="ENUM74" /> -</bitfield> -<doc>Edge rules for triangles, points, left-right lines, right-left -lines, upper-bottom lines, bottom-upper lines. For values 0 to 15, -bit 0 specifies whether a sample on a horizontal- bottom edge is -in, bit 1 specifies whether a sample on a horizontal-top edge is -in, bit 2 species whether a sample on a right edge is in, bit 3 -specifies whether a sample on a left edge is in. For values 16 to -31, bit 0 specifies whether a sample on a vertical-right edge is -in, bit 1 specifies whether a sample on a vertical-left edge is in, -bit 2 species whether a sample on a bottom edge is in, bit 3 -specifies whether a sample on a top edge is in</doc> -</reg32> -<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8"> -<doc>SU Raster pipe destination select for registers</doc> -<bitfield high="3" low="0" name="SELECT"> -<value name="LOGICAL_PIPE0" value="0"> -<doc>logical pipe0, b</doc> -</value> -<value name="LOGICAL_PIPE1" value="1"> -<doc>logical pipe1, b</doc> -</value> -<value name="LOGICAL_PIPE2_AND_B" value="2"> -<doc>logical pipe2 and b</doc> -</value> -<value name="LOGICAL_PIPE3" value="3"> -<doc>logical pipe3</doc> -</value> -</bitfield> -<doc>Register read/write destination select: b0: logical pipe0, b1: -logical pipe1, b2: logical pipe2 and b3: logical pipe3</doc> -</reg32> -<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0"> -<doc>Enables for Cylindrical Wrapping</doc> -<bitfield high="0" low="0" name="T0C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="1" low="1" name="T0C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="2" low="2" name="T0C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="3" low="3" name="T0C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="4" low="4" name="T1C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="5" low="5" name="T1C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="6" low="6" name="T1C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="7" low="7" name="T1C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="8" low="8" name="T2C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="9" low="9" name="T2C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="10" low="10" name="T2C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="11" low="11" name="T2C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="12" low="12" name="T3C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="13" low="13" name="T3C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="14" low="14" name="T3C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="15" low="15" name="T3C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="16" low="16" name="T4C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="17" low="17" name="T4C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="18" low="18" name="T4C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="19" low="19" name="T4C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="20" low="20" name="T5C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="21" low="21" name="T5C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="22" low="22" name="T5C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="23" low="23" name="T5C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="24" low="24" name="T6C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="25" low="25" name="T6C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="26" low="26" name="T6C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="27" low="27" name="T6C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="28" low="28" name="T7C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="29" low="29" name="T7C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="30" low="30" name="T7C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="31" low="31" name="T7C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -</reg32> -<reg32 access="rw" name="SU_TEX_WRAP_PS3" offset="0x4114"> -<doc>Specifies texture wrapping for new PS3 textures.</doc> -<bitfield high="0" low="0" name="T9C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="1" low="1" name="T9C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="2" low="2" name="T9C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="3" low="3" name="T9C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="4" low="4" name="T8C0"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="5" low="5" name="T8C1"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="6" low="6" name="T8C2"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -<bitfield high="7" low="7" name="T8C3"> -<use-enum ref="ENUM247" /> -</bitfield> -<doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of -texture N.</doc> -</reg32> -<stripe length="16" offset="0x45C0" stride="0x0004"> -<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0"> -<doc>Border Color</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4580" stride="0x0004"> -<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0"> -<doc>Texture Chroma Key</doc> -</reg32> -</stripe> -<reg32 access="rw" name="TX_ENABLE" offset="0x4104"> -<doc>Texture Enables for Maps 0 to 15</doc> -<bitfield high="0" low="0" name="TEX_0_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="1" low="1" name="TEX_1_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="2" low="2" name="TEX_2_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="3" low="3" name="TEX_3_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="4" low="4" name="TEX_4_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="5" low="5" name="TEX_5_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="6" low="6" name="TEX_6_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="7" low="7" name="TEX_7_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="8" low="8" name="TEX_8_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="9" low="9" name="TEX_9_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="10" low="10" name="TEX_10_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="11" low="11" name="TEX_11_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="12" low="12" name="TEX_12_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="13" low="13" name="TEX_13_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="14" low="14" name="TEX_14_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -<bitfield high="15" low="15" name="TEX_15_ENABLE"> -<use-enum ref="ENUM248" /> -</bitfield> -<doc>Texture Map Enables.</doc> -</reg32> -<stripe length="16" offset="0x4400" stride="0x0004"> -<reg32 access="rw" name="TX_FILTER0" offset="0x0"> -<doc>Texture Filter State</doc> -<bitfield high="2" low="0" name="CLAMP_S"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for texture coordinates</doc> -<bitfield high="5" low="3" name="CLAMP_T"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for texture coordinates</doc> -<bitfield high="8" low="6" name="CLAMP_R"> -<use-enum ref="ENUM136" /> -</bitfield> -<doc>Clamp mode for texture coordinates</doc> -<bitfield high="10" low="9" name="MAG_FILTER"> -<use-enum ref="ENUM249" /> -</bitfield> -<doc>Filter used when texture is magnified</doc> -<bitfield high="12" low="11" name="MIN_FILTER"> -<use-enum ref="ENUM249" /> -</bitfield> -<doc>Filter used when texture is minified</doc> -<bitfield high="14" low="13" name="MIP_FILTER"> -<use-enum ref="ENUM138" /> -</bitfield> -<doc>Filter used between mipmap levels</doc> -<bitfield high="16" low="15" name="VOL_FILTER"> -<use-enum ref="ENUM139" /> -</bitfield> -<doc>Filter used between layers of a volume</doc> -<bitfield high="20" low="17" name="MAX_MIP_LEVEL" /> -<doc>LOD index of largest (finest) mipmap to use (0 is largest). -Ranges from 0 to NUM_LEVELS.</doc> -<bitfield high="31" low="28" name="ID" /> -<doc>Logical id for this physical texture</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4440" stride="0x0004"> -<reg32 access="rw" name="TX_FILTER1" offset="0x0"> -<doc>Texture Filter State</doc> -<bitfield high="1" low="0" name="CHROMA_KEY_MODE"> -<use-enum ref="ENUM140" /> -</bitfield> -<doc>Chroma Key Mode</doc> -<bitfield high="2" low="2" name="MC_ROUND"> -<use-enum ref="ENUM141" /> -</bitfield> -<doc>Bilinear rounding mode</doc> -<bitfield high="12" low="3" name="LOD_BIAS" /> -<doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias measured -in mipmap levels. Added to the signed, computed LOD before the LOD -is clamped.</doc> -<bitfield high="14" low="14" name="MC_COORD_TRUNCATE"> -<use-enum ref="ENUM142" /> -</bitfield> -<doc>MPEG coordinate truncation mode</doc> -<bitfield high="16" low="15" name="TRI_PERF"> -<value name="BREAKPOINT" value="0"> -<doc>Breakpoint=0/8. lfrac_out = lfrac_in</doc> -</value> -<value name="BREAKPOINT" value="1"> -<doc>Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in - 1/6)</doc> -</value> -<value name="BREAKPOINT" value="2"> -<doc>Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in - 1/2)</doc> -</value> -<value name="BREAKPOINT" value="3"> -<doc>Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in - 3/2)</doc> -</value> -</bitfield> -<doc>Apply slope and bias to trilerp fraction to reduce the number -of 2-level fetches for trilinear. Should only be used if MIP_FILTER -is LINEAR.</doc> -<bitfield high="19" low="17" name="Reserved" /> -<doc>Set to 0</doc> -<bitfield high="20" low="20" name="Reserved" /> -<doc>Set to 0</doc> -<bitfield high="21" low="21" name="Reserved" /> -<doc>Set to 0</doc> -<bitfield high="22" low="22" name="MACRO_SWITCH"> -<value name="RV350_MODE" value="0"> -<doc>RV350 mode</doc> -</value> -<value name="SWITCH_FROM_MACRO" value="1"> -<doc>Switch from macro-tiled to macro-linear when (width <= 8 -micro-tiles)</doc> -</value> -</bitfield> -<doc>If enabled, addressing switches to macro-linear when image -width is <= 8 micro-tiles. If disabled, functionality is same as -RV350, switch to macro-linear when image width is < 8 -micro-tiles.</doc> -<bitfield high="31" low="31" name="BORDER_FIX"> -<value name="R3XX_R4XX_MODE" value="0"> -<doc>R3xx R4xx mode</doc> -</value> -<value name="STOP_RIGHT_SHIFTING_COORD_ONCE_MIP_SIZE_IS_PINNED_TO_ONE" -value="1"> -<doc>Stop right shifting coord once mip size is pinned to one</doc> -</value> -</bitfield> -<doc>To fix issues when using non-square mipmaps, with -border_color, and extreme minification.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="TX_FILTER4" offset="0x4110"> -<doc>Filter4 Kernel</doc> -<bitfield high="10" low="0" name="WEIGHT_1" /> -<doc>(s1.9). Bottom or Right weight of pair.</doc> -<bitfield high="21" low="11" name="WEIGHT_0" /> -<doc>(s1.9). Top or Left weight of pair.</doc> -<bitfield high="22" low="22" name="WEIGHT_PAIR"> -<value name="TOP_OR_LEFT" value="0"> -<doc>Top or Left</doc> -</value> -<value name="BOTTOM_OR_RIGHT" value="1"> -<doc>Bottom or Right</doc> -</value> -</bitfield> -<doc>Indicates which pair of weights within phase to load.</doc> -<bitfield high="26" low="23" name="PHASE" /> -<doc>Indicates which of 9 phases to load</doc> -<bitfield high="27" low="27" name="DIRECTION"> -<value name="HORIZONTAL" value="0"> -<doc>Horizontal</doc> -</value> -<value name="VERTICAL" value="1"> -<doc>Vertical</doc> -</value> -</bitfield> -<doc>Indicates whether to load the horizontal or vertical -weights</doc> -</reg32> -<stripe length="16" offset="0x4480" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT0" offset="0x0"> -<doc>Texture Format State</doc> -<bitfield high="10" low="0" name="TXWIDTH" /> -<doc>Image width - 1. The largest image is 4096 texels. When -wrapping or mirroring, must be a power of 2. When mipmapping, must -be a power of 2 or padded to a power of 2 in memory. Can always be -non-square, except for cube maps which must be square.</doc> -<bitfield high="21" low="11" name="TXHEIGHT" /> -<doc>Image height - 1. The largest image is 4096 texels. When -wrapping or mirroring, must be a power of 2. When mipmapping, must -be a power of 2 or padded to a power of 2 in memory. Can always be -non-square, except for cube maps which must be square.</doc> -<bitfield high="25" low="22" name="TXDEPTH" /> -<doc>LOG2(depth) of volume texture</doc> -<bitfield high="29" low="26" name="NUM_LEVELS" /> -<doc>Number of mipmap levels minus 1. Ranges from 0 to 12. -Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc> -<bitfield high="30" low="30" name="PROJECTED"> -<use-enum ref="ENUM143" /> -</bitfield> -<doc>Specifies whether texture coords are projected.</doc> -<bitfield high="31" low="31" name="TXPITCH_EN"> -<use-enum ref="ENUM144" /> -</bitfield> -<doc>Indicates when TXPITCH should be used instead of TXWIDTH for -image addressing</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x44C0" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT1" offset="0x0"> -<doc>Texture Format State</doc> -<bitfield high="4" low="0" name="TXFORMAT"> -<value name="TX_FMT_8_OR_TX_FMT_1" value="0"> -<doc>TX_FMT_8 or TX_FMT_1 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc> -</value> -<value name="TX_FMT_16_OR_TX_FMT_1_REVERSE" value="1"> -<doc>TX_FMT_16 or TX_FMT_1_REVERSE (if TX_FORMAT2.TXFORMAT_MSB is -set)</doc> -</value> -<value name="TX_FMT_4_4_OR_TX_FMT_10" value="2"> -<doc>TX_FMT_4_4 or TX_FMT_10 (if TX_FORMAT2.TXFORMAT_MSB is -set)</doc> -</value> -<value name="TX_FMT_8_8_OR_TX_FMT_10_10" value="3"> -<doc>TX_FMT_8_8 or TX_FMT_10_10 (if TX_FORMAT2.TXFORMAT_MSB is -set)</doc> -</value> -<value name="TX_FMT_16_16_OR_TX_FMT_10_10_10_10" value="4"> -<doc>TX_FMT_16_16 or TX_FMT_10_10_10_10 (if TX_FORMAT2.TXFORMAT_MSB -is set)</doc> -</value> -<value name="TX_FMT_3_3_2_OR_TX_FMT_ATI1N" value="5"> -<doc>TX_FMT_3_3_2 or TX_FMT_ATI1N (if TX_FORMAT2.TXFORMAT_MSB is -set)</doc> -</value> -<value name="TX_FMT_5_6_5" value="6"> -<doc>TX_FMT_5_6_5</doc> -</value> -<value name="TX_FMT_6_5_5" value="7"> -<doc>TX_FMT_6_5_5</doc> -</value> -<value name="TX_FMT_11_11_10" value="8"> -<doc>TX_FMT_11_11_10</doc> -</value> -<value name="TX_FMT_10_11_11" value="9"> -<doc>TX_FMT_10_11_11</doc> -</value> -<value name="TX_FMT_4_4_4_4" value="10"> -<doc>TX_FMT_4_4_4_4</doc> -</value> -<value name="TX_FMT_1_5_5_5" value="11"> -<doc>TX_FMT_1_5_5_5</doc> -</value> -<value name="TX_FMT_8_8_8_8" value="12"> -<doc>TX_FMT_8_8_8_8</doc> -</value> -<value name="TX_FMT_2_10_10_10" value="13"> -<doc>TX_FMT_2_10_10_10</doc> -</value> -<value name="TX_FMT_16_16_16_16" value="14"> -<doc>TX_FMT_16_16_16_16</doc> -</value> -<value name="TX_FMT_Y8" value="18"> -<doc>TX_FMT_Y8</doc> -</value> -<value name="TX_FMT_AVYU444" value="19"> -<doc>TX_FMT_AVYU444</doc> -</value> -<value name="TX_FMT_VYUY422" value="20"> -<doc>TX_FMT_VYUY422</doc> -</value> -<value name="TX_FMT_YVYU422" value="21"> -<doc>TX_FMT_YVYU422</doc> -</value> -<value name="TX_FMT_16_MPEG" value="22"> -<doc>TX_FMT_16_MPEG</doc> -</value> -<value name="TX_FMT_16_16_MPEG" value="23"> -<doc>TX_FMT_16_16_MPEG</doc> -</value> -<value name="TX_FMT_16F" value="24"> -<doc>TX_FMT_16f</doc> -</value> -<value name="TX_FMT_16F_16F" value="25"> -<doc>TX_FMT_16f_16f</doc> -</value> -<value name="TX_FMT_16F_16F_16F_16F" value="26"> -<doc>TX_FMT_16f_16f_16f_16f</doc> -</value> -<value name="TX_FMT_32F" value="27"> -<doc>TX_FMT_32f</doc> -</value> -<value name="TX_FMT_32F_32F" value="28"> -<doc>TX_FMT_32f_32f</doc> -</value> -<value name="TX_FMT_32F_32F_32F_32F" value="29"> -<doc>TX_FMT_32f_32f_32f_32f</doc> -</value> -<value name="TX_FMT_W24_FP" value="30"> -<doc>TX_FMT_W24_FP</doc> -</value> -<value name="TX_FMT_ATI2N" value="31"> -<doc>TX_FMT_ATI2N</doc> -</value> -</bitfield> -<doc>Texture Format. Components are numbered right to left. -Parenthesis indicate typical uses of each format.</doc> -<bitfield high="5" low="5" name="SIGNED_COMP0"> -<use-enum ref="ENUM256" /> -</bitfield> -<doc>Component filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="6" low="6" name="SIGNED_COMP1"> -<use-enum ref="ENUM256" /> -</bitfield> -<doc>Component filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="7" low="7" name="SIGNED_COMP2"> -<use-enum ref="ENUM256" /> -</bitfield> -<doc>Component filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="8" low="8" name="SIGNED_COMP3"> -<use-enum ref="ENUM256" /> -</bitfield> -<doc>Component filter should interpret texel data as signed or -unsigned. (Ignored for Y/YUV formats.)</doc> -<bitfield high="11" low="9" name="SEL_ALPHA"> -<use-enum ref="ENUM257" /> -</bitfield> -<doc>Specifies swizzling for each channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="14" low="12" name="SEL_RED"> -<use-enum ref="ENUM257" /> -</bitfield> -<doc>Specifies swizzling for each channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="17" low="15" name="SEL_GREEN"> -<use-enum ref="ENUM257" /> -</bitfield> -<doc>Specifies swizzling for each channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="20" low="18" name="SEL_BLUE"> -<use-enum ref="ENUM257" /> -</bitfield> -<doc>Specifies swizzling for each channel at the input of the pixel -shader. (Ignored for Y/YUV formats.)</doc> -<bitfield high="21" low="21" name="GAMMA"> -<use-enum ref="ENUM154" /> -</bitfield> -<doc>Optionally remove gamma from texture before passing to shader. -Only apply to 8bit or less components.</doc> -<bitfield high="23" low="22" name="YUV_TO_RGB"> -<use-enum ref="ENUM155" /> -</bitfield> -<doc>YUV to RGB conversion mode</doc> -<bitfield high="24" low="24" name="SWAP_YUV"> -<use-enum ref="ENUM156" /> -</bitfield> -<doc /> -<bitfield high="26" low="25" name="TEX_COORD_TYPE"> -<use-enum ref="ENUM157" /> -</bitfield> -<doc>Specifies coordinate type.</doc> -<bitfield high="31" low="27" name="CACHE"> -<use-enum ref="ENUM158" /> -</bitfield> -<doc>This field is ignored on R520 and RV510.</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4500" stride="0x0004"> -<reg32 access="rw" name="TX_FORMAT2" offset="0x0"> -<doc>Texture Format State</doc> -<bitfield high="13" low="0" name="TXPITCH" /> -<doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN -is asserted. Pitch is given as number of texels minus one. Maximum -pitch is 16K texels.</doc> -<bitfield high="14" low="14" name="TXFORMAT_MSB" /> -<doc>Specifies the MSB of the texture format to extend the number -of formats to 64.</doc> -<bitfield high="15" low="15" name="TXWIDTH_11" /> -<doc>Specifies bit 11 of TXWIDTH to extend the largest image to -4096 texels.</doc> -<bitfield high="16" low="16" name="TXHEIGHT_11" /> -<doc>Specifies bit 11 of TXHEIGHT to extend the largest image to -4096 texels.</doc> -<bitfield high="17" low="17" name="POW2FIX2FLT"> -<value name="DIVIDE_BY_POW2" value="0"> -<doc>Divide by pow2-1 for fix2float (default)</doc> -</value> -<value name="DIVIDE_BY_POW2_FOR_FIX2FLOAT" value="1"> -<doc>Divide by pow2 for fix2float</doc> -</value> -</bitfield> -<doc>Optionally divide by 256 instead of 255 during fix2float. Can -only be asserted for 8-bit components.</doc> -<bitfield high="19" low="18" name="SEL_FILTER4"> -<value name="SELECT_TEXTURE_COMPONENT0" value="0"> -<doc>Select Texture Component0.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT1" value="1"> -<doc>Select Texture Component1.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT2" value="2"> -<doc>Select Texture Component2.</doc> -</value> -<value name="SELECT_TEXTURE_COMPONENT3" value="3"> -<doc>Select Texture Component3.</doc> -</value> -</bitfield> -<doc>If filter4 is enabled, specifies which texture component to -apply filter4 to.</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4540" stride="0x0004"> -<reg32 access="rw" name="TX_OFFSET" offset="0x0"> -<doc>Texture Offset State</doc> -<bitfield high="1" low="0" name="ENDIAN_SWAP"> -<use-enum ref="ENUM159" /> -</bitfield> -<doc>Endian Control</doc> -<bitfield high="2" low="2" name="MACRO_TILE"> -<use-enum ref="ENUM160" /> -</bitfield> -<doc>Macro Tile Control</doc> -<bitfield high="4" low="3" name="MICRO_TILE"> -<use-enum ref="ENUM161" /> -</bitfield> -<doc>Micro Tile Control</doc> -<bitfield high="31" low="5" name="TXOFFSET" /> -<doc>32-byte aligned pointer to base map</doc> -</reg32> -</stripe> -<stripe length="512" offset="0xA800" stride="0x0004"> -<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0"> -<doc>ALU Alpha Instruction</doc> -<bitfield high="3" low="0" name="ALPHA_OP"> -<value name="OP_MAD" value="0"> -<doc>OP_MAD: Result = A*B + C</doc> -</value> -<value name="OP_DP" value="1"> -<doc>OP_DP: Result = dot product from RGB ALU</doc> -</value> -<value name="OP_MIN" value="2"> -<doc>OP_MIN: Result = min(A,B)</doc> -</value> -<value name="OP_MAX" value="3"> -<doc>OP_MAX: Result = max(A,B)</doc> -</value> -<value name="OP_CND" value="5"> -<doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> -</value> -<value name="OP_CMP" value="6"> -<doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc> -</value> -<value name="OP_FRC" value="7"> -<doc>OP_FRC: Result = A-floor(A)</doc> -</value> -<value name="OP_EX" value="8"> -<doc>OP_EX</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result = 2^^A</doc> -</value> -<value name="OP_LN" value="9"> -<doc>OP_LN</doc> -</value> -<value name="RESULT" value="2"> -<doc>Result = log2(A)</doc> -</value> -<value name="OP_RCP" value="10"> -<doc>OP_RCP: Result = 1/A</doc> -</value> -<value name="OP_RSQ" value="11"> -<doc>OP_RSQ: Result = 1/sqrt(A)</doc> -</value> -<value name="OP_SIN" value="12"> -<doc>OP_SIN: Result = sin(A*2pi)</doc> -</value> -<value name="OP_COS" value="13"> -<doc>OP_COS: Result = cos(A*2pi)</doc> -</value> -<value name="OP_MDH" value="14"> -<doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is -always topright.src0 (source select and swizzles ignored). Input -modifiers are respected for all inputs.</doc> -</value> -<value name="OP_MDV" value="15"> -<doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is -always bottomleft.src0 (source select and swizzles ignored). Input -modifiers are respected for all inputs.</doc> -</value> -</bitfield> -<doc>Specifies the opcode for this instruction.</doc> -<bitfield high="10" low="4" name="ALPHA_ADDRD" /> -<doc>Specifies the address of the pixel stack frame register to -which the Alpha result of this instruction is to be written.</doc> -<bitfield high="11" low="11" name="ALPHA_ADDRD_REL"> -<use-enum ref="ENUM261" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -ALPHA_ADDRD before it is used. This implements relative -addressing.</doc> -<bitfield high="13" low="12" name="ALPHA_SEL_A"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for Alpha inputs A and B.</doc> -<bitfield high="16" low="14" name="ALPHA_SWIZ_A"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies the channel sources for Alpha inputs A and B.</doc> -<bitfield high="18" low="17" name="ALPHA_MOD_A"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for Alpha inputs A and B.</doc> -<bitfield high="20" low="19" name="ALPHA_SEL_B"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for Alpha inputs A and B.</doc> -<bitfield high="23" low="21" name="ALPHA_SWIZ_B"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies the channel sources for Alpha inputs A and B.</doc> -<bitfield high="25" low="24" name="ALPHA_MOD_B"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for Alpha inputs A and B.</doc> -<bitfield high="28" low="26" name="OMOD"> -<use-enum ref="ENUM264" /> -</bitfield> -<doc>Specifies the output modifier for this instruction.</doc> -<bitfield high="30" low="29" name="TARGET"> -<use-enum ref="ENUM265" /> -</bitfield> -<doc>This specifies which (cached) frame buffer target to write to. -For non-output ALU instructions, this specifies how to compare the -results against zero when setting the predicate bits.</doc> -<bitfield high="31" low="31" name="W_OMASK"> -<value name="NONE" value="0"> -<doc>NONE: Do not write output to w.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only to w.</doc> -</value> -</bitfield> -<doc>Specifies whether or not to write the Alpha component of the -result of this instuction to the depth output fifo.</doc> -</reg32> -</stripe> -<stripe length="512" offset="0x9800" stride="0x0004"> -<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0"> -<doc>This table specifies the Alpha source addresses and -pre-subtract operation for up to 512 ALU instruction. The ALU -expects 6 source operands - three for color (rgb0, rgb1, rgb2) and -three for alpha (a0, a1, a2). The pre-subtract operation creates -two more (rgbp and ap).</doc> -<bitfield high="7" low="0" name="ADDR0" /> -<doc>Specifies the identity of source operands a0, a1, and a2. If -the const field is set, this number ranges from 0 to 255 and -specifies a location within the constant register bank. Otherwise: -If the most significant bit is cleared, this field specifies a -location within the current pixel stack frame (ranging from 0 to -127). If the most significant bit is set, then the lower 7 bits -specify an inline unsigned floating- point constant with 4 bit -exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="8" low="8" name="ADDR0_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="9" low="9" name="ADDR0_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="17" low="10" name="ADDR1" /> -<doc>Specifies the identity of source operands a0, a1, and a2. If -the const field is set, this number ranges from 0 to 255 and -specifies a location within the constant register bank. Otherwise: -If the most significant bit is cleared, this field specifies a -location within the current pixel stack frame (ranging from 0 to -127). If the most significant bit is set, then the lower 7 bits -specify an inline unsigned floating- point constant with 4 bit -exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="18" low="18" name="ADDR1_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="19" low="19" name="ADDR1_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="27" low="20" name="ADDR2" /> -<doc>Specifies the identity of source operands a0, a1, and a2. If -the const field is set, this number ranges from 0 to 255 and -specifies a location within the constant register bank. Otherwise: -If the most significant bit is cleared, this field specifies a -location within the current pixel stack frame (ranging from 0 to -127). If the most significant bit is set, then the lower 7 bits -specify an inline unsigned floating- point constant with 4 bit -exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="28" low="28" name="ADDR2_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="29" low="29" name="ADDR2_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="31" low="30" name="SRCP_OP"> -<use-enum ref="ENUM168" /> -</bitfield> -<doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> -</reg32> -</stripe> -<stripe length="512" offset="0xB000" stride="0x0004"> -<reg32 access="rw" name="US_ALU_RGBA_INST" offset="0x0"> -<doc>ALU Shared RGBA Instruction</doc> -<bitfield high="3" low="0" name="RGB_OP"> -<value name="OP_MAD" value="0"> -<doc>OP_MAD: Result = A*B + C</doc> -</value> -<value name="OP_DP" value="1"> -<doc>OP_DP</doc> -</value> -<value name="RESULT" value="3"> -<doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc> -</value> -<value name="OP_DP" value="2"> -<doc>OP_DP</doc> -</value> -<value name="RESULT" value="4"> -<doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc> -</value> -<value name="OP_D2A" value="3"> -<doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc> -</value> -<value name="OP_MIN" value="4"> -<doc>OP_MIN: Result = min(A,B)</doc> -</value> -<value name="OP_MAX" value="5"> -<doc>OP_MAX: Result = max(A,B)</doc> -</value> -<value name="OP_CND" value="7"> -<doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> -</value> -<value name="OP_CMP" value="8"> -<doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc> -</value> -<value name="OP_FRC" value="9"> -<doc>OP_FRC: Result = A-floor(A)</doc> -</value> -<value name="OP_SOP" value="10"> -<doc>OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from Alpha ALU</doc> -</value> -<value name="OP_MDH" value="11"> -<doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is -always topright.src0 (source select and swizzles ignored). Input -modifiers are respected for all inputs.</doc> -</value> -<value name="OP_MDV" value="12"> -<doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is -always bottomleft.src0 (source select and swizzles ignored). Input -modifiers are respected for all inputs.</doc> -</value> -</bitfield> -<doc>Specifies the opcode for this instruction.</doc> -<bitfield high="10" low="4" name="RGB_ADDRD" /> -<doc>Specifies the address of the pixel stack frame register to -which the RGB result of this instruction is to be written.</doc> -<bitfield high="11" low="11" name="RGB_ADDRD_REL"> -<use-enum ref="ENUM261" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -RGB_ADDRD before it is used. This implements relative -addressing.</doc> -<bitfield high="13" low="12" name="RGB_SEL_C"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for RGB and Alpha input C.</doc> -<bitfield high="16" low="14" name="RED_SWIZ_C"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB and Alpha input -C.</doc> -<bitfield high="19" low="17" name="GREEN_SWIZ_C"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB and Alpha input -C.</doc> -<bitfield high="22" low="20" name="BLUE_SWIZ_C"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB and Alpha input -C.</doc> -<bitfield high="24" low="23" name="RGB_MOD_C"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for RGB and Alpha input C.</doc> -<bitfield high="26" low="25" name="ALPHA_SEL_C"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for RGB and Alpha input C.</doc> -<bitfield high="29" low="27" name="ALPHA_SWIZ_C"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB and Alpha input -C.</doc> -<bitfield high="31" low="30" name="ALPHA_MOD_C"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for RGB and Alpha input C.</doc> -</reg32> -</stripe> -<stripe length="512" offset="0xA000" stride="0x0004"> -<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0"> -<doc>ALU RGB Instruction</doc> -<bitfield high="1" low="0" name="RGB_SEL_A"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for RGB inputs A and B.</doc> -<bitfield high="4" low="2" name="RED_SWIZ_A"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="7" low="5" name="GREEN_SWIZ_A"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="10" low="8" name="BLUE_SWIZ_A"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="12" low="11" name="RGB_MOD_A"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for RGB inputs A and B.</doc> -<bitfield high="14" low="13" name="RGB_SEL_B"> -<use-enum ref="ENUM262" /> -</bitfield> -<doc>Specifies the operands for RGB inputs A and B.</doc> -<bitfield high="17" low="15" name="RED_SWIZ_B"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="20" low="18" name="GREEN_SWIZ_B"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="23" low="21" name="BLUE_SWIZ_B"> -<use-enum ref="ENUM263" /> -</bitfield> -<doc>Specifies, per channel, the sources for RGB inputs A and -B.</doc> -<bitfield high="25" low="24" name="RGB_MOD_B"> -<use-enum ref="ENUM167" /> -</bitfield> -<doc>Specifies the input modifiers for RGB inputs A and B.</doc> -<bitfield high="28" low="26" name="OMOD"> -<use-enum ref="ENUM264" /> -</bitfield> -<doc>Specifies the output modifier for this instruction.</doc> -<bitfield high="30" low="29" name="TARGET"> -<use-enum ref="ENUM265" /> -</bitfield> -<doc>This specifies which (cached) frame buffer target to write to. -For non-output ALU instructions, this specifies how to compare the -results against zero when setting the predicate bits.</doc> -<bitfield high="31" low="31" name="ALU_WMASK"> -<value name="DO_NOT_MODIFY_THE_CURRENT_ALU_RESULT" value="0"> -<doc>Do not modify the current ALU result.</doc> -</value> -<value name="MODIFY_THE_CURRENT_ALU_RESULT_BASED_ON_THE_SETTINGS_OF_ALU_RESULT_SEL_AND_ALU_RESULT_OP" -value="1"> -<doc>Modify the current ALU result based on the settings of -ALU_RESULT_SEL and ALU_RESULT_OP.</doc> -</value> -</bitfield> -<doc>Specifies whether to update the current ALU result.</doc> -</reg32> -</stripe> -<stripe length="512" offset="0x9000" stride="0x0004"> -<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0"> -<doc>This table specifies the RGB source addresses and pre-subtract -operation for up to 512 ALU instructions. The ALU expects 6 source -operands - three for color (rgb0, rgb1, rgb2) and three for alpha -(a0, a1, a2). The pre-subtract operation creates two more (rgbp and -ap).</doc> -<bitfield high="7" low="0" name="ADDR0" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. If the const field is set, this number ranges from 0 to 255 -and specifies a location within the constant register bank. -Otherwise: If the most significant bit is cleared, this field -specifies a location within the current pixel stack frame (ranging -from 0 to 127). If the most significant bit is set, then the lower -7 bits specify an inline unsigned floating-point constant with 4 -bit exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="8" low="8" name="ADDR0_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="9" low="9" name="ADDR0_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="17" low="10" name="ADDR1" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. If the const field is set, this number ranges from 0 to 255 -and specifies a location within the constant register bank. -Otherwise: If the most significant bit is cleared, this field -specifies a location within the current pixel stack frame (ranging -from 0 to 127). If the most significant bit is set, then the lower -7 bits specify an inline unsigned floating-point constant with 4 -bit exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="18" low="18" name="ADDR1_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="19" low="19" name="ADDR1_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="27" low="20" name="ADDR2" /> -<doc>Specifies the identity of source operands rgb0, rgb1, and -rgb2. If the const field is set, this number ranges from 0 to 255 -and specifies a location within the constant register bank. -Otherwise: If the most significant bit is cleared, this field -specifies a location within the current pixel stack frame (ranging -from 0 to 127). If the most significant bit is set, then the lower -7 bits specify an inline unsigned floating-point constant with 4 -bit exponent (bias 7) and 3 bit mantissa, including denormals but -excluding infinite/NaN.</doc> -<bitfield high="28" low="28" name="ADDR2_CONST"> -<use-enum ref="ENUM267" /> -</bitfield> -<doc>Specifies whether the associated address is a constant -register address or a temporary address / inline constant.</doc> -<bitfield high="29" low="29" name="ADDR2_REL"> -<use-enum ref="ENUM268" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="31" low="30" name="SRCP_OP"> -<use-enum ref="ENUM174" /> -</bitfield> -<doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> -</reg32> -</stripe> -<stripe length="512" offset="0xB800" stride="0x0004"> -<reg32 access="rw" name="US_CMN_INST" offset="0x0"> -<doc>Shared instruction fields for all instruction types</doc> -<bitfield high="1" low="0" name="TYPE"> -<value name="US_INST_TYPE_ALU" value="0"> -<doc>US_INST_TYPE_ALU: This instruction is an ALU -instruction.</doc> -</value> -<value name="US_INST_TYPE_OUT" value="1"> -<doc>US_INST_TYPE_OUT: This instruction is an output -instruction.</doc> -</value> -<value name="US_INST_TYPE_FC" value="2"> -<doc>US_INST_TYPE_FC: This instruction is a flow control -instruction.</doc> -</value> -<value name="US_INST_TYPE_TEX" value="3"> -<doc>US_INST_TYPE_TEX: This instruction is a texture -instruction.</doc> -</value> -</bitfield> -<doc>Specifies the type of instruction. Note that output -instructions write to render targets.</doc> -<bitfield high="2" low="2" name="TEX_SEM_WAIT"> -<value name="THIS_INSTRUCTION_MAY_ISSUE_IMMEDIATELY" value="0"> -<doc>This instruction may issue immediately.</doc> -</value> -<value name="THIS_INSTRUCTION_WILL_NOT_ISSUE_UNTIL_THE_TEXTURE_SEMAPHORE_IS_AVAILABLE" -value="1"> -<doc>This instruction will not issue until the texture semaphore is -available.</doc> -</value> -</bitfield> -<doc>Specifies whether to wait for the texture semaphore.</doc> -<bitfield high="5" low="3" name="RGB_PRED_SEL"> -<value name="US_PRED_SEL_NONE" value="0"> -<doc>US_PRED_SEL_NONE: No predication</doc> -</value> -<value name="US_PRED_SEL_RGBA" value="1"> -<doc>US_PRED_SEL_RGBA: Independent Channel Predication</doc> -</value> -<value name="US_PRED_SEL_RRRR" value="2"> -<doc>US_PRED_SEL_RRRR: R-Replicate Predication</doc> -</value> -<value name="US_PRED_SEL_GGGG" value="3"> -<doc>US_PRED_SEL_GGGG: G-Replicate Predication</doc> -</value> -<value name="US_PRED_SEL_BBBB" value="4"> -<doc>US_PRED_SEL_BBBB: B-Replicate Predication</doc> -</value> -<value name="US_PRED_SEL_AAAA" value="5"> -<doc>US_PRED_SEL_AAAA: A-Replicate Predication</doc> -</value> -</bitfield> -<doc>Specifies whether the instruction uses predication. For -ALU/TEX/Output this specifies predication for the RGB channels -only. For FC this specifies the predicate for the entire -instruction.</doc> -<bitfield high="6" low="6" name="RGB_PRED_INV"> -<use-enum ref="ENUM274" /> -</bitfield> -<doc>Specifies whether the predicate should be inverted. For -ALU/TEX/Output this specifies predication for the RGB channels -only. For FC this specifies the predicate for the entire -instruction.</doc> -<bitfield high="7" low="7" name="WRITE_INACTIVE"> -<value name="ONLY_WRITE_TO_CHANNELS_OF_ACTIVE_PIXELS" value="0"> -<doc>Only write to channels of active pixels</doc> -</value> -<value name="WRITE_TO_CHANNELS_OF_ALL_PIXELS" value="1"> -<doc>Write to channels of all pixels, including inactive -pixels</doc> -</value> -</bitfield> -<doc>Specifies which pixels to write to.</doc> -<bitfield high="8" low="8" name="LAST"> -<value name="DO_NOT_TERMINATE_THE_SHADER_AFTER_EXECUTING_THIS_INSTRUCTION" -value="0"> -<doc>Do not terminate the shader after executing this instruction -(unless this instruction is at END_ADDR).</doc> -</value> -<value name="ALL_ACTIVE_PIXELS_ARE_WILLING_TO_TERMINATE_AFTER_EXECUTING_THIS_INSTRUCTION" -value="1"> -<doc>All active pixels are willing to terminate after executing -this instruction. There is no guarantee that the shader will -actually terminate here. This feature is provided as a performance -optimization for tests where pixels can conditionally terminate -early.</doc> -</value> -</bitfield> -<doc>Specifies whether this is the last instruction.</doc> -<bitfield high="9" low="9" name="NOP"> -<value name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE" -value="0"> -<doc>Do not insert NOP instruction after this one.</doc> -</value> -<value name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE" value="1"> -<doc>Insert a NOP instruction after this one.</doc> -</value> -</bitfield> -<doc>Specifies whether to insert a NOP instruction after this. This -would get specified in order to meet dependency requirements for -the pre-subtract inputs, and dependency requirements for src0 of an -MDH/MDV instruction.</doc> -<bitfield high="10" low="10" name="ALU_WAIT"> -<value name="DO_NOT_WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION" -value="0"> -<doc>Do not wait for pending ALU instructions to complete before -issuing the current instruction.</doc> -</value> -<value name="WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION" -value="1"> -<doc>Wait for pending ALU instructions to complete before issuing -the current instruction.</doc> -</value> -</bitfield> -<doc>Specifies whether to wait for pending ALU instructions to -complete before issuing this instruction.</doc> -<bitfield high="13" low="11" name="RGB_WMASK"> -<use-enum ref="ENUM279" /> -</bitfield> -<doc>Specifies which components of the result of the RGB -instruction are written to the pixel stack frame.</doc> -<bitfield high="14" low="14" name="ALPHA_WMASK"> -<value name="NONE" value="0"> -<doc>NONE: Do not write register.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only.</doc> -</value> -</bitfield> -<doc>Specifies whether the result of the Alpha instruction is -written to the pixel stack frame.</doc> -<bitfield high="17" low="15" name="RGB_OMASK"> -<use-enum ref="ENUM279" /> -</bitfield> -<doc>Specifies which components of the result of the RGB -instruction are written to the output fifo if this is an output -instruction, and which predicate bits should be modified if this is -an ALU instruction.</doc> -<bitfield high="18" low="18" name="ALPHA_OMASK"> -<value name="NONE" value="0"> -<doc>NONE: Do not write output.</doc> -</value> -<value name="A" value="1"> -<doc>A: Write the alpha channel only.</doc> -</value> -</bitfield> -<doc>Specifies whether the result of the Alpha instruction is -written to the output fifo if this is an output instruction, and -whether the Alpha predicate bit should be modified if this is an -ALU instruction.</doc> -<bitfield high="19" low="19" name="RGB_CLAMP"> -<use-enum ref="ENUM171" /> -</bitfield> -<doc>Specifies RGB and Alpha clamp mode for this instruction.</doc> -<bitfield high="20" low="20" name="ALPHA_CLAMP"> -<use-enum ref="ENUM171" /> -</bitfield> -<doc>Specifies RGB and Alpha clamp mode for this instruction.</doc> -<bitfield high="21" low="21" name="ALU_RESULT_SEL"> -<value name="RED" value="0"> -<doc>RED: Use red as ALU result for FC.</doc> -</value> -<value name="ALPHA" value="1"> -<doc>ALPHA: Use alpha as ALU result for FC.</doc> -</value> -</bitfield> -<doc>Specifies which component of the result of this instruction -should be used as the `ALU result` by a subsequent flow control -instruction.</doc> -<bitfield high="22" low="22" name="ALPHA_PRED_INV"> -<use-enum ref="ENUM274" /> -</bitfield> -<doc>Specifies whether the predicate should be inverted. For -ALU/TEX/Output this specifies predication for the alpha channel -only. This field has no effect on FC instructions.</doc> -<bitfield high="24" low="23" name="ALU_RESULT_OP"> -<value name="EQUAL_TO" value="0"> -<doc>Equal to</doc> -</value> -<value name="LESS_THAN" value="1"> -<doc>Less than</doc> -</value> -<value name="GREATER_THAN_OR_EQUAL_TO" value="2"> -<doc>Greater than or equal to</doc> -</value> -<value name="NOT_EQUAL" value="3"> -<doc>Not equal</doc> -</value> -</bitfield> -<doc>Specifies how to compare the ALU result against zero for the -`alu_result` bit in a subsequent flow control instruction.</doc> -<bitfield high="27" low="25" name="ALPHA_PRED_SEL"> -<value name="US_PRED_SEL_NONE" value="0"> -<doc>US_PRED_SEL_NONE: No predication</doc> -</value> -<value name="US_PRED_SEL_RGBA" value="1"> -<doc>US_PRED_SEL_RGBA: A predication (identical to -US_PRED_SEL_AAAA)</doc> -</value> -<value name="US_PRED_SEL_RRRR" value="2"> -<doc>US_PRED_SEL_RRRR: R Predication</doc> -</value> -<value name="US_PRED_SEL_GGGG" value="3"> -<doc>US_PRED_SEL_GGGG: G Predication</doc> -</value> -<value name="US_PRED_SEL_BBBB" value="4"> -<doc>US_PRED_SEL_BBBB: B Predication</doc> -</value> -<value name="US_PRED_SEL_AAAA" value="5"> -<doc>US_PRED_SEL_AAAA: A Predication</doc> -</value> -</bitfield> -<doc>Specifies whether the instruction uses predication. For -ALU/TEX/Output this specifies predication for the alpha channel -only. This field has no effect on FC instructions.</doc> -<bitfield high="31" low="28" name="STAT_WE" /> -<doc>Specifies which components (R,G,B,A) contribute to the stat -count</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_CODE_ADDR" offset="0x4630"> -<doc>Code start and end instruction addresses.</doc> -<bitfield high="8" low="0" name="START_ADDR" /> -<doc>Specifies the address of the first instruction to execute in -the shader program. This address is relative to the shader program -offset given in US_CODE_OFFSET.OFFSET_ADDR.</doc> -<bitfield high="24" low="16" name="END_ADDR" /> -<doc>Specifies the address of the last instruction to execute in -the shader program. This address is relative to the shader program -offset given in US_CODE_OFFSET.OFFSET_ADDR. Shader program -execution will always terminate after the instruction at this -address is executed.</doc> -</reg32> -<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4638"> -<doc>Offsets used for relative instruction addresses in the shader -program, including START_ADDR, END_ADDR, and any non-global flow -control jump addresses.</doc> -<bitfield high="8" low="0" name="OFFSET_ADDR" /> -<doc>Specifies the offset to add to relative instruction addresses, -including START_ADDR, END_ADDR, and some flow control jump -addresses.</doc> -</reg32> -<reg32 access="rw" name="US_CODE_RANGE" offset="0x4634"> -<doc>Range of instructions that contains the current shader -program.</doc> -<bitfield high="8" low="0" name="CODE_ADDR" /> -<doc>Specifies the start address of the current code window. This -address is an absolute address.</doc> -<bitfield high="24" low="16" name="CODE_SIZE" /> -<doc>Specifies the size of the current code window, minus one. The -last instruction in the code window is given by CODE_ADDR + -CODE_SIZE.</doc> -</reg32> -<reg32 access="rw" name="US_CONFIG" offset="0x4600"> -<doc>Shader Configuration</doc> -<bitfield high="0" low="0" name="Reserved" /> -<doc>Set to 0</doc> -<bitfield high="1" low="1" name="ZERO_TIMES_ANYTHING_EQUALS_ZERO"> -<value name="DEFAULT_BEHAVIOUR" value="0"> -<doc>Default behaviour (0*inf=nan,0*nan=nan)</doc> -</value> -<value name="LEGACY_BEHAVIOUR_FOR_SHADER_MODEL_1" value="1"> -<doc>Legacy behaviour for shader model 1 (0*anything=0)</doc> -</value> -</bitfield> -<doc>Control how ALU multiplier behaves when one argument is zero. -This affects the multiplier used in MAD and dot product -calculations.</doc> -</reg32> -<stripe length="512" offset="0xA000" stride="0x0004"> -<reg32 access="rw" name="US_FC_ADDR" offset="0x0"> -<doc>Flow Control Instruction Address Fields</doc> -<bitfield high="4" low="0" name="BOOL_ADDR" /> -<doc>The address of the static boolean register to use in the jump -function.</doc> -<bitfield high="12" low="8" name="INT_ADDR" /> -<doc>The address of the static integer register to use for loop/rep -and endloop/endrep.</doc> -<bitfield high="24" low="16" name="JUMP_ADDR" /> -<doc>The address to jump to if the jump function evaluates to -true.</doc> -<bitfield high="31" low="31" name="JUMP_GLOBAL"> -<value name="ADD_THE_SHADER_PROGRAM_OFFSET_IN_US_CODE_OFFSET" -value="0"> -<doc>Add the shader program offset in US_CODE_OFFSET.OFFSET_ADDR -when calculating the destination address of a jump</doc> -</value> -<value name="DON" value="1"> -<doc>Don`t use the shader program offset when calculating the -destination address jump</doc> -</value> -</bitfield> -<doc>Specifies whether to interpret JUMP_ADDR as a global -address.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_FC_BOOL_CONST" offset="0x4620"> -<doc>Static Boolean Constants for Flow Control Branching -Instructions. Quad-buffered.</doc> -</reg32> -<reg32 access="rw" name="US_FC_CTRL" offset="0x4624"> -<doc>Flow Control Options. Quad-buffered.</doc> -<bitfield high="30" low="30" name="TEST_EN"> -<value name="NORMAL_MODE" value="0"> -<doc>Normal mode</doc> -</value> -<value name="TEST_MODE" value="1"> -<doc>Test mode (currently unused)</doc> -</value> -</bitfield> -<doc>Specifies whether test mode is enabled. This flag currently -has no effect in hardware.</doc> -<bitfield high="31" low="31" name="FULL_FC_EN"> -<value name="USE_PARTIAL_FLOW" value="0"> -<doc>Use partial flow-control (enables twice the contexts). Loops -and subroutines are not available in partial flow-control mode, and -the nesting depth of branch statements is limited.</doc> -</value> -<value name="USE_FULL_PIXEL_SHADER_3" value="1"> -<doc>Use full pixel shader 3.0 flow control, including loops and -subroutines.</doc> -</value> -</bitfield> -<doc>Specifies whether full flow control functionality is -enabled.</doc> -</reg32> -<stripe length="512" offset="0x9800" stride="0x0004"> -<reg32 access="rw" name="US_FC_INST" offset="0x0"> -<doc>Flow Control Instruction</doc> -<bitfield high="2" low="0" name="OP"> -<value name="US_FC_OP_JUMP" value="0"> -<doc>US_FC_OP_JUMP: (if, endif, call, etc)</doc> -</value> -<value name="US_FC_OP_LOOP" value="1"> -<doc>US_FC_OP_LOOP: same as jump except always take the jump if the -static counter is 0. If we don`t take the jump, push initial loop -counter and loop register (aL) values onto the loop stack.</doc> -</value> -<value name="US_FC_OP_ENDLOOP" value="2"> -<doc>US_FC_OP_ENDLOOP: same as jump but decrement the loop counter -and increment the loop register (aL), and don`t take the jump if -the loop counter becomes zero.</doc> -</value> -<value name="US_FC_OP_REP" value="3"> -<doc>US_FC_OP_REP: same as loop but don`t push the loop register -aL.</doc> -</value> -<value name="US_FC_OP_ENDREP" value="4"> -<doc>US_FC_OP_ENDREP: same as endloop but don`t update/pop the loop -register aL.</doc> -</value> -<value name="US_FC_OP_BREAKLOOP" value="5"> -<doc>US_FC_OP_BREAKLOOP: same as jump but pops the loop stacks if a -pixel stops being active.</doc> -</value> -<value name="US_FC_OP_BREAKREP" value="6"> -<doc>US_FC_OP_BREAKREP: same as breakloop but don`t pop the loop -register if it jumps.</doc> -</value> -<value name="US_FC_OP_CONTINUE" value="7"> -<doc>US_FC_OP_CONTINUE: used to disable pixels that are ready to -jump to the ENDLOOP/ENDREP instruction.</doc> -</value> -</bitfield> -<doc>Specifies the type of flow control instruction.</doc> -<bitfield high="4" low="4" name="B_ELSE"> -<value name="DON" value="0"> -<doc>Don`t alter the branch state before executing the -instruction.</doc> -</value> -<value name="PERFORM_AN_ELSE_OPERATION_ON_THE_BRANCH_STATE_BEFORE_EXECUTING_THE_INSTRUCTION" -value="1"> -<doc>Perform an else operation on the branch state before executing -the instruction; pixels in the active state are moved to the branch -inactive state with zero counter, and vice versa.</doc> -</value> -</bitfield> -<doc>Specifies whether to perform an else operation on the active -and branch-inactive pixels before executing the instruction.</doc> -<bitfield high="5" low="5" name="JUMP_ANY"> -<value name="JUMP_IF_ALL_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP" -value="0"> -<doc>Jump if ALL active pixels want to take the jump (for if and -else). If no pixels are active, jump.</doc> -</value> -<value name="JUMP_IF_ANY_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP" -value="1"> -<doc>Jump if ANY active pixels want to take the jump (for call, -loop/rep and endrep/endloop). If no pixels are active, do not -jump.</doc> -</value> -</bitfield> -<doc>If set, jump if any active pixels want to take the jump -(otherwise the instruction jumps only if all active pixels want -to).</doc> -<bitfield high="7" low="6" name="A_OP"> -<value name="US_FC_A_OP_NONE" value="0"> -<doc>US_FC_A_OP_NONE: Don`t change the address stack</doc> -</value> -<value name="US_FC_A_OP_POP" value="1"> -<doc>US_FC_A_OP_POP: If we jump, pop the address stack and use that -value for the jump target</doc> -</value> -<value name="US_FC_A_OP_PUSH" value="2"> -<doc>US_FC_A_OP_PUSH: If we jump, push the current address onto the -address stack</doc> -</value> -</bitfield> -<doc>The address stack operation to perform if we take the -jump.</doc> -<bitfield high="15" low="8" name="JUMP_FUNC" /> -<doc>A 2x2x2 table of boolean values indicating whether to take the -jump. The table index is indexed by {ALU Compare Result, -Predication Result, Boolean Value (from the static boolean address -in US_FC_ADDR.BOOL)}. To determine whether to jump, look at bit -((alu_result<<2) | (predicate<<1) | bool).</doc> -<bitfield high="20" low="16" name="B_POP_CNT" /> -<doc>The amount to decrement the branch counter by if -US_FC_B_OP_DECR operation is performed.</doc> -<bitfield high="25" low="24" name="B_OP0"> -<value name="US_FC_B_OP_NONE" value="0"> -<doc>US_FC_B_OP_NONE: If we don`t jump, don`t alter the branch -counter for any pixel.</doc> -</value> -<value name="US_FC_B_OP_DECR" value="1"> -<doc>US_FC_B_OP_DECR: If we don`t jump, decrement branch counter by -B_POP_CNT for inactive pixels. Activate pixels with negative -counters.</doc> -</value> -<value name="US_FC_B_OP_INCR" value="2"> -<doc>US_FC_B_OP_INCR: If we don`t jump, increment branch counter by -1 for inactive pixels. Deactivate pixels that decided to jump and -set their counter to zero.</doc> -</value> -</bitfield> -<doc>The branch state operation to perform if we don`t take the -jump.</doc> -<bitfield high="27" low="26" name="B_OP1"> -<value name="US_FC_B_OP_NONE" value="0"> -<doc>US_FC_B_OP_NONE: If we do jump, don`t alter the branch counter -for any pixel.</doc> -</value> -<value name="US_FC_B_OP_DECR" value="1"> -<doc>US_FC_B_OP_DECR: If we do jump, decrement branch counter by -B_POP_CNT for inactive pixels. Activate pixels with negative -counters.</doc> -</value> -<value name="US_FC_B_OP_INCR" value="2"> -<doc>US_FC_B_OP_INCR: If we do jump, increment branch counter by 1 -for inactive pixels. Deactivate pixels that decided not to jump and -set their counter to zero.</doc> -</value> -</bitfield> -<doc>The branch state operation to perform if we do take the -jump.</doc> -<bitfield high="28" low="28" name="IGNORE_UNCOVERED"> -<value name="INCLUDE_UNCOVERED_PIXELS_IN_JUMP_DECISIONS" value="0"> -<doc>Include uncovered pixels in jump decisions</doc> -</value> -<value name="IGNORE_UNCOVERED_PIXELS_IN_MAKING_JUMP_DECISIONS" -value="1"> -<doc>Ignore uncovered pixels in making jump decisions</doc> -</value> -</bitfield> -<doc>If set, uncovered pixels will not participate in flow control -decisions.</doc> -</reg32> -</stripe> -<stripe length="32" offset="0x4C00" stride="0x0004"> -<reg32 access="rw" name="US_FC_INT_CONST" offset="0x0"> -<doc>Integer Constants used by Flow Control Loop Instructions. -Single buffered.</doc> -<bitfield high="7" low="0" name="KR" /> -<doc>Specifies the number of iterations. Unsigned 8-bit integer in -[0, 255].</doc> -<bitfield high="15" low="8" name="KG" /> -<doc>Specifies the initial value of the loop register (aL). -Unsigned 8-bit integer in [0, 255].</doc> -<bitfield high="23" low="16" name="KB" /> -<doc>Specifies the increment used to change the loop register (aL) -on each iteration. Signed 7-bit integer in [-128, 127].</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x4640" stride="0x0004"> -<reg32 access="rw" name="US_FORMAT0" offset="0x0"> -<bitfield high="25" low="22" name="TXDEPTH"> -<value name="WIDTH" value="13"> -<doc>width > 2048, height <= 2048</doc> -</value> -<value name="WIDTH" value="14"> -<doc>width <= 2048, height > 2048</doc> -</value> -<value name="WIDTH" value="15"> -<doc>width > 2048, height > 2048</doc> -</value> -</bitfield> -<doc /> -</reg32> -</stripe> -<stripe length="4" offset="0x46A4" stride="0x0004"> -<reg32 access="rw" name="US_OUT_FMT" offset="0x0"> -<bitfield high="4" low="0" name="OUT_FMT"> -<use-enum ref="ENUM179" /> -</bitfield> -<doc /> -<bitfield high="9" low="8" name="C0_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc /> -<bitfield high="11" low="10" name="C1_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc /> -<bitfield high="13" low="12" name="C2_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc /> -<bitfield high="15" low="14" name="C3_SEL"> -<use-enum ref="ENUM180" /> -</bitfield> -<doc /> -<bitfield high="20" low="20" name="ROUND_ADJ"> -<value name="NORMAL_ROUNDING" value="0"> -<doc>Normal rounding</doc> -</value> -<value name="MODIFIED_ROUNDING_OF_FIXED" value="1"> -<doc>Modified rounding of fixed-point data</doc> -</value> -</bitfield> -<doc /> -</reg32> -</stripe> -<reg32 access="rw" name="US_PIXSIZE" offset="0x4604"> -<doc>Shader pixel size. This register specifies the size and -partitioning of the current pixel stack frame</doc> -<bitfield high="6" low="0" name="PIX_SIZE" /> -<doc>Specifies the total size of the current pixel stack frame -(1:128)</doc> -</reg32> -<stripe length="512" offset="0x9800" stride="0x0004"> -<reg32 access="rw" name="US_TEX_ADDR" offset="0x0"> -<doc>Texture addresses and swizzles</doc> -<bitfield high="6" low="0" name="SRC_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the texture address for this instruction</doc> -<bitfield high="7" low="7" name="SRC_ADDR_REL"> -<use-enum ref="ENUM298" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="9" low="8" name="SRC_S_SWIZ"> -<use-enum ref="ENUM299" /> -</bitfield> -<doc>Specify which colour channel of src_addr to use for S -coordinate</doc> -<bitfield high="11" low="10" name="SRC_T_SWIZ"> -<use-enum ref="ENUM300" /> -</bitfield> -<doc>Specify which colour channel of src_addr to use for T -coordinate</doc> -<bitfield high="13" low="12" name="SRC_R_SWIZ"> -<use-enum ref="ENUM301" /> -</bitfield> -<doc>Specify which colour channel of src_addr to use for R -coordinate</doc> -<bitfield high="15" low="14" name="SRC_Q_SWIZ"> -<use-enum ref="ENUM302" /> -</bitfield> -<doc>Specify which colour channel of src_addr to use for Q -coordinate</doc> -<bitfield high="22" low="16" name="DST_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the returned texture data for this instruction</doc> -<bitfield high="23" low="23" name="DST_ADDR_REL"> -<value name="NONE" value="0"> -<doc>NONE: Do not modify destination address</doc> -</value> -<value name="RELATIVE" value="1"> -<doc>RELATIVE: Add aL before lookup.</doc> -</value> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="25" low="24" name="DST_R_SWIZ"> -<value name="WRITE_R_CHANNEL_TO_R_CHANNEL" value="0"> -<doc>Write R channel to R channel</doc> -</value> -<value name="WRITE_G_CHANNEL_TO_R_CHANNEL" value="1"> -<doc>Write G channel to R channel</doc> -</value> -<value name="WRITE_B_CHANNEL_TO_R_CHANNEL" value="2"> -<doc>Write B channel to R channel</doc> -</value> -<value name="WRITE_A_CHANNEL_TO_R_CHANNEL" value="3"> -<doc>Write A channel to R channel</doc> -</value> -</bitfield> -<doc>Specify which colour channel of the returned texture data to -write to the red channel of dst_addr</doc> -<bitfield high="27" low="26" name="DST_G_SWIZ"> -<value name="WRITE_R_CHANNEL_TO_G_CHANNEL" value="0"> -<doc>Write R channel to G channel</doc> -</value> -<value name="WRITE_G_CHANNEL_TO_G_CHANNEL" value="1"> -<doc>Write G channel to G channel</doc> -</value> -<value name="WRITE_B_CHANNEL_TO_G_CHANNEL" value="2"> -<doc>Write B channel to G channel</doc> -</value> -<value name="WRITE_A_CHANNEL_TO_G_CHANNEL" value="3"> -<doc>Write A channel to G channel</doc> -</value> -</bitfield> -<doc>Specify which colour channel of the returned texture data to -write to the green channel of dst_addr</doc> -<bitfield high="29" low="28" name="DST_B_SWIZ"> -<value name="WRITE_R_CHANNEL_TO_B_CHANNEL" value="0"> -<doc>Write R channel to B channel</doc> -</value> -<value name="WRITE_G_CHANNEL_TO_B_CHANNEL" value="1"> -<doc>Write G channel to B channel</doc> -</value> -<value name="WRITE_B_CHANNEL_TO_B_CHANNEL" value="2"> -<doc>Write B channel to B channel</doc> -</value> -<value name="WRITE_A_CHANNEL_TO_B_CHANNEL" value="3"> -<doc>Write A channel to B channel</doc> -</value> -</bitfield> -<doc>Specify which colour channel of the returned texture data to -write to the blue channel of dst_addr</doc> -<bitfield high="31" low="30" name="DST_A_SWIZ"> -<value name="WRITE_R_CHANNEL_TO_A_CHANNEL" value="0"> -<doc>Write R channel to A channel</doc> -</value> -<value name="WRITE_G_CHANNEL_TO_A_CHANNEL" value="1"> -<doc>Write G channel to A channel</doc> -</value> -<value name="WRITE_B_CHANNEL_TO_A_CHANNEL" value="2"> -<doc>Write B channel to A channel</doc> -</value> -<value name="WRITE_A_CHANNEL_TO_A_CHANNEL" value="3"> -<doc>Write A channel to A channel</doc> -</value> -</bitfield> -<doc>Specify which colour channel of the returned texture data to -write to the alpha channel of dst_addr</doc> -</reg32> -</stripe> -<stripe length="512" offset="0xA000" stride="0x0004"> -<reg32 access="rw" name="US_TEX_ADDR_DXDY" offset="0x0"> -<doc>Additional texture addresses and swizzles for DX/DY -inputs</doc> -<bitfield high="6" low="0" name="DX_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the DX value for this instruction</doc> -<bitfield high="7" low="7" name="DX_ADDR_REL"> -<use-enum ref="ENUM298" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="9" low="8" name="DX_S_SWIZ"> -<use-enum ref="ENUM299" /> -</bitfield> -<doc>Specify which colour channel of dx_addr to use for S -coordinate</doc> -<bitfield high="11" low="10" name="DX_T_SWIZ"> -<use-enum ref="ENUM300" /> -</bitfield> -<doc>Specify which colour channel of dx_addr to use for T -coordinate</doc> -<bitfield high="13" low="12" name="DX_R_SWIZ"> -<use-enum ref="ENUM301" /> -</bitfield> -<doc>Specify which colour channel of dx_addr to use for R -coordinate</doc> -<bitfield high="15" low="14" name="DX_Q_SWIZ"> -<use-enum ref="ENUM302" /> -</bitfield> -<doc>Specify which colour channel of dx_addr to use for Q -coordinate</doc> -<bitfield high="22" low="16" name="DY_ADDR" /> -<doc>Specifies the location (within the shader pixel stack frame) -of the DY value for this instruction</doc> -<bitfield high="23" low="23" name="DY_ADDR_REL"> -<use-enum ref="ENUM298" /> -</bitfield> -<doc>Specifies whether the loop register is added to the value of -the associated address before it is used. This implements relative -addressing.</doc> -<bitfield high="25" low="24" name="DY_S_SWIZ"> -<use-enum ref="ENUM299" /> -</bitfield> -<doc>Specify which colour channel of dy_addr to use for S -coordinate</doc> -<bitfield high="27" low="26" name="DY_T_SWIZ"> -<use-enum ref="ENUM300" /> -</bitfield> -<doc>Specify which colour channel of dy_addr to use for T -coordinate</doc> -<bitfield high="29" low="28" name="DY_R_SWIZ"> -<use-enum ref="ENUM301" /> -</bitfield> -<doc>Specify which colour channel of dy_addr to use for R -coordinate</doc> -<bitfield high="31" low="30" name="DY_Q_SWIZ"> -<use-enum ref="ENUM302" /> -</bitfield> -<doc>Specify which colour channel of dy_addr to use for Q -coordinate</doc> -</reg32> -</stripe> -<stripe length="512" offset="0x9000" stride="0x0004"> -<reg32 access="rw" name="US_TEX_INST" offset="0x0"> -<doc>Texture Instruction</doc> -<bitfield high="19" low="16" name="TEX_ID" /> -<doc>Specifies the id of the texture map used for this -instruction</doc> -<bitfield high="24" low="22" name="INST"> -<value name="NOP" value="0"> -<doc>NOP: Do nothing</doc> -</value> -<value name="LD" value="1"> -<doc>LD: Do Texture Lookup (S,T,R)</doc> -</value> -<value name="TEXKILL" value="2"> -<doc>TEXKILL: Kill pixel if any component is < 0</doc> -</value> -<value name="PROJ" value="3"> -<doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc> -</value> -<value name="LODBIAS" value="4"> -<doc>LODBIAS: Do texture lookup with lod bias</doc> -</value> -<value name="LOD" value="5"> -<doc>LOD: Do texture lookup with explicit lod</doc> -</value> -<value name="DXDY" value="6"> -<doc>DXDY: Do texture lookup with lod calculated from DX and -DY</doc> -</value> -</bitfield> -<doc>Specifies the operation taking place for this -instruction</doc> -<bitfield high="25" low="25" name="TEX_SEM_ACQUIRE"> -<value name="DON" value="0"> -<doc>Don`t hold the texture semaphore</doc> -</value> -<value name="HOLD_THE_TEXTURE_SEMAPHORE_UNTIL_THE_DATA_IS_WRITTEN_TO_THE_TEMPORARY_REGISTER" -value="1"> -<doc>Hold the texture semaphore until the data is written to the -temporary register.</doc> -</value> -</bitfield> -<doc>Whether to hold the texture semaphore until the data is -written to the temporary register.</doc> -<bitfield high="26" low="26" name="IGNORE_UNCOVERED"> -<value name="FETCH_TEXELS_FOR_UNCOVERED_PIXELS" value="0"> -<doc>Fetch texels for uncovered pixels</doc> -</value> -<value name="DON" value="1"> -<doc>Don`t fetch texels for uncovered pixels</doc> -</value> -</bitfield> -<doc>If set, US will not request data for pixels which are -uncovered. Clear this bit for indirect texture lookups.</doc> -<bitfield high="27" low="27" name="UNSCALED"> -<value name="SCALE_THE_S" value="0"> -<doc>Scale the S, T, R texture coordinates from [0.0,1.0] to the -dimensions of the target texture</doc> -</value> -<value name="USE_THE_UNSCALED_S" value="1"> -<doc>Use the unscaled S, T, R texture coordates.</doc> -</value> -</bitfield> -<doc>Whether to scale texture coordinates when sending them to the -texture unit.</doc> -</reg32> -</stripe> -<reg32 access="rw" name="US_W_FMT" offset="0x46B4"> -<doc>Specifies the source and format for the Depth (W) value output -by the shader</doc> -<bitfield high="1" low="0" name="W_FMT"> -<value name="W" value="0"> -<doc>W</doc> -</value> -<value name="W_IS_ALWAYS_ZERO" value="0"> -<doc>W is always zero</doc> -</value> -<value name="W" value="1"> -<doc>W</doc> -</value> -<value name="24" value="24"> -<doc>24-bit fixed point</doc> -</value> -<value name="W24_FP" value="2"> -<doc>W24_FP - 24-bit floating point. The floating point values are -a special format that preserve sorting order when values are -compared as integers, allowing higher precision in W without -additional logic in other blocks.</doc> -</value> -</bitfield> -<doc>Format for W</doc> -<bitfield high="2" low="2" name="W_SRC"> -<use-enum ref="ENUM183" /> -</bitfield> -<doc>Source for W</doc> -</reg32> -<reg32 access="rw" name="VAP_ALT_NUM_VERTICES" offset="0x2088"> -<doc>Alternate Number of Vertices to allow > 16-bits of Vertex -count</doc> -<bitfield high="23" low="0" name="NUM_VERTICES" /> -<doc>24-bit vertex count for command packet. Used instead of bits -31:16 of VAP_VF_CNTL if VAP_VF_CNTL.USE_ALT_NUM_VERTS is set.</doc> -</reg32> -<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C"> -<doc>Control Bits for User Clip Planes and Clipping</doc> -<bitfield high="0" low="0" name="UCP_ENA_0" /> -<doc>Enable User Clip Plane 0</doc> -<bitfield high="1" low="1" name="UCP_ENA_1" /> -<doc>Enable User Clip Plane 1</doc> -<bitfield high="2" low="2" name="UCP_ENA_2" /> -<doc>Enable User Clip Plane 2</doc> -<bitfield high="3" low="3" name="UCP_ENA_3" /> -<doc>Enable User Clip Plane 3</doc> -<bitfield high="4" low="4" name="UCP_ENA_4" /> -<doc>Enable User Clip Plane 4</doc> -<bitfield high="5" low="5" name="UCP_ENA_5" /> -<doc>Enable User Clip Plane 5</doc> -<bitfield high="15" low="14" name="PS_UCP_MODE" /> -<doc>0 = Cull using distance from center of point 1 = Cull using -radius-based distance from center of point 2 = Cull using -radius-based distance from center of point, Expand and Clip on -intersection 3 = Always expand and clip as trifan</doc> -<bitfield high="16" low="16" name="CLIP_DISABLE" /> -<doc>Disables clip code generation and clipping process for -TCL</doc> -<bitfield high="17" low="17" name="UCP_CULL_ONLY_ENA" /> -<doc>Cull Primitives against UCPS, but don`t clip</doc> -<bitfield high="18" low="18" name="BOUNDARY_EDGE_FLAG_ENA" /> -<doc>If set, boundary edges are highlighted, else they are not -highlighted</doc> -<bitfield high="20" low="20" name="COLOR2_IS_TEXTURE" /> -<doc>If set, color2 is used as texture8 by GA (PS3.0 -requirement)</doc> -<bitfield high="21" low="21" name="COLOR3_IS_TEXTURE" /> -<doc>If set, color3 is used as texture9 by GA (PS3.0 -requirement)</doc> -</reg32> -<reg32 access="rw" name="VAP_CNTL" offset="0x2080"> -<doc>Vertex Assembler/Processor Control Register</doc> -<bitfield high="3" low="0" name="PVS_NUM_SLOTS" /> -<doc>Specifies the number of vertex slots to be used in the VAP PVS -process. A slot represents a single vertex storage location1 across -multiple engines (one vertex per engine). By decreasing the number -of slots, there is more memory for each vertex, but less parallel -processing. Similarly, by increasing the number of slots, there is -less memory per vertex but more vertices being processed in -parallel.</doc> -<bitfield high="7" low="4" name="PVS_NUM_CNTLRS" /> -<doc>Specifies the maximum number of controllers to be processing -in parallel. In general should be set to max value of TBD. Can be -changed for performance analysis.</doc> -<bitfield high="11" low="8" name="PVS_NUM_FPUS" /> -<doc>Specifies the number of Floating Point Units (Vector/Math -Engines) to use when processing vertices.</doc> -<bitfield high="17" low="17" name="VAP_NO_RENDER" /> -<doc>If set, VAP will not process any draw commands (i.e. writes to -VAP_VF_CNTL, the INDX and DATAPORT and Immediate mode writes are -ignored.</doc> -<bitfield high="21" low="18" name="VF_MAX_VTX_NUM" /> -<doc>This field controls the number of vertices that the vertex -fetcher manages for the TCL and Setup Vertex Storage memories (and -therefore the number of vertices that can be re-used). This value -should be set to 12 for most operation, This number may be modified -for performance evaluation. The value is the maximum vertex number -used which is one less than the number of vertices (i.e. a 12 means -13 vertices will be used)</doc> -<bitfield high="22" low="22" name="DX_CLIP_SPACE_DEF"> -<use-enum ref="ENUM184" /> -</bitfield> -<doc>Clip space is defined as:</doc> -<bitfield high="23" low="23" name="TCL_STATE_OPTIMIZATION" /> -<doc>If set, enables the TCL state optimization, and the new state -is used only if there is a change in TCL state, between VF_CNTL -(triggers)</doc> -</reg32> -<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140"> -<doc>Vertex Assemblen/Processor Control Status</doc> -<bitfield high="1" low="0" name="VC_SWAP" /> -<doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD -becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3 -= Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB Default = 0</doc> -<bitfield high="8" low="8" name="PVS_BYPASS" /> -<doc>The TCL engine is logically or physically removed from the -circuit.</doc> -<bitfield high="11" low="11" name="PVS_BUSY" /> -<doc>Transform/Clip/Light (TCL) Engine is Busy. Read-only.</doc> -<bitfield high="19" low="16" name="MAX_MPS" /> -<doc>Maximum number of MPs fused for this chip. Read- only. For -A11, fusemask is fixed to 1XXX. For A12, -CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 000 => max_mps[3:0] = 1XXX -=> 8 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 001 => -max_mps[3:0] = 0110 => 6 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = -010 => max_mps[3:0] = 0101 => 5 MPs -CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 011 => max_mps[3:0] = 0100 -=> 4 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 100 => -max_mps[3:0] = 0011 => 3 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = -101 => max_mps[3:0] = 0010 => 2 MPs -CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 110 => max_mps[3:0] = 0001 -=> 1 MP CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 111 => -max_mps[3:0] = 0000 => 0 MP Note that max_mps[3:0] = 0111 = 7 -MPs is not available</doc> -<bitfield high="24" low="24" name="VS_BUSY" /> -<doc>Vertex Store is Busy. Read-only.</doc> -<bitfield high="25" low="25" name="RCP_BUSY" /> -<doc>Reciprocal Engine is Busy. Read-only.</doc> -<bitfield high="26" low="26" name="VTE_BUSY" /> -<doc>ViewPort Transform Engine is Busy. Read-only.</doc> -<bitfield high="27" low="27" name="MIU_BUSY" /> -<doc>Memory Interface Unit is Busy. Read-only.</doc> -<bitfield high="28" low="28" name="VC_BUSY" /> -<doc>Vertex Cache is Busy. Read-only.</doc> -<bitfield high="29" low="29" name="VF_BUSY" /> -<doc>Vertex Fetcher is Busy. Read-only.</doc> -<bitfield high="30" low="30" name="REGPIPE_BUSY" /> -<doc>Register Pipeline is Busy. Read-only.</doc> -<bitfield high="31" low="31" name="VAP_BUSY" /> -<doc>VAP Engine is Busy. Read-only.</doc> -</reg32> -<reg32 access="rw" name="VAP_INDEX_OFFSET" offset="0x208C"> -<doc>Offset Value added to index value in both Indexed and -Auto-indexed modes. Disabled by setting to 0</doc> -<bitfield high="24" low="0" name="INDEX_OFFSET" /> -<doc>25-bit signed 2`s comp offset value</doc> -</reg32> -<stripe length="8" offset="0x2150" stride="0x0004"> -<reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0"> -<doc>Programmable Stream Control Word 0</doc> -<bitfield high="3" low="0" name="DATA_TYPE_0" /> -<doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 -= FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 -(4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) -(X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * -(Same as BYTE except has X->Z,Z- >X swap for D3D color def) -(Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 -DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z -= 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit -fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 -[15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit -fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) -9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point -values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) 10 = -FLOAT_8 (8 IEEE Floats) Sames as 2 FLOAT_4 but must use consecutive -DST_VEC_LOC. Used to allow > 16 PSC for OGL path. 11 = FLT16_2 -(1 DWORD with 2 16-bit floating point values (SE5M10 exp bias of -15, supports denormalized numbers)) (X = [15:0], Y = [31:16], Z = -0.0, W = 1.0) 12 = FLT16_4 (2 DWORDS with 4(2 per dword) 16-bit -floating point values (SE5M10 exp bias of 15, supports denormalized -numbers))) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = -DW1 [31:16]) * These data types use the SIGNED and NORMALIZE flags -described below.</doc> -<bitfield high="7" low="4" name="SKIP_DWORDS_0" /> -<doc>The number of DWORDS to skip (discard) after processing the -current element.</doc> -<bitfield high="12" low="8" name="DST_VEC_LOC_0" /> -<doc>The vector address in the input memory to write this -element</doc> -<bitfield high="13" low="13" name="LAST_VEC_0" /> -<doc>If set, indicates the last vector of the current vertex -stream</doc> -<bitfield high="14" low="14" name="SIGNED_0" /> -<doc>Determines whether fixed point data types are unsigned (0) or -2`s complement signed (1) data types. See NORMALIZE for complete -description of affect</doc> -<bitfield high="15" low="15" name="NORMALIZE_0"> -<use-enum ref="ENUM185" /> -</bitfield> -<doc>Determines whether the fixed to floating point conversion will -normalize the value (i.e. fixed point value is all fractional bits) -or not (i.e. fixed point value is all integer bits). This table -describes the fixed to float conversion results SIGNED NORMALIZE -FLT RANGE 0 0 0.0 - (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 -0.0 - 1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - -127.0) 1 1 -1.0 - 1.0 where n is the number of bits in the -associated fixed point value For signed, normalize conversion, -since the fixed point range is not evenly distributed around 0, -there are 3 different methods supported by R300. See the -VAP_PSC_SGN_NORM_CNTL description for details.</doc> -<bitfield high="19" low="16" name="DATA_TYPE_1" /> -<doc>Similar to DATA_TYPE_0</doc> -<bitfield high="23" low="20" name="SKIP_DWORDS_1" /> -<doc>See SKIP_DWORDS_0</doc> -<bitfield high="28" low="24" name="DST_VEC_LOC_1" /> -<doc>See DST_VEC_LOC_0</doc> -<bitfield high="29" low="29" name="LAST_VEC_1" /> -<doc>See LAST_VEC_0</doc> -<bitfield high="30" low="30" name="SIGNED_1" /> -<doc>See SIGNED_0</doc> -<bitfield high="31" low="31" name="NORMALIZE_1" /> -<doc>See NORMALIZE_0</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x2500" stride="0x0008"> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_LW" offset="0x0"> -<doc>For VS3.0 - To support more PVS instructions, increase the -address range - Programmable Vertex Shader Flow Control Lower Word -Addresses Register 0</doc> -<bitfield high="15" low="0" name="PVS_FC_ACT_ADRS_0"> -<use-enum ref="ENUM313" /> -</bitfield> -<doc>This field defines the last PVS instruction to execute prior -to the control flow redirection. JUMP - The last instruction -executed prior to the jump LOOP - The last instruction executed -prior to the loop (init loop counter/inc) JSR - The last -instruction executed prior to the jump to the subroutine. -(Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> -<bitfield high="31" low="16" name="PVS_FC_LOOP_CNT_JMP_INST_0"> -<use-enum ref="ENUM314" /> -</bitfield> -<doc>This field has multiple definitions as follows: JUMP - The -instruction address to jump to. LOOP - The loop count. *Note loop -count of 0 must be replaced by a jump. JSR - The instruction -address to jump to (first inst of subroutine). -(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x2504" stride="0x0008"> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_UW" offset="0x0"> -<doc>For VS3.0 - To support more PVS instructions, increase the -address range - Programmable Vertex Shader Flow Control Upper Word -Addresses Register 0</doc> -<bitfield high="15" low="0" name="PVS_FC_LAST_INST_0"> -<use-enum ref="ENUM313" /> -</bitfield> -<doc>This field has multiple definitions as follows: JUMP - Not -Applicable LOOP - The last instruction of the loop. JSR - The last -instruction of the subroutine. -(Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> -<bitfield high="31" low="16" name="PVS_FC_RTN_INST_0"> -<use-enum ref="ENUM314" /> -</bitfield> -<doc>This field has multiple definitions as follows: JUMP - Not -Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS + -1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1). -(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> -</reg32> -</stripe> -<stripe length="16" offset="0x2290" stride="0x0004"> -<reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" -offset="0x0"> -<doc>Programmable Vertex Shader Flow Control Loop Index Register -0</doc> -<bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" /> -<doc>This field stores the automatic loop index register init -value. This is an 8-bit unsigned value 0-255. This field is only -used if the corresponding control flow instruction is a loop.</doc> -<bitfield high="15" low="8" name="PVS_FC_LOOP_STEP_VAL_0" /> -<doc>This field stores the automatic loop index register step -value. This is an 8-bit 2`s comp signed value -128-127. This field -is only used if the corresponding control flow instruction is a -loop.</doc> -<bitfield high="31" low="31" name="PVS_FC_LOOP_REPEAT_NO_FLI_0" /> -<doc>When this field is set, the automatic loop index register init -value is not used at loop activation. The intial loop index is -inherited from outer loop. The loop index register step value is -used at the end of each loop iteration ; after loop completion, the -outer loop index register is restored</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_TEX_TO_COLOR_CNTL" offset="0x2218"> -<doc>For VS3.0 color2texture - flat shading on textures - -limitation: only first 8 vectors can have clipping with wrap -shortest or point sprite generated textures</doc> -</reg32> -<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084"> -<doc>Vertex Fetcher Control</doc> -<bitfield high="3" low="0" name="PRIM_TYPE" /> -<doc>Primitive Type 0 : None (will not trigger Setup Engine to run) -1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 : -Triangle Fan 6 : Triangle Strip 7 : Triangle with wFlags (aka, -Rage128 `Type-2` triangles) * 8-11 : Unused 12 : Line Loop 13 : -Quad List 14 : Quad Strip 15 : Polygon *Encoding 7 indicates -whether a 16-bit word of wFlags is present in the stream of indices -arriving when the VTX_AMODE is programmed as a `0`. The Setup -Engine just steps over the wFlags word; ignoring it. 0 = Stream -contains just indices, as: [ Index1, Index0] [ Index3, Index2] [ -Index5, Index4 ] etc... 1 = Stream contains indices and wFlags: [ -Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ wFlags, -Index5 ] etc...</doc> -<bitfield high="5" low="4" name="PRIM_WALK" /> -<doc>Method of Passing Vertex Data. 0 : State-Based Vertex Data. -(Vertex data and tokens embedded in command stream.) 1 = Indexes -(Indices embedded in command stream; vertex data to be fetched from -memory.) 2 = Vertex List (Vertex data to be fetched from memory.) 3 -= Vertex Data (Vertex data embedded in command stream.)</doc> -<bitfield high="10" low="6" name="RSVD_PREV_USED" /> -<doc>Reserved bits</doc> -<bitfield high="11" low="11" name="INDEX_SIZE" /> -<doc>When set, vertex indices are 32-bits/indx, otherwise, 16- -bits/indx.</doc> -<bitfield high="12" low="12" name="VTX_REUSE_DIS" /> -<doc>When set, vertex reuse is disabled. DO NOT SET unless -PRIM_WALK is Indexes.</doc> -<bitfield high="13" low="13" name="DUAL_INDEX_MODE" /> -<doc>When set, the incoming index is treated as two separate -indices. Bits 23-16 are used as the index for AOS 0 (These are 0 -for 16-bit indices) Bits 15-0 are used as the index for AOS 1-15. -This mode was added specifically for HOS usage</doc> -<bitfield high="14" low="14" name="USE_ALT_NUM_VERTS" /> -<doc>When set, the number of vertices in the command packet is -taken from VAP_ALT_NUM_VERTICES register instead of bits 31:16 of -VAP_VF_CNTL</doc> -<bitfield high="31" low="16" name="NUM_VERTICES" /> -<doc>Number of vertices in the command packet.</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0"> -<doc>Vertex Array of Structures Control</doc> -<bitfield high="4" low="0" name="VTX_NUM_ARRAYS" /> -<doc>The number of arrays required to represent the current vertex -type. Each Array is described by the following three fields: -VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> -<bitfield high="5" low="5" name="VC_FORCE_PREFETCH" /> -<doc>Force Vertex Data Pre-fetching. If this bit is set, then a -256-bit word will always be fetched, regardless of which dwords are -needed. Typically useful when VAP_VF_CNTL.PRIM_WALK is set to -Vertex List (Auto-incremented indices).</doc> -<bitfield high="6" low="6" name="VC_DIS_CACHE_INVLD" /> -<doc>If set, the vertex cache is not invalidated between draw -packets. This allows vertex cache hits to occur from packet to -packet. This must be set with caution with respect to multiple -contexts in the driver.</doc> -<bitfield high="16" low="16" name="AOS_0_FETCH_SIZE" /> -<doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule size 1 = -256-bit granule size This allows the driver to program the fetch -size based on DWORDS/VTX/AOS combined with AGP vs. LOC Memory. The -general belief is that the granule size should always be 256-bits -for LOC memory and AGP8X data, but should be 128-bit for AGP2X/4X -data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc> -<bitfield high="17" low="17" name="AOS_1_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="18" low="18" name="AOS_2_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="19" low="19" name="AOS_3_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="20" low="20" name="AOS_4_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="21" low="21" name="AOS_5_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="22" low="22" name="AOS_6_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="23" low="23" name="AOS_7_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="24" low="24" name="AOS_8_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="25" low="25" name="AOS_9_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="26" low="26" name="AOS_10_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="27" low="27" name="AOS_11_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="28" low="28" name="AOS_12_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="29" low="29" name="AOS_13_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -<bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" /> -<doc>See AOS_0_FETCH_SIZE</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180"> -<doc>VAP Vertex State Control Register</doc> -<bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="3" low="2" name="COLOR_1_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 1 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="5" low="4" name="COLOR_2_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 2 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="7" low="6" name="COLOR_3_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 3 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="9" low="8" name="COLOR_4_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 4 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="11" low="10" name="COLOR_5_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 5 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="13" low="12" name="COLOR_6_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 6 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="15" low="14" name="COLOR_7_ASSEMBLY_CNTL" /> -<doc>0 : Select Color 7 1 : Select User Color 0 2 : Select User -Color 1 3 : Reserved</doc> -<bitfield high="16" low="16" name="UPDATE_USER_COLOR_0_ENA" /> -<doc>0 : User Color 0 State is NOT updated when User Color 0 is -written. 1 : User Color 1 State IS updated when User Color 0 is -written.</doc> -<bitfield high="18" low="18" name="Reserved" /> -<doc>Set to 0</doc> -</reg32> -<stripe length="4" offset="0x2430" stride="0x0004"> -<reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x232C" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x2328" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x2324" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x2470" stride="0x0004"> -<reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x2320" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_EDGE_FLAGS" offset="0x245C"> -<doc>Data register</doc> -<bitfield high="0" low="0" name="DATA_REGISTER" /> -<doc>EDGE_FLAGS</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" offset="0x24AC"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" offset="0x2498"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" offset="0x2310"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" offset="0x2314"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" offset="0x2318"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" offset="0x2450"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" offset="0x2454"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" offset="0x2458"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_PNT_SPRT_SZ" offset="0x2420"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" offset="0x230C"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" offset="0x2490"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" offset="0x24A0"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" offset="0x2300"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" offset="0x2494"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" offset="0x24A4"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" offset="0x2304"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" offset="0x24A8"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" offset="0x2308"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" offset="0x2428"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" offset="0x242C"> -<doc>Data register</doc> -</reg32> -<stripe length="8" offset="0x23AC" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x23A8" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x23A0" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<stripe length="8" offset="0x23A4" stride="0x0010"> -<reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0"> -<doc>Data register</doc> -</reg32> -</stripe> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" offset="0x2468"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464"> -<doc>Data register</doc> -</reg32> -<reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" offset="0x249C"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460"> -<doc>Data register</doc> -</reg32> -<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C"> -<doc>Z Buffer Band-Width Control Defa</doc> -<bitfield high="0" low="0" name="HIZ_ENABLE"> -<use-enum ref="ENUM187" /> -</bitfield> -<doc>Enables hierarchical Z.</doc> -<bitfield high="1" low="1" name="HIZ_MIN"> -<use-enum ref="ENUM188" /> -</bitfield> -<doc /> -<bitfield high="2" low="2" name="FAST_FILL"> -<use-enum ref="ENUM189" /> -</bitfield> -<doc /> -<bitfield high="3" low="3" name="RD_COMP_ENABLE"> -<use-enum ref="ENUM190" /> -</bitfield> -<doc>Enables reading of compressed Z data from memory to the -cache.</doc> -<bitfield high="4" low="4" name="WR_COMP_ENABLE"> -<use-enum ref="ENUM191" /> -</bitfield> -<doc>Enables writing of compressed Z data from cache to -memory,</doc> -<bitfield high="5" low="5" name="ZB_CB_CLEAR"> -<use-enum ref="ENUM192" /> -</bitfield> -<doc>This bit is set when the Z buffer is used to help the CB in -clearing a region. Part of the region is cleared by the color -buffer and part will be cleared by the Z buffer. Since the Z buffer -does not have any write masks in the cache, full micro- tiles need -to be written. If a partial micro-tile is touched, then the -un-touched part will be unknowns. The cache will operate in -write-allocate mode and quads will be accumulated in the cache and -then evicted to main memory. The color value is supplied through -the ZB_DEPTHCLEARVALUE register.</doc> -<bitfield high="6" low="6" name="FORCE_COMPRESSED_STENCIL_V" /> -<doc>Enabling this bit will force all the compressed stencil -values</doc> -<bitfield high="7" low="7" name="ZEQUAL_OPTIMIZE_DISABLE"> -<value name="ENABLE_NOT_UPDATING_THE_Z_BUFFER_IF_NEWZ" value="0"> -<doc>Enable not updating the Z buffer if NewZ=OldZ</doc> -</value> -<value name="DISABLE_ABOVE_FEATURE" value="1"> -<doc>Disable above feature (in case there is a bug)</doc> -</value> -</bitfield> -<doc>By default this is 0 (enabled). When NEWZ=OLDZ, then writes do -not occur to save BW.</doc> -<bitfield high="8" low="8" name="SEQUAL_OPTIMIZE_DISABLE"> -<value name="ENABLE_NOT_UPDATING_THE_STENCIL_BUFFER_IF_NEWS" -value="0"> -<doc>Enable not updating the Stencil buffer if NewS=OldS</doc> -</value> -<value name="DISABLE_ABOVE_FEATURE" value="1"> -<doc>Disable above feature (in case there is a bug)</doc> -</value> -</bitfield> -<doc>By default this is 0 (enabled). When NEW_STENCIL=OLD_STENCIL, -then writes do not occur to save BW.</doc> -<bitfield high="10" low="10" name="BMASK_DISABLE"> -<value name="ENABLE_BYTEMASKING" value="0"> -<doc>Enable bytemasking</doc> -</value> -<value name="DISABLE_BYTEMASKING" value="1"> -<doc>Disable bytemasking</doc> -</value> -</bitfield> -<doc>Controls whether bytemasking is used or not.</doc> -<bitfield high="11" low="11" name="HIZ_EQUAL_REJECT_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables hiz rejects when the z function is equals.</doc> -<bitfield high="15" low="15" name="HIZ_FP_INVERT"> -<value name="COUNT_LEADING_1S" value="0"> -<doc>Count leading 1s</doc> -</value> -<value name="COUNT_LEADING_0S" value="1"> -<doc>Count leading 0s</doc> -</value> -</bitfield> -<doc>Determines whether leading zeros or ones are eliminated.</doc> -<bitfield high="16" low="16" name="TILE_OVERWRITE_RECOMPRESSI" /> -<doc>The zb tries to detect single plane equations that -completely</doc> -<bitfield high="17" low="17" name="CONTIGUOUS_6XAA_SAMPLES_DI" /> -<doc>This disables storing samples contiguously in 6xaa.</doc> -<bitfield high="18" low="18" name="PEQ_PACKING_ENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables packing of the plane equations to eliminate wasted peq -slots.</doc> -<bitfield high="19" low="19" name="COVERED_PTR_MASKING_ENABL" /> -<doc>Enables discarding of pointers from pixels that are going to -be</doc> -</reg32> -<reg32 access="rw" name="ZB_CNTL" offset="0x4F00"> -<doc>Z Buffer Control</doc> -<bitfield high="0" low="0" name="STENCIL_ENABLE"> -<use-enum ref="ENUM178" /> -</bitfield> -<doc>Enables stenciling.</doc> -<bitfield high="1" low="1" name="Z_ENABLE"> -<use-enum ref="ENUM178" /> -</bitfield> -<doc>Enables Z functions.</doc> -<bitfield high="2" low="2" name="ZWRITEENABLE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enables writing of the Z buffer.</doc> -<bitfield high="3" low="3" name="ZSIGNED_COMPARE"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Enable signed Z buffer comparison , for W-buffering.</doc> -<bitfield high="4" low="4" name="STENCIL_FRONT_BACK"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK bit to -one specifies that -stencilfunc/stencilfail/stencilzpass/stencilzfail registers are -used if the quad is generated from front faced primitive and -stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf are -used if the quad is generated from a back faced primitive. If the -STENCIL_FRONT_BACK is not set, then -stencilfunc/stencilfail/stencilzpass/stencilzfail registers -determine the operation independent of the front/back face state of -the quad.</doc> -<bitfield high="5" low="5" name="ZSIGNED_MAGNITUDE"> -<value name="TWOS_COMPLEMENT" value="0"> -<doc>Twos complement</doc> -</value> -<value name="SIGNED_MAGNITUDE" value="1"> -<doc>Signed magnitude</doc> -</value> -</bitfield> -<doc>Specifies the signed number type to use for the Z buffer -comparison. This only has an effect when ZSIGNED_COMPARE is -enabled.</doc> -<bitfield high="6" low="6" name="STENCIL_REFMASK_FRONT_BACK"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc /> -</reg32> -<reg32 access="rw" name="ZB_FIFO_SIZE" offset="0x4FD0"> -<doc>Sets the fifo sizes</doc> -<bitfield high="1" low="0" name="OP_FIFO_SIZE"> -<use-enum ref="ENUM216" /> -</bitfield> -<doc>Determines the size of the op fifo</doc> -</reg32> -<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10"> -<doc>Format of the Data in the Z buffer</doc> -<bitfield high="3" low="0" name="DEPTHFORMAT"> -<use-enum ref="ENUM196" /> -</bitfield> -<doc>Specifies the format of the Z buffer.</doc> -<bitfield high="4" low="4" name="INVERT"> -<value name="IN_13E3_FORMAT" value="0"> -<doc>in 13E3 format , count leading 1`s</doc> -</value> -<value name="IN_13E3_FORMAT" value="1"> -<doc>in 13E3 format , count leading 0`s.</doc> -</value> -</bitfield> -<doc /> -<bitfield high="5" low="5" name="PEQ8" /> -<doc>This bit is unused</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44"> -<doc>Hierarchical Z Memory Offset</doc> -<bitfield high="17" low="2" name="HIZ_OFFSET" /> -<doc>DWORD offset into HiZ RAM.</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50"> -<doc>Hierarchical Z Read Index</doc> -<bitfield high="17" low="2" name="HIZ_RDINDEX" /> -<doc>Read index into HiZ RAM.</doc> -</reg32> -<reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48"> -<doc>Hierarchical Z Write Index</doc> -<bitfield high="17" low="2" name="HIZ_WRINDEX" /> -<doc>Self-incrementing write index into the HiZ RAM. Starting write -index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is -written, this index will autoincrement. HIZ_OFFSET and HIZ_PITCH -are not used to compute read/write address to HIZ ram, when it is -accessed through WRINDEX and DWORD</doc> -</reg32> -<reg32 access="rw" name="ZB_STENCILREFMASK_BF" offset="0x4FD4"> -<doc>Stencil Reference Value and Mask for backfacing quads</doc> -<bitfield high="7" low="0" name="STENCILREF" /> -<doc>Specifies the reference stencil value.</doc> -<bitfield high="15" low="8" name="STENCILMASK" /> -<doc>This value is ANDed with both the reference and the current -stencil value prior to the stencil test.</doc> -<bitfield high="23" low="16" name="STENCILWRITEMASK" /> -<doc>Specifies the write mask for the stencil planes.</doc> -</reg32> -<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04"> -<doc>Z and Stencil Function Control</doc> -<bitfield high="2" low="0" name="ZFUNC"> -<use-enum ref="ENUM202" /> -</bitfield> -<doc>Specifies the Z function.</doc> -<bitfield high="5" low="3" name="STENCILFUNC"> -<use-enum ref="ENUM203" /> -</bitfield> -<doc>Specifies the stencil function.</doc> -<bitfield high="8" low="6" name="STENCILFAIL"> -<use-enum ref="ENUM204" /> -</bitfield> -<doc>Specifies the stencil value to be written if the stencil test -fails.</doc> -<bitfield high="11" low="9" name="STENCILZPASS" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test passes (or is -not enabled).</doc> -<bitfield high="14" low="12" name="STENCILZFAIL" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test fails.</doc> -<bitfield high="17" low="15" name="STENCILFUNC_BF" /> -<doc>Same encoding as STENCILFUNC. Specifies the stencil function -for back faced quads , if STENCIL_FRONT_BACK = 1.</doc> -<bitfield high="20" low="18" name="STENCILFAIL_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test fails for back faced quads, if -STENCIL_FRONT_BACK = 1</doc> -<bitfield high="23" low="21" name="STENCILZPASS_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test passes (or is -not enabled) for back faced quads, if STENCIL_FRONT_BACK = 1</doc> -<bitfield high="26" low="24" name="STENCILZFAIL_BF" /> -<doc>Same encoding as STENCILFAIL. Specifies the stencil value to -be written if the stencil test passes and the Z test fails for back -faced quads, if STENCIL_FRONT_BACK =1</doc> -<bitfield high="27" low="27" name="ZERO_OUTPUT_MASK"> -<use-enum ref="ENUM5" /> -</bitfield> -<doc>Zeroes the zb coverage mask output. This does not affect the -updating of the depth or stencil values.</doc> -</reg32> -</group> -<variant id="r300"> -<use-group ref="rX00_regs" /> -<use-group ref="r300_regs" /> -</variant> -<variant id="r500"> -<use-group ref="rX00_regs" /> -<use-group ref="r500_regs" /> -</variant> + <domain name="R300" /> + <enum name="ENUM0"> + <value name="NORMAL_OPERATION" value="0"> + <doc>Normal operation.</doc> + </value> + <value name="RESOLVE_OPERATION" value="1"> + <doc>Resolve operation.</doc> + </value> + </enum> + <enum name="ENUM1"> + <value name="1" value="0"> + <doc>1.0</doc> + </value> + <value name="2" value="1"> + <doc>2.2</doc> + </value> + </enum> + <enum name="ENUM2"> + <value name="ADD_AND_CLAMP" value="0"> + <doc>Add and Clamp</doc> + </value> + <value name="ADD_BUT_NO_CLAMP" value="1"> + <doc>Add but no Clamp</doc> + </value> + <value name="SUBTRACT_DST_FROM_SRC" value="2"> + <doc>Subtract Dst from Src, and Clamp</doc> + </value> + <value name="SUBTRACT_DST_FROM_SRC" value="3"> + <doc>Subtract Dst from Src, and don`t Clamp</doc> + </value> + <value name="MINIMUM_OF_SRC" value="4"> + <doc>Minimum of Src, Dst (the src and dst blend functions are + forced to D3D_ONE)</doc> + </value> + <value name="MAXIMUM_OF_SRC" value="5"> + <doc>Maximum of Src, Dst (the src and dst blend functions are + forced to D3D_ONE)</doc> + </value> + <value name="SUBTRACT_SRC_FROM_DST" value="6"> + <doc>Subtract Src from Dst, and Clamp</doc> + </value> + <value name="SUBTRACT_SRC_FROM_DST" value="7"> + <doc>Subtract Src from Dst, and don`t Clamp</doc> + </value> + </enum> + <enum name="ENUM3"> + <value name="D3D_ZERO" value="1"> + <doc>D3D_ZERO</doc> + </value> + <value name="D3D_ONE" value="2"> + <doc>D3D_ONE</doc> + </value> + <value name="D3D_SRCCOLOR" value="3"> + <doc>D3D_SRCCOLOR</doc> + </value> + <value name="D3D_INVSRCCOLOR" value="4"> + <doc>D3D_INVSRCCOLOR</doc> + </value> + <value name="D3D_SRCALPHA" value="5"> + <doc>D3D_SRCALPHA</doc> + </value> + <value name="D3D_INVSRCALPHA" value="6"> + <doc>D3D_INVSRCALPHA</doc> + </value> + <value name="D3D_DESTALPHA" value="7"> + <doc>D3D_DESTALPHA</doc> + </value> + <value name="D3D_INVDESTALPHA" value="8"> + <doc>D3D_INVDESTALPHA</doc> + </value> + <value name="D3D_DESTCOLOR" value="9"> + <doc>D3D_DESTCOLOR</doc> + </value> + <value name="D3D_INVDESTCOLOR" value="10"> + <doc>D3D_INVDESTCOLOR</doc> + </value> + <value name="D3D_SRCALPHASAT" value="11"> + <doc>D3D_SRCALPHASAT</doc> + </value> + <value name="D3D_BOTHSRCALPHA" value="12"> + <doc>D3D_BOTHSRCALPHA</doc> + </value> + <value name="D3D_BOTHINVSRCALPHA" value="13"> + <doc>D3D_BOTHINVSRCALPHA</doc> + </value> + <value name="GL_ZERO" value="32"> + <doc>GL_ZERO</doc> + </value> + <value name="GL_ONE" value="33"> + <doc>GL_ONE</doc> + </value> + <value name="GL_SRC_COLOR" value="34"> + <doc>GL_SRC_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_SRC_COLOR" value="35"> + <doc>GL_ONE_MINUS_SRC_COLOR</doc> + </value> + <value name="GL_DST_COLOR" value="36"> + <doc>GL_DST_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_DST_COLOR" value="37"> + <doc>GL_ONE_MINUS_DST_COLOR</doc> + </value> + <value name="GL_SRC_ALPHA" value="38"> + <doc>GL_SRC_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_SRC_ALPHA" value="39"> + <doc>GL_ONE_MINUS_SRC_ALPHA</doc> + </value> + <value name="GL_DST_ALPHA" value="40"> + <doc>GL_DST_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_DST_ALPHA" value="41"> + <doc>GL_ONE_MINUS_DST_ALPHA</doc> + </value> + <value name="GL_SRC_ALPHA_SATURATE" value="42"> + <doc>GL_SRC_ALPHA_SATURATE</doc> + </value> + <value name="GL_CONSTANT_COLOR" value="43"> + <doc>GL_CONSTANT_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_CONSTANT_COLOR" value="44"> + <doc>GL_ONE_MINUS_CONSTANT_COLOR</doc> + </value> + <value name="GL_CONSTANT_ALPHA" value="45"> + <doc>GL_CONSTANT_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_CONSTANT_ALPHA" value="46"> + <doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc> + </value> + </enum> + <enum name="ENUM4"> + <value name="D3D_ZERO" value="1"> + <doc>D3D_ZERO</doc> + </value> + <value name="D3D_ONE" value="2"> + <doc>D3D_ONE</doc> + </value> + <value name="D3D_SRCCOLOR" value="3"> + <doc>D3D_SRCCOLOR</doc> + </value> + <value name="D3D_INVSRCCOLOR" value="4"> + <doc>D3D_INVSRCCOLOR</doc> + </value> + <value name="D3D_SRCALPHA" value="5"> + <doc>D3D_SRCALPHA</doc> + </value> + <value name="D3D_INVSRCALPHA" value="6"> + <doc>D3D_INVSRCALPHA</doc> + </value> + <value name="D3D_DESTALPHA" value="7"> + <doc>D3D_DESTALPHA</doc> + </value> + <value name="D3D_INVDESTALPHA" value="8"> + <doc>D3D_INVDESTALPHA</doc> + </value> + <value name="D3D_DESTCOLOR" value="9"> + <doc>D3D_DESTCOLOR</doc> + </value> + <value name="D3D_INVDESTCOLOR" value="10"> + <doc>D3D_INVDESTCOLOR</doc> + </value> + <value name="GL_ZERO" value="32"> + <doc>GL_ZERO</doc> + </value> + <value name="GL_ONE" value="33"> + <doc>GL_ONE</doc> + </value> + <value name="GL_SRC_COLOR" value="34"> + <doc>GL_SRC_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_SRC_COLOR" value="35"> + <doc>GL_ONE_MINUS_SRC_COLOR</doc> + </value> + <value name="GL_DST_COLOR" value="36"> + <doc>GL_DST_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_DST_COLOR" value="37"> + <doc>GL_ONE_MINUS_DST_COLOR</doc> + </value> + <value name="GL_SRC_ALPHA" value="38"> + <doc>GL_SRC_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_SRC_ALPHA" value="39"> + <doc>GL_ONE_MINUS_SRC_ALPHA</doc> + </value> + <value name="GL_DST_ALPHA" value="40"> + <doc>GL_DST_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_DST_ALPHA" value="41"> + <doc>GL_ONE_MINUS_DST_ALPHA</doc> + </value> + <value name="GL_CONSTANT_COLOR" value="43"> + <doc>GL_CONSTANT_COLOR</doc> + </value> + <value name="GL_ONE_MINUS_CONSTANT_COLOR" value="44"> + <doc>GL_ONE_MINUS_CONSTANT_COLOR</doc> + </value> + <value name="GL_CONSTANT_ALPHA" value="45"> + <doc>GL_CONSTANT_ALPHA</doc> + </value> + <value name="GL_ONE_MINUS_CONSTANT_ALPHA" value="46"> + <doc>GL_ONE_MINUS_CONSTANT_ALPHA</doc> + </value> + </enum> + <enum name="ENUM5"> + <value name="DISABLE" value="0"> + <doc>Disable</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </enum> + <enum name="ENUM6"> + <value name="DISABLED" value="0"> + <doc>Disabled (Use RB3D_BLENDCNTL)</doc> + </value> + <value name="ENABLED" value="1"> + <doc>Enabled (Use RB3D_ABLENDCNTL)</doc> + </value> + </enum> + <enum name="ENUM7"> + <value name="DISABLE_READS" value="0"> + <doc>Disable reads</doc> + </value> + <value name="ENABLE_READS" value="1"> + <doc>Enable reads</doc> + </value> + </enum> + <enum name="ENUM9"> + <value name="1_BUFFER" value="0"> + <doc>1 buffer. This is the only mode where the cb processes + the end of packet command.</doc> + </value> + <value name="2_BUFFERS" value="1"> + <doc>2 buffers</doc> + </value> + <value name="3_BUFFERS" value="2"> + <doc>3 buffers</doc> + </value> + <value name="4_BUFFERS" value="3"> + <doc>4 buffers</doc> + </value> + </enum> + <enum name="ENUM10"> + <value name="DISABLE_COLOR_COMPARE" value="0"> + <doc>Disable color compare.</doc> + </value> + <value name="ENABLE_COLOR_COMPARE" value="1"> + <doc>Enable color compare.</doc> + </value> + </enum> + <enum name="ENUM11"> + <value name="DISABLE_AA_COMPRESSION" value="0"> + <doc>Disable AA compression</doc> + </value> + <value name="ENABLE_AA_COMPRESSION" value="1"> + <doc>Enable AA compression</doc> + </value> + </enum> + <enum name="ENUM12"> + <value name="3D_DESTINATION_IS_NOT_MACROTILED" value="0"> + <doc>3D destination is not macrotiled</doc> + </value> + <value name="3D_DESTINATION_IS_MACROTILED" value="1"> + <doc>3D destination is macrotiled</doc> + </value> + </enum> + <enum name="ENUM13"> + <value name="3D_DESTINATION_IS_NO_MICROTILED" value="0"> + <doc>3D destination is no microtiled</doc> + </value> + <value name="3D_DESTINATION_IS_MICROTILED" value="1"> + <doc>3D destination is microtiled</doc> + </value> + <value name="3D_DESTINATION_IS_SQUARE_MICROTILED" value="2"> + <doc>3D destination is square microtiled. Only available in + 16-bit</doc> + </value> + </enum> + <enum name="ENUM14"> + <value name="NO_SWAP" value="0"> + <doc>No swap</doc> + </value> + <value name="WORD_SWAP" value="1"> + <doc>Word swap (2 bytes in 16-bit)</doc> + </value> + <value name="DWORD_SWAP" value="2"> + <doc>Dword swap (4 bytes in a 32-bit)</doc> + </value> + <value name="HALF" value="3"> + <doc>Half-Dword swap (2 16-bit in a 32-bit)</doc> + </value> + </enum> + <enum name="ENUM16"> + <value name="DISABLE" value="0"> + <doc>disable</doc> + </value> + <value name="ENABLE" value="1"> + <doc>enable</doc> + </value> + </enum> + <enum name="ENUM17"> + <value name="TRUNCATE" value="0"> + <doc>Truncate</doc> + </value> + <value name="ROUND" value="1"> + <doc>Round</doc> + </value> + <value name="LUT_DITHER" value="2"> + <doc>LUT dither</doc> + </value> + </enum> + <enum name="ENUM22"> + <value name="AF_NEVER" value="0"> + <doc>AF_NEVER</doc> + </value> + <value name="AF_LESS" value="1"> + <doc>AF_LESS</doc> + </value> + <value name="AF_EQUAL" value="2"> + <doc>AF_EQUAL</doc> + </value> + <value name="AF_LE" value="3"> + <doc>AF_LE</doc> + </value> + <value name="AF_GREATER" value="4"> + <doc>AF_GREATER</doc> + </value> + <value name="AF_NOTEQUAL" value="5"> + <doc>AF_NOTEQUAL</doc> + </value> + <value name="AF_GE" value="6"> + <doc>AF_GE</doc> + </value> + <value name="AF_ALWAYS" value="7"> + <doc>AF_ALWAYS</doc> + </value> + </enum> + <enum name="ENUM23"> + <value name="DISABLE_ALPHA_FUNCTION" value="0"> + <doc>Disable alpha function.</doc> + </value> + <value name="ENABLE_ALPHA_FUNCTION" value="1"> + <doc>Enable alpha function.</doc> + </value> + </enum> + <enum name="ENUM24"> + <value name="DISABLE_ALPHA_TO_MASK_FUNCTION" value="0"> + <doc>Disable alpha to mask function.</doc> + </value> + <value name="ENABLE_ALPHA_TO_MASK_FUNCTION" value="1"> + <doc>Enable alpha to mask function.</doc> + </value> + </enum> + <enum name="ENUM25"> + <value name="2" value="0"> + <doc>2/4 sub-pixel samples.</doc> + </value> + <value name="3" value="1"> + <doc>3/6 sub-pixel samples.</doc> + </value> + </enum> + <enum name="ENUM26"> + <value name="DISABLE_DITHERING" value="0"> + <doc>Disable Dithering</doc> + </value> + <value name="ENABLE_DITHERING" value="1"> + <doc>Enable Dithering.</doc> + </value> + </enum> + <enum name="ENUM30"> + <value name="SOLID_FILL_COLOR" value="0"> + <doc>Solid fill color</doc> + </value> + <value name="FLAT_SHADING" value="1"> + <doc>Flat shading</doc> + </value> + <value name="GOURAUD_SHADING" value="2"> + <doc>Gouraud shading</doc> + </value> + </enum> + <enum name="ENUM32"> + <value name="NO_EFFECT" value="0"> + <doc>No effect.</doc> + </value> + <value name="PREVENTS_TCL_INTERFACE_FROM_DEADLOCKING_ON_GA_SIDE" + value="1"> + <doc>Prevents TCL interface from deadlocking on GA + side.</doc> + </value> + </enum> + <enum name="ENUM33"> + <value name="NO_EFFECT" value="0"> + <doc>No effect.</doc> + </value> + <value name="ENABLES_HIGH" value="1"> + <doc>Enables high-performance register/primitive + switching.</doc> + </value> + </enum> + <enum name="ENUM34"> + <value name="HORIZONTAL" value="0"> + <doc>Horizontal</doc> + </value> + <value name="VERTICAL" value="1"> + <doc>Vertical</doc> + </value> + <value name="SQUARE" value="2"> + <doc>Square (horizontal or vertical depending upon + slope)</doc> + </value> + <value name="COMPUTED" value="3"> + <doc>Computed (perpendicular to slope)</doc> + </value> + </enum> + <enum name="ENUM37"> + <value name="DRAW_POINTS" value="0"> + <doc>Draw points.</doc> + </value> + <value name="DRAW_LINES" value="1"> + <doc>Draw lines.</doc> + </value> + <value name="DRAW_TRIANGLES" value="2"> + <doc>Draw triangles.</doc> + </value> + <value name="7" value="3"> + <doc>7.</doc> + </value> + </enum> + <enum name="ENUM38"> + <value name="ROUND_TO_TRUNC" value="0"> + <doc>Round to trunc</doc> + </value> + <value name="ROUND_TO_NEAREST" value="1"> + <doc>Round to nearest</doc> + </value> + </enum> + <enum name="ENUM43"> + <value name="DISABLE_POINT_TEXTURE_STUFFING" value="0"> + <doc>Disable point texture stuffing.</doc> + </value> + <value name="ENABLE_POINT_TEXTURE_STUFFING" value="1"> + <doc>Enable point texture stuffing.</doc> + </value> + </enum> + <enum name="ENUM44"> + <value name="DISABLE_LINE_TEXTURE_STUFFING" value="0"> + <doc>Disable line texture stuffing.</doc> + </value> + <value name="ENABLE_LINE_TEXTURE_STUFFING" value="1"> + <doc>Enable line texture stuffing.</doc> + </value> + </enum> + <enum name="ENUM45"> + <value name="DISABLE_TRIANGLE_TEXTURE_STUFFING" value="0"> + <doc>Disable triangle texture stuffing.</doc> + </value> + <value name="ENABLE_TRIANGLE_TEXTURE_STUFFING" value="1"> + <doc>Enable triangle texture stuffing.</doc> + </value> + </enum> + <enum name="ENUM46"> + <value name="DISABLE_STENCIL_AUTO_INC" value="0"> + <doc>Disable stencil auto inc/dec (def).</doc> + </value> + <value name="ENABLE_STENCIL_AUTO_INC" value="1"> + <doc>Enable stencil auto inc/dec based on triangle cw/ccw, + force into dzy low bit.</doc> + </value> + <value name="FORCE_0_INTO_DZY_LOW_BIT" value="2"> + <doc>Force 0 into dzy low bit.</doc> + </value> + </enum> + <enum name="ENUM55"> + <value name="32_WORDS" value="0"> + <doc>32 words</doc> + </value> + <value name="64_WORDS" value="1"> + <doc>64 words</doc> + </value> + <value name="128_WORDS" value="2"> + <doc>128 words</doc> + </value> + <value name="256_WORDS" value="3"> + <doc>256 words</doc> + </value> + </enum> + <enum name="ENUM56"> + <value name="16_WORDS" value="0"> + <doc>16 words</doc> + </value> + <value name="32_WORDS" value="1"> + <doc>32 words</doc> + </value> + <value name="64_WORDS" value="2"> + <doc>64 words</doc> + </value> + <value name="128_WORDS" value="3"> + <doc>128 words</doc> + </value> + </enum> + <enum name="ENUM57"> + <value name="64_WORDS" value="0"> + <doc>64 words</doc> + </value> + <value name="128_WORDS" value="1"> + <doc>128 words</doc> + </value> + <value name="256_WORDS" value="2"> + <doc>256 words</doc> + </value> + <value name="512_WORDS" value="3"> + <doc>512 words</doc> + </value> + </enum> + <enum name="ENUM58"> + <value name="0_WORDS" value="0"> + <doc>0 words</doc> + </value> + <value name="4_WORDS" value="1"> + <doc>4 words</doc> + </value> + <value name="8_WORDS" value="2"> + <doc>8 words</doc> + </value> + <value name="12_WORDS" value="3"> + <doc>12 words</doc> + </value> + </enum> + <enum name="ENUM59"> + <value name="SELECT_C0A" value="0"> + <doc>Select C0A</doc> + </value> + <value name="SELECT_C1A" value="1"> + <doc>Select C1A</doc> + </value> + <value name="SELECT_C2A" value="2"> + <doc>Select C2A</doc> + </value> + <value name="SELECT_C3A" value="3"> + <doc>Select C3A</doc> + </value> + <value name="SELECT_1" value="4"> + <doc>Select 1/(1/W)</doc> + </value> + <value name="SELECT_Z" value="5"> + <doc>Select Z</doc> + </value> + </enum> + <enum name="ENUM60"> + <value name="SELECT_Z" value="0"> + <doc>Select Z</doc> + </value> + <value name="SELECT_1" value="1"> + <doc>Select 1/(1/W)</doc> + </value> + </enum> + <enum name="ENUM61"> + <value name="SELECT" value="0"> + <doc>Select (1/W)</doc> + </value> + <value name="SELECT_1" value="1"> + <doc>Select 1.0</doc> + </value> + </enum> + <enum name="ENUM62"> + <value name="TILING_DISABLED" value="0"> + <doc>Tiling disabled.</doc> + </value> + <value name="TILING_ENABLED" value="1"> + <doc>Tiling enabled (def).</doc> + </value> + </enum> + <enum name="ENUM65"> + <value name="1X1_TILE" value="0"> + <doc>1x1 tile (one 1x1).</doc> + </value> + <value name="2_TILES" value="1"> + <doc>2 tiles (two 1x1 : ST-A,B).</doc> + </value> + <value name="4_TILES" value="2"> + <doc>4 tiles (one 2x2).</doc> + </value> + <value name="8_TILES" value="3"> + <doc>8 tiles (two 2x2 : ST-A,B).</doc> + </value> + <value name="16_TILES" value="4"> + <doc>16 tiles (one 4x4).</doc> + </value> + <value name="32_TILES" value="5"> + <doc>32 tiles (two 4x4 : ST-A,B).</doc> + </value> + <value name="64_TILES" value="6"> + <doc>64 tiles (one 8x8).</doc> + </value> + <value name="128_TILES" value="7"> + <doc>128 tiles (two 8x8 : ST-A,B).</doc> + </value> + </enum> + <enum name="ENUM66"> + <value name="ST" value="0"> + <doc>ST-A tile.</doc> + </value> + <value name="ST" value="1"> + <doc>ST-B tile.</doc> + </value> + </enum> + <enum name="ENUM67"> + <value name="SELECT_1" value="0"> + <doc>Select 1/12 subpixel precision.</doc> + </value> + <value name="SELECT_1" value="1"> + <doc>Select 1/16 subpixel precision.</doc> + </value> + </enum> + <enum name="ENUM68"> + <value name="NO_WRITE" value="0"> + <doc>No write - texture coordinate not valid</doc> + </value> + <value name="WRITE" value="1"> + <doc>write - texture valid</doc> + </value> + </enum> + <enum name="ENUM70"> + <value name="SAMPLE_TEXTURE_COORDINATES_AT_REAL_PIXEL_CENTERS" + value="0"> + <doc>Sample texture coordinates at real pixel centers</doc> + </value> + <value name="SAMPLE_TEXTURE_COORDINATES_AT_ADJUSTED_PIXEL_CENTERS" + value="1"> + <doc>Sample texture coordinates at adjusted pixel + centers</doc> + </value> + </enum> + <enum name="ENUM72"> + <value name="FOUR_COMPONENTS" value="0"> + <doc>Four components (R,G,B,A)</doc> + </value> + <value name="THREE_COMPONENTS" value="1"> + <doc>Three components (R,G,B,0)</doc> + </value> + <value name="THREE_COMPONENTS" value="2"> + <doc>Three components (R,G,B,1)</doc> + </value> + <value name="ONE_COMPONENT" value="4"> + <doc>One component (0,0,0,A)</doc> + </value> + <value name="ZERO_COMPONENTS" value="5"> + <doc>Zero components (0,0,0,0)</doc> + </value> + <value name="ZERO_COMPONENTS" value="6"> + <doc>Zero components (0,0,0,1)</doc> + </value> + <value name="ONE_COMPONENT" value="8"> + <doc>One component (1,1,1,A)</doc> + </value> + <value name="ZERO_COMPONENTS" value="9"> + <doc>Zero components (1,1,1,0)</doc> + </value> + <value name="ZERO_COMPONENTS" value="10"> + <doc>Zero components (1,1,1,1)</doc> + </value> + </enum> + <enum name="ENUM73"> + <value name="C" value="0"> + <doc>C</doc> + </value> + <value name="1ST_TEXTURE_COMPONENT" value="0"> + <doc>1st texture component</doc> + </value> + <value name="C" value="1"> + <doc>C</doc> + </value> + <value name="2ND_TEXTURE_COMPONENT" value="1"> + <doc>2nd texture component</doc> + </value> + <value name="C" value="2"> + <doc>C</doc> + </value> + <value name="3RD_TEXTURE_COMPONENT" value="2"> + <doc>3rd texture component</doc> + </value> + <value name="C" value="3"> + <doc>C</doc> + </value> + <value name="4TH_TEXTURE_COMPONENT" value="3"> + <doc>4th texture component</doc> + </value> + <value name="K" value="4"> + <doc>K</doc> + </value> + <value name="THE_VALUE_0" value="0"> + <doc>The value 0.0</doc> + </value> + <value name="K" value="5"> + <doc>K</doc> + </value> + <value name="THE_VALUE_1" value="1"> + <doc>The value 1.0</doc> + </value> + </enum> + <enum name="ENUM74"> + <value name="L" value="0"> + <doc>L-in,R-in,HT-in,HB-in</doc> + </value> + <value name="L" value="1"> + <doc>L-in,R-in,HT-in,HB-out</doc> + </value> + <value name="L" value="2"> + <doc>L-in,R-in,HT-out,HB-in</doc> + </value> + <value name="L" value="3"> + <doc>L-in,R-in,HT-out,HB-out</doc> + </value> + <value name="L" value="4"> + <doc>L-in,R-out,HT-in,HB-in</doc> + </value> + <value name="L" value="5"> + <doc>L-in,R-out,HT-in,HB-out</doc> + </value> + <value name="L" value="6"> + <doc>L-in,R-out,HT-out,HB-in</doc> + </value> + <value name="L" value="7"> + <doc>L-in,R-out,HT-out,HB-out</doc> + </value> + <value name="L" value="8"> + <doc>L-out,R-in,HT-in,HB-in</doc> + </value> + <value name="L" value="9"> + <doc>L-out,R-in,HT-in,HB-out</doc> + </value> + <value name="L" value="10"> + <doc>L-out,R-in,HT-out,HB-in</doc> + </value> + <value name="L" value="11"> + <doc>L-out,R-in,HT-out,HB-out</doc> + </value> + <value name="L" value="12"> + <doc>L-out,R-out,HT-in,HB-in</doc> + </value> + <value name="L" value="13"> + <doc>L-out,R-out,HT-in,HB-out</doc> + </value> + <value name="L" value="14"> + <doc>L-out,R-out,HT-out,HB-in</doc> + </value> + <value name="L" value="15"> + <doc>L-out,R-out,HT-out,HB-out</doc> + </value> + <value name="T" value="16"> + <doc>T-in,B-in,VL-in,VR-in</doc> + </value> + <value name="T" value="17"> + <doc>T-in,B-in,VL-in,VR-out</doc> + </value> + <value name="T" value="18"> + <doc>T-in,B-in,VL,VR-in</doc> + </value> + <value name="T" value="19"> + <doc>T-in,B-in,VL-out,VR-out</doc> + </value> + <value name="T" value="20"> + <doc>T-out,B-in,VL-in,VR-in</doc> + </value> + <value name="T" value="21"> + <doc>T-out,B-in,VL-in,VR-out</doc> + </value> + <value name="T" value="22"> + <doc>T-out,B-in,VL-out,VR-in</doc> + </value> + <value name="T" value="23"> + <doc>T-out,B-in,VL-out,VR-out</doc> + </value> + <value name="T" value="24"> + <doc>T-in,B-out,VL-in,VR-in</doc> + </value> + <value name="T" value="25"> + <doc>T-in,B-out,VL-in,VR-out</doc> + </value> + <value name="T" value="26"> + <doc>T-in,B-out,VL-out,VR-in</doc> + </value> + <value name="T" value="27"> + <doc>T-in,B-out,VL-out,VR-out</doc> + </value> + <value name="T" value="28"> + <doc>T-out,B-out,VL-in,VR-in</doc> + </value> + <value name="T" value="29"> + <doc>T-out,B-out,VL-in,VR-out</doc> + </value> + <value name="T" value="30"> + <doc>T-out,B-out,VL-out,VR-in</doc> + </value> + <value name="T" value="31"> + <doc>T-out,B-out,VL-out,VR-out</doc> + </value> + </enum> + <enum name="ENUM75"> + <value name="L" value="0"> + <doc>L-in,R-in,HT-in,HB-in</doc> + </value> + <value name="L" value="1"> + <doc>L-in,R-in,HT-in,HB-out</doc> + </value> + <value name="L" value="2"> + <doc>L-in,R-in,HT-out,HB-in</doc> + </value> + <value name="L" value="3"> + <doc>L-in,R-in,HT-out,HB-out</doc> + </value> + <value name="L" value="4"> + <doc>L-in,R-out,HT-in,HB-in</doc> + </value> + <value name="L" value="5"> + <doc>L-in,R-out,HT-in,HB-out</doc> + </value> + <value name="L" value="6"> + <doc>L-in,R-out,HT-out,HB-in</doc> + </value> + <value name="L" value="7"> + <doc>L-in,R-out,HT-out,HB-out</doc> + </value> + <value name="L" value="8"> + <doc>L-out,R-in,HT-in,HB-in</doc> + </value> + <value name="L" value="9"> + <doc>L-out,R-in,HT-in,HB-out</doc> + </value> + <value name="L" value="10"> + <doc>L-out,R-in,HT-out,HB-in</doc> + </value> + <value name="L" value="11"> + <doc>L-out,R-in,HT-out,HB-out</doc> + </value> + <value name="L" value="12"> + <doc>L-out,R-out,HT-in,HB-in</doc> + </value> + <value name="L" value="13"> + <doc>L-out,R-out,HT-in,HB-out</doc> + </value> + <value name="L" value="14"> + <doc>L-out,R-out,HT-out,HB-in</doc> + </value> + <value name="L" value="15"> + <doc>L-out,R-out,HT-out,HB-out</doc> + </value> + <value name="T" value="16"> + <doc>T-in,B-in,VL-in,VR-in</doc> + </value> + <value name="T" value="17"> + <doc>T-in,B-in,VL-in,VR-out</doc> + </value> + <value name="T" value="18"> + <doc>T-in,B-in,VL,VR-in</doc> + </value> + <value name="T" value="19"> + <doc>T-in,B-in,VL-out,VR-out</doc> + </value> + <value name="T" value="20"> + <doc>T-in,B-out,VL-in,VR-in</doc> + </value> + <value name="T" value="21"> + <doc>T-in,B-out,VL-in,VR-out</doc> + </value> + <value name="T" value="22"> + <doc>T-in,B-out,VL-out,VR-in</doc> + </value> + <value name="T" value="23"> + <doc>T-in,B-out,VL-out,VR-out</doc> + </value> + <value name="T" value="24"> + <doc>T-out,B-in,VL-in,VR-in</doc> + </value> + <value name="T" value="25"> + <doc>T-out,B-in,VL-in,VR-out</doc> + </value> + <value name="T" value="26"> + <doc>T-out,B-in,VL-out,VR-in</doc> + </value> + <value name="T" value="27"> + <doc>T-out,B-in,VL-out,VR-out</doc> + </value> + <value name="T" value="28"> + <doc>T-out,B-out,VL-in,VR-in</doc> + </value> + <value name="T" value="29"> + <doc>T-out,B-out,VL-in,VR-out</doc> + </value> + <value name="T" value="30"> + <doc>T-out,B-out,VL-out,VR-in</doc> + </value> + <value name="T" value="31"> + <doc>T-out,B-out,VL-out,VR-out</doc> + </value> + </enum> + <enum name="ENUM136"> + <value name="WRAP" value="0"> + <doc>Wrap (repeat)</doc> + </value> + <value name="MIRROR" value="1"> + <doc>Mirror</doc> + </value> + <value name="CLAMP_TO_LAST_TEXEL" value="2"> + <doc>Clamp to last texel (0.0 to 1.0)</doc> + </value> + <value name="MIRRORONCE_TO_LAST_TEXEL" value="3"> + <doc>MirrorOnce to last texel (-1.0 to 1.0)</doc> + </value> + <value name="CLAMP_HALF_WAY_TO_BORDER_COLOR" value="4"> + <doc>Clamp half way to border color (0.0 to 1.0)</doc> + </value> + <value name="MIRRORONCE_HALF_WAY_TO_BORDER_COLOR" value="5"> + <doc>MirrorOnce half way to border color (-1.0 to 1.0)</doc> + </value> + <value name="CLAMP_TO_BORDER_COLOR" value="6"> + <doc>Clamp to border color (0.0 to 1.0)</doc> + </value> + <value name="MIRRORONCE_TO_BORDER_COLOR" value="7"> + <doc>MirrorOnce to border color (-1.0 to 1.0)</doc> + </value> + </enum> + <enum name="ENUM137"> + <value name="POINT" value="1"> + <doc>Point</doc> + </value> + <value name="LINEAR" value="2"> + <doc>Linear</doc> + </value> + </enum> + <enum name="ENUM138"> + <value name="NONE" value="0"> + <doc>None</doc> + </value> + <value name="POINT" value="1"> + <doc>Point</doc> + </value> + <value name="LINEAR" value="2"> + <doc>Linear</doc> + </value> + </enum> + <enum name="ENUM139"> + <value name="NONE" value="0"> + <doc>None (no filter specifed, select from MIN/MAG + filters)</doc> + </value> + <value name="POINT" value="1"> + <doc>Point</doc> + </value> + <value name="LINEAR" value="2"> + <doc>Linear</doc> + </value> + </enum> + <enum name="ENUM140"> + <value name="DISABLE" value="0"> + <doc>Disable</doc> + </value> + <value name="CHROMAKEY" value="1"> + <doc>ChromaKey (kill pixel if any sample matches chroma + key)</doc> + </value> + <value name="CHROMAKEYBLEND" value="2"> + <doc>ChromaKeyBlend (set sample to 0 if it matches chroma + key)</doc> + </value> + </enum> + <enum name="ENUM141"> + <value name="NORMAL_ROUNDING_ON_ALL_COMPONENTS" value="0"> + <doc>Normal rounding on all components (+0.5)</doc> + </value> + <value name="MPEG4_ROUNDING_ON_ALL_COMPONENTS" value="1"> + <doc>MPEG4 rounding on all components (+0.25)</doc> + </value> + </enum> + <enum name="ENUM142"> + <value name="DONT_TRUNCATE_COORDINATE_FRACTIONS" value="0"> + <doc>Dont truncate coordinate fractions.</doc> + </value> + <value name="TRUNCATE_COORDINATE_FRACTIONS_TO_0" value="1"> + <doc>Truncate coordinate fractions to 0.0 and 0.5 for + MPEG</doc> + </value> + </enum> + <enum name="ENUM143"> + <value name="NON" value="0"> + <doc>Non-Projected</doc> + </value> + <value name="PROJECTED" value="1"> + <doc>Projected</doc> + </value> + </enum> + <enum name="ENUM144"> + <value name="USE_TXWIDTH_FOR_IMAGE_ADDRESSING" value="0"> + <doc>Use TXWIDTH for image addressing</doc> + </value> + <value name="USE_TXPITCH_FOR_IMAGE_ADDRESSING" value="1"> + <doc>Use TXPITCH for image addressing</doc> + </value> + </enum> + <enum name="ENUM154"> + <value name="DISABLE_GAMMA_REMOVAL" value="0"> + <doc>Disable gamma removal</doc> + </value> + <value name="ENABLE_GAMMA_REMOVAL" value="1"> + <doc>Enable gamma removal</doc> + </value> + </enum> + <enum name="ENUM155"> + <value name="DISABLE_YUV_TO_RGB_CONVERSION" value="0"> + <doc>Disable YUV to RGB conversion</doc> + </value> + <value name="ENABLE_YUV_TO_RGB_CONVERSION" value="1"> + <doc>Enable YUV to RGB conversion (with clamp)</doc> + </value> + <value name="ENABLE_YUV_TO_RGB_CONVERSION" value="2"> + <doc>Enable YUV to RGB conversion (without clamp)</doc> + </value> + </enum> + <enum name="ENUM156"> + <value name="DISABLE_SWAP_YUV_MODE" value="0"> + <doc>Disable swap YUV mode</doc> + </value> + <value name="ENABLE_SWAP_YUV_MODE" value="1"> + <doc>Enable swap YUV mode (hw inverts upper bit of U and + V)</doc> + </value> + </enum> + <enum name="ENUM157"> + <value name="2D" value="0"> + <doc>2D</doc> + </value> + <value name="3D" value="1"> + <doc>3D</doc> + </value> + <value name="CUBE" value="2"> + <doc>Cube</doc> + </value> + </enum> + <enum name="ENUM158"> + <value name="WHOLE" value="0"> + <doc>WHOLE</doc> + </value> + <value name="HALF_REGION_0" value="2"> + <doc>HALF_REGION_0</doc> + </value> + <value name="HALF_REGION_1" value="3"> + <doc>HALF_REGION_1</doc> + </value> + <value name="FOURTH_REGION_0" value="4"> + <doc>FOURTH_REGION_0</doc> + </value> + <value name="FOURTH_REGION_1" value="5"> + <doc>FOURTH_REGION_1</doc> + </value> + <value name="FOURTH_REGION_2" value="6"> + <doc>FOURTH_REGION_2</doc> + </value> + <value name="FOURTH_REGION_3" value="7"> + <doc>FOURTH_REGION_3</doc> + </value> + <value name="EIGHTH_REGION_0" value="8"> + <doc>EIGHTH_REGION_0</doc> + </value> + <value name="EIGHTH_REGION_1" value="9"> + <doc>EIGHTH_REGION_1</doc> + </value> + <value name="EIGHTH_REGION_2" value="10"> + <doc>EIGHTH_REGION_2</doc> + </value> + <value name="EIGHTH_REGION_3" value="11"> + <doc>EIGHTH_REGION_3</doc> + </value> + <value name="EIGHTH_REGION_4" value="12"> + <doc>EIGHTH_REGION_4</doc> + </value> + <value name="EIGHTH_REGION_5" value="13"> + <doc>EIGHTH_REGION_5</doc> + </value> + <value name="EIGHTH_REGION_6" value="14"> + <doc>EIGHTH_REGION_6</doc> + </value> + <value name="EIGHTH_REGION_7" value="15"> + <doc>EIGHTH_REGION_7</doc> + </value> + <value name="SIXTEENTH_REGION_0" value="16"> + <doc>SIXTEENTH_REGION_0</doc> + </value> + <value name="SIXTEENTH_REGION_1" value="17"> + <doc>SIXTEENTH_REGION_1</doc> + </value> + <value name="SIXTEENTH_REGION_2" value="18"> + <doc>SIXTEENTH_REGION_2</doc> + </value> + <value name="SIXTEENTH_REGION_3" value="19"> + <doc>SIXTEENTH_REGION_3</doc> + </value> + <value name="SIXTEENTH_REGION_4" value="20"> + <doc>SIXTEENTH_REGION_4</doc> + </value> + <value name="SIXTEENTH_REGION_5" value="21"> + <doc>SIXTEENTH_REGION_5</doc> + </value> + <value name="SIXTEENTH_REGION_6" value="22"> + <doc>SIXTEENTH_REGION_6</doc> + </value> + <value name="SIXTEENTH_REGION_7" value="23"> + <doc>SIXTEENTH_REGION_7</doc> + </value> + <value name="SIXTEENTH_REGION_8" value="24"> + <doc>SIXTEENTH_REGION_8</doc> + </value> + <value name="SIXTEENTH_REGION_9" value="25"> + <doc>SIXTEENTH_REGION_9</doc> + </value> + <value name="SIXTEENTH_REGION_A" value="26"> + <doc>SIXTEENTH_REGION_A</doc> + </value> + <value name="SIXTEENTH_REGION_B" value="27"> + <doc>SIXTEENTH_REGION_B</doc> + </value> + <value name="SIXTEENTH_REGION_C" value="28"> + <doc>SIXTEENTH_REGION_C</doc> + </value> + <value name="SIXTEENTH_REGION_D" value="29"> + <doc>SIXTEENTH_REGION_D</doc> + </value> + <value name="SIXTEENTH_REGION_E" value="30"> + <doc>SIXTEENTH_REGION_E</doc> + </value> + <value name="SIXTEENTH_REGION_F" value="31"> + <doc>SIXTEENTH_REGION_F</doc> + </value> + </enum> + <enum name="ENUM159"> + <value name="NO_SWAP" value="0"> + <doc>No swap</doc> + </value> + <value name="16_BIT_SWAP" value="1"> + <doc>16 bit swap</doc> + </value> + <value name="32_BIT_SWAP" value="2"> + <doc>32 bit swap</doc> + </value> + <value name="HALF" value="3"> + <doc>Half-DWORD swap</doc> + </value> + </enum> + <enum name="ENUM160"> + <value name="2KB_PAGE_IS_LINEAR" value="0"> + <doc>2KB page is linear</doc> + </value> + <value name="2KB_PAGE_IS_TILED" value="1"> + <doc>2KB page is tiled</doc> + </value> + </enum> + <enum name="ENUM161"> + <value name="32_BYTE_CACHE_LINE_IS_LINEAR" value="0"> + <doc>32 byte cache line is linear</doc> + </value> + <value name="32_BYTE_CACHE_LINE_IS_TILED" value="1"> + <doc>32 byte cache line is tiled</doc> + </value> + <value name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE" value="2"> + <doc>32 byte cache line is tiled square (only applies to + 16-bit texel)</doc> + </value> + </enum> + <enum name="ENUM164"> + <value name="A" value="0"> + <doc>A: Output to render target A</doc> + </value> + <value name="B" value="1"> + <doc>B: Output to render target B</doc> + </value> + <value name="C" value="2"> + <doc>C: Output to render target C</doc> + </value> + <value name="D" value="3"> + <doc>D: Output to render target D</doc> + </value> + </enum> + <enum name="ENUM166"> + <value name="SRC0" value="0"> + <doc>src0.r</doc> + </value> + <value name="SRC0" value="1"> + <doc>src0.g</doc> + </value> + <value name="SRC0" value="2"> + <doc>src0.b</doc> + </value> + <value name="SRC1" value="3"> + <doc>src1.r</doc> + </value> + <value name="SRC1" value="4"> + <doc>src1.g</doc> + </value> + <value name="SRC1" value="5"> + <doc>src1.b</doc> + </value> + <value name="SRC2" value="6"> + <doc>src2.r</doc> + </value> + <value name="SRC2" value="7"> + <doc>src2.g</doc> + </value> + <value name="SRC2" value="8"> + <doc>src2.b</doc> + </value> + <value name="SRC0" value="9"> + <doc>src0.a</doc> + </value> + <value name="SRC1" value="10"> + <doc>src1.a</doc> + </value> + <value name="SRC2" value="11"> + <doc>src2.a</doc> + </value> + <value name="SRCP" value="12"> + <doc>srcp.r</doc> + </value> + <value name="SRCP" value="13"> + <doc>srcp.g</doc> + </value> + <value name="SRCP" value="14"> + <doc>srcp.b</doc> + </value> + <value name="SRCP" value="15"> + <doc>srcp.a</doc> + </value> + <value name="0" value="16"> + <doc>0.0</doc> + </value> + <value name="1" value="17"> + <doc>1.0</doc> + </value> + <value name="0" value="18"> + <doc>0.5</doc> + </value> + </enum> + <enum name="ENUM167"> + <value name="NOP" value="0"> + <doc>NOP: Do not modify input</doc> + </value> + <value name="NEG" value="1"> + <doc>NEG: Negate input</doc> + </value> + <value name="ABS" value="2"> + <doc>ABS: Take absolute value of input</doc> + </value> + <value name="NAB" value="3"> + <doc>NAB: Take negative absolute value of input</doc> + </value> + </enum> + <enum name="ENUM168"> + <value name="1" value="0"> + <doc>1.0-2.0*A0</doc> + </value> + <value name="A1" value="1"> + <doc>A1-A0</doc> + </value> + <value name="A1" value="2"> + <doc>A1+A0</doc> + </value> + <value name="1" value="3"> + <doc>1.0-A0</doc> + </value> + </enum> + <enum name="ENUM170"> + <value name="RESULT" value="0"> + <doc>Result</doc> + </value> + <value name="RESULT" value="1"> + <doc>Result *2</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result *4</doc> + </value> + <value name="RESULT" value="3"> + <doc>Result *8</doc> + </value> + <value name="RESULT" value="4"> + <doc>Result / 2</doc> + </value> + <value name="RESULT" value="5"> + <doc>Result / 4</doc> + </value> + <value name="RESULT" value="6"> + <doc>Result / 8</doc> + </value> + </enum> + <enum name="ENUM171"> + <value name="DO_NOT_CLAMP_OUTPUT" value="0"> + <doc>Do not clamp output.</doc> + </value> + <value name="CLAMP_OUTPUT_TO_THE_RANGE" value="1"> + <doc>Clamp output to the range [0,1].</doc> + </value> + </enum> + <enum name="ENUM172"> + <value name="NONE" value="0"> + <doc>NONE: No not write any output.</doc> + </value> + <value name="R" value="1"> + <doc>R: Write the red channel only.</doc> + </value> + <value name="G" value="2"> + <doc>G: Write the green channel only.</doc> + </value> + <value name="RG" value="3"> + <doc>RG: Write the red and green channels.</doc> + </value> + <value name="B" value="4"> + <doc>B: Write the blue channel only.</doc> + </value> + <value name="RB" value="5"> + <doc>RB: Write the red and blue channels.</doc> + </value> + <value name="GB" value="6"> + <doc>GB: Write the green and blue channels.</doc> + </value> + <value name="RGB" value="7"> + <doc>RGB: Write the red, green, and blue channels.</doc> + </value> + </enum> + <enum name="ENUM173"> + <value name="SRC0" value="0"> + <doc>src0.rgb</doc> + </value> + <value name="SRC0" value="1"> + <doc>src0.rrr</doc> + </value> + <value name="SRC0" value="2"> + <doc>src0.ggg</doc> + </value> + <value name="SRC0" value="3"> + <doc>src0.bbb</doc> + </value> + <value name="SRC1" value="4"> + <doc>src1.rgb</doc> + </value> + <value name="SRC1" value="5"> + <doc>src1.rrr</doc> + </value> + <value name="SRC1" value="6"> + <doc>src1.ggg</doc> + </value> + <value name="SRC1" value="7"> + <doc>src1.bbb</doc> + </value> + <value name="SRC2" value="8"> + <doc>src2.rgb</doc> + </value> + <value name="SRC2" value="9"> + <doc>src2.rrr</doc> + </value> + <value name="SRC2" value="10"> + <doc>src2.ggg</doc> + </value> + <value name="SRC2" value="11"> + <doc>src2.bbb</doc> + </value> + <value name="SRC0" value="12"> + <doc>src0.aaa</doc> + </value> + <value name="SRC1" value="13"> + <doc>src1.aaa</doc> + </value> + <value name="SRC2" value="14"> + <doc>src2.aaa</doc> + </value> + <value name="SRCP" value="15"> + <doc>srcp.rgb</doc> + </value> + <value name="SRCP" value="16"> + <doc>srcp.rrr</doc> + </value> + <value name="SRCP" value="17"> + <doc>srcp.ggg</doc> + </value> + <value name="SRCP" value="18"> + <doc>srcp.bbb</doc> + </value> + <value name="SRCP" value="19"> + <doc>srcp.aaa</doc> + </value> + <value name="0" value="20"> + <doc>0.0</doc> + </value> + <value name="1" value="21"> + <doc>1.0</doc> + </value> + <value name="0" value="22"> + <doc>0.5</doc> + </value> + <value name="SRC0" value="23"> + <doc>src0.gbr</doc> + </value> + <value name="SRC1" value="24"> + <doc>src1.gbr</doc> + </value> + <value name="SRC2" value="25"> + <doc>src2.gbr</doc> + </value> + <value name="SRC0" value="26"> + <doc>src0.brg</doc> + </value> + <value name="SRC1" value="27"> + <doc>src1.brg</doc> + </value> + <value name="SRC2" value="28"> + <doc>src2.brg</doc> + </value> + <value name="SRC0" value="29"> + <doc>src0.abg</doc> + </value> + <value name="SRC1" value="30"> + <doc>src1.abg</doc> + </value> + <value name="SRC2" value="31"> + <doc>src2.abg</doc> + </value> + </enum> + <enum name="ENUM174"> + <value name="1" value="0"> + <doc>1.0-2.0*RGB0</doc> + </value> + <value name="RGB1" value="1"> + <doc>RGB1-RGB0</doc> + </value> + <value name="RGB1" value="2"> + <doc>RGB1+RGB0</doc> + </value> + <value name="1" value="3"> + <doc>1.0-RGB0</doc> + </value> + </enum> + <enum name="ENUM178"> + <value name="DISABLED" value="0"> + <doc>Disabled</doc> + </value> + <value name="ENABLED" value="1"> + <doc>Enabled</doc> + </value> + </enum> + <enum name="ENUM179"> + <value name="C4_8" value="0"> + <doc>C4_8 (S/U)</doc> + </value> + <value name="C4_10" value="1"> + <doc>C4_10 (U)</doc> + </value> + <value name="C4_10_GAMMA" value="2"> + <doc>C4_10_GAMMA - (U)</doc> + </value> + <value name="C" value="3"> + <doc>C_</doc> + </value> + <value name="C2" value="4"> + <doc>C2_</doc> + </value> + <value name="C4" value="5"> + <doc>C4_</doc> + </value> + <value name="C_16_MPEG" value="6"> + <doc>C_16_MPEG - (S)</doc> + </value> + <value name="C2_16_MPEG" value="7"> + <doc>C2_16_MPEG - (S)</doc> + </value> + <value name="C2" value="8"> + <doc>C2_</doc> + </value> + <value name="C_3_3" value="9"> + <doc>C_3_3_</doc> + </value> + <value name="C_6_5" value="10"> + <doc>C_6_5_</doc> + </value> + <value name="C_11_11" value="11"> + <doc>C_11_11_</doc> + </value> + <value name="C_10_11" value="12"> + <doc>C_10_11_</doc> + </value> + <value name="C_2_10_10" value="13"> + <doc>C_2_10_10_</doc> + </value> + <value name="UNUSED" value="15"> + <doc>UNUSED - Render target is not used</doc> + </value> + <value name="C_16_FP" value="16"> + <doc>C_16_FP - (S10E5)</doc> + </value> + <value name="C2_16_FP" value="17"> + <doc>C2_16_FP - (S10E5)</doc> + </value> + <value name="C4_16_FP" value="18"> + <doc>C4_16_FP - (S10E5)</doc> + </value> + <value name="C_32_FP" value="19"> + <doc>C_32_FP - (S23E8)</doc> + </value> + <value name="C2_32_FP" value="20"> + <doc>C2_32_FP - (S23E8)</doc> + </value> + <value name="C4_32_FP" value="21"> + <doc>C4_32_FP - (S23E8)</doc> + </value> + </enum> + <enum name="ENUM180"> + <value name="ALPHA" value="0"> + <doc>Alpha</doc> + </value> + <value name="RED" value="1"> + <doc>Red</doc> + </value> + <value name="GREEN" value="2"> + <doc>Green</doc> + </value> + <value name="BLUE" value="3"> + <doc>Blue</doc> + </value> + </enum> + <enum name="ENUM183"> + <value name="WSRC_US" value="0"> + <doc>WSRC_US - W comes from shader instruction</doc> + </value> + <value name="WSRC_RAS" value="1"> + <doc>WSRC_RAS - W comes from rasterizer</doc> + </value> + </enum> + <enum name="ENUM185"> + <value name="255" value="0"> + <doc>255.0) 0 1 0.</doc> + </value> + <value name="1" value="0"> + <doc>1.0 1 0 -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> + -128.</doc> + </value> + <value name="127" value="0"> + <doc>127.0) 1 1 -1.</doc> + </value> + <value name="1" value="0"> + <doc>1.0 where n is the number of bits in the associated + fixed point value For signed, normalize conversion, since the + fixed point range is not evenly distributed around 0, there + are 3 different methods supported by R300. See the + VAP_PSC_SGN_NORM_CNTL description for details.</doc> + </value> + </enum> + <enum name="ENUM187"> + <value name="HIERARCHICAL_Z_DISABLED" value="0"> + <doc>Hierarchical Z Disabled</doc> + </value> + <value name="HIERARCHICAL_Z_ENABLED" value="1"> + <doc>Hierarchical Z Enabled</doc> + </value> + </enum> + <enum name="ENUM188"> + <value name="UPDATE_HIERARCHICAL_Z_WITH_MAX_VALUE" value="0"> + <doc>Update Hierarchical Z with Max value</doc> + </value> + <value name="UPDATE_HIERARCHICAL_Z_WITH_MIN_VALUE" value="1"> + <doc>Update Hierarchical Z with Min value</doc> + </value> + </enum> + <enum name="ENUM189"> + <value name="FAST_FILL_DISABLED" value="0"> + <doc>Fast Fill Disabled</doc> + </value> + <value name="FAST_FILL_ENABLED" value="1"> + <doc>Fast Fill Enabled (ZB_DEPTHCLEARVALUE )</doc> + </value> + </enum> + <enum name="ENUM190"> + <value name="Z_READ_COMPRESSION_DISABLED" value="0"> + <doc>Z Read Compression Disabled</doc> + </value> + <value name="Z_READ_COMPRESSION_ENABLED" value="1"> + <doc>Z Read Compression Enabled</doc> + </value> + </enum> + <enum name="ENUM191"> + <value name="Z_WRITE_COMPRESSION_DISABLED" value="0"> + <doc>Z Write Compression Disabled</doc> + </value> + <value name="Z_WRITE_COMPRESSION_ENABLED" value="1"> + <doc>Z Write Compression Enabled</doc> + </value> + </enum> + <enum name="ENUM192"> + <value name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW" value="0"> + <doc>Z unit cache controller does RMW</doc> + </value> + <value name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE" value="1"> + <doc>Z unit cache controller does cache-line granular Write + only</doc> + </value> + </enum> + <enum name="ENUM196"> + <value name="16" value="0"> + <doc>16-bit Integer Z</doc> + </value> + <value name="16" value="1"> + <doc>16-bit compressed 13E3</doc> + </value> + <value name="24" value="2"> + <doc>24-bit Integer Z, 8 bit Stencil (LSBs)</doc> + </value> + </enum> + <enum name="ENUM202"> + <value name="NEVER" value="0"> + <doc>Never</doc> + </value> + <value name="LESS" value="1"> + <doc>Less</doc> + </value> + <value name="LESS_OR_EQUAL" value="2"> + <doc>Less or Equal</doc> + </value> + <value name="EQUAL" value="3"> + <doc>Equal</doc> + </value> + <value name="GREATER_OR_EQUAL" value="4"> + <doc>Greater or Equal</doc> + </value> + <value name="GREATER_THAN" value="5"> + <doc>Greater Than</doc> + </value> + <value name="NOT_EQUAL" value="6"> + <doc>Not Equal</doc> + </value> + <value name="ALWAYS" value="7"> + <doc>Always</doc> + </value> + </enum> + <enum name="ENUM203"> + <value name="NEVER" value="0"> + <doc>Never</doc> + </value> + <value name="LESS" value="1"> + <doc>Less</doc> + </value> + <value name="LESS_OR_EQUAL" value="2"> + <doc>Less or Equal</doc> + </value> + <value name="EQUAL" value="3"> + <doc>Equal</doc> + </value> + <value name="GREATER_OR_EQUAL" value="4"> + <doc>Greater or Equal</doc> + </value> + <value name="GREATER" value="5"> + <doc>Greater</doc> + </value> + <value name="NOT_EQUAL" value="6"> + <doc>Not Equal</doc> + </value> + <value name="ALWAYS" value="7"> + <doc>Always</doc> + </value> + </enum> + <enum name="ENUM204"> + <value name="KEEP" value="0"> + <doc>Keep: New value = Old value</doc> + </value> + <value name="ZERO" value="1"> + <doc>Zero: New value = 0</doc> + </value> + <value name="REPLACE" value="2"> + <doc>Replace: New value = STENCILREF</doc> + </value> + <value name="INCREMENT" value="3"> + <doc>Increment: New value++ (clamp)</doc> + </value> + <value name="DECREMENT" value="4"> + <doc>Decrement: New value-- (clamp)</doc> + </value> + <value name="INVERT_NEW_VALUE" value="5"> + <doc>Invert new value: New value = !Old value</doc> + </value> + <value name="INCREMENT" value="6"> + <doc>Increment: New value++ (wrap)</doc> + </value> + <value name="DECREMENT" value="7"> + <doc>Decrement: New value-- (wrap)</doc> + </value> + </enum> + <enum name="ENUM209"> + <value name="PHYSICAL" value="0"> + <doc>Physical (Default),</doc> + </value> + <value name="VIRTUAL" value="1"> + <doc>Virtual</doc> + </value> + </enum> + <enum name="ENUM216"> + <value name="FULL_SIZE" value="0"> + <doc>Full size</doc> + </value> + <value name="1" value="1"> + <doc>1/2 size</doc> + </value> + <value name="1" value="2"> + <doc>1/4 size</doc> + </value> + <value name="1" value="3"> + <doc>1/8 size</doc> + </value> + </enum> + <enum name="ENUM221"> + <value name="NO_OVERRIDE" value="0"> + <doc>No override</doc> + </value> + <value name="STUFF_TEXTURE_0" value="1"> + <doc>Stuff texture 0</doc> + </value> + <value name="STUFF_TEXTURE_1" value="2"> + <doc>Stuff texture 1</doc> + </value> + <value name="STUFF_TEXTURE_2" value="3"> + <doc>Stuff texture 2</doc> + </value> + <value name="STUFF_TEXTURE_3" value="4"> + <doc>Stuff texture 3</doc> + </value> + <value name="STUFF_TEXTURE_4" value="5"> + <doc>Stuff texture 4</doc> + </value> + <value name="STUFF_TEXTURE_5" value="6"> + <doc>Stuff texture 5</doc> + </value> + <value name="STUFF_TEXTURE_6" value="7"> + <doc>Stuff texture 6</doc> + </value> + <value name="STUFF_TEXTURE_7" value="8"> + <doc>Stuff texture 7</doc> + </value> + <value name="STUFF_TEXTURE_8" value="9"> + <doc>Stuff texture 8/C2</doc> + </value> + <value name="STUFF_TEXTURE_9" value="10"> + <doc>Stuff texture 9/C3</doc> + </value> + </enum> + <enum name="ENUM229"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES" + value="0"> + <doc>Replicate VAP source texture coordinates + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </enum> + <enum name="ENUM247"> + <value name="DISABLE_CYLINDRICAL_WRAPPING" value="0"> + <doc>Disable cylindrical wrapping.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING" value="1"> + <doc>Enable cylindrical wrapping.</doc> + </value> + </enum> + <enum name="ENUM248"> + <value name="DISABLE" value="0"> + <doc>Disable, ARGB = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </enum> + <enum name="ENUM249"> + <value name="FILTER4" value="0"> + <doc>Filter4</doc> + </value> + <value name="POINT" value="1"> + <doc>Point</doc> + </value> + <value name="LINEAR" value="2"> + <doc>Linear</doc> + </value> + </enum> + <enum name="ENUM256"> + <value name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" + value="0"> + <doc>Component filter should interpret texel data as + unsigned</doc> + </value> + <value name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" + value="1"> + <doc>Component filter should interpret texel data as + signed</doc> + </value> + </enum> + <enum name="ENUM257"> + <value name="SELECT_TEXTURE_COMPONENT0" value="0"> + <doc>Select Texture Component0.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1" value="1"> + <doc>Select Texture Component1.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2" value="2"> + <doc>Select Texture Component2.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3" value="3"> + <doc>Select Texture Component3.</doc> + </value> + <value name="SELECT_THE_VALUE_0" value="4"> + <doc>Select the value 0.</doc> + </value> + <value name="SELECT_THE_VALUE_1" value="5"> + <doc>Select the value 1.</doc> + </value> + </enum> + <enum name="ENUM261"> + <value name="NONE" value="0"> + <doc>NONE: Do not modify destination address.</doc> + </value> + <value name="RELATIVE" value="1"> + <doc>RELATIVE: Add aL to address before write.</doc> + </value> + </enum> + <enum name="ENUM262"> + <value name="SRC0" value="0"> + <doc>src0</doc> + </value> + <value name="SRC1" value="1"> + <doc>src1</doc> + </value> + <value name="SRC2" value="2"> + <doc>src2</doc> + </value> + <value name="SRCP" value="3"> + <doc>srcp</doc> + </value> + </enum> + <enum name="ENUM263"> + <value name="RED" value="0"> + <doc>Red</doc> + </value> + <value name="GREEN" value="1"> + <doc>Green</doc> + </value> + <value name="BLUE" value="2"> + <doc>Blue</doc> + </value> + <value name="ALPHA" value="3"> + <doc>Alpha</doc> + </value> + <value name="ZERO" value="4"> + <doc>Zero</doc> + </value> + <value name="HALF" value="5"> + <doc>Half</doc> + </value> + <value name="ONE" value="6"> + <doc>One</doc> + </value> + <value name="UNUSED" value="7"> + <doc>Unused</doc> + </value> + </enum> + <enum name="ENUM264"> + <value name="RESULT" value="0"> + <doc>Result * 1</doc> + </value> + <value name="RESULT" value="1"> + <doc>Result * 2</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result * 4</doc> + </value> + <value name="RESULT" value="3"> + <doc>Result * 8</doc> + </value> + <value name="RESULT" value="4"> + <doc>Result / 2</doc> + </value> + <value name="RESULT" value="5"> + <doc>Result / 4</doc> + </value> + <value name="RESULT" value="6"> + <doc>Result / 8</doc> + </value> + <value name="DISABLE_OUTPUT_MODIFIER_AND_CLAMPING" value="7"> + <doc>Disable output modifier and clamping (result is copied + exactly; only valid for MIN/MAX/CMP/CND)</doc> + </value> + </enum> + <enum name="ENUM265"> + <value name="A" value="0"> + <doc>A: Output to render target A. Predicate == (ALU)</doc> + </value> + <value name="B" value="1"> + <doc>B: Output to render target B. Predicate < (ALU)</doc> + </value> + <value name="C" value="2"> + <doc>C: Output to render target C. Predicate >= + (ALU)</doc> + </value> + <value name="D" value="3"> + <doc>D: Output to render target D. Predicate != (ALU)</doc> + </value> + </enum> + <enum name="ENUM267"> + <value name="TEMPORARY" value="0"> + <doc>TEMPORARY: Address temporary register or inline constant + value.</doc> + </value> + <value name="CONSTANT" value="1"> + <doc>CONSTANT: Address constant register.</doc> + </value> + </enum> + <enum name="ENUM268"> + <value name="NONE" value="0"> + <doc>NONE: Do not modify source address.</doc> + </value> + <value name="RELATIVE" value="1"> + <doc>RELATIVE: Add aL before lookup.</doc> + </value> + </enum> + <enum name="ENUM274"> + <value name="NORMAL_PREDICATION" value="0"> + <doc>Normal predication</doc> + </value> + <value name="INVERT_THE_VALUE_OF_THE_PREDICATE" value="1"> + <doc>Invert the value of the predicate</doc> + </value> + </enum> + <enum name="ENUM279"> + <value name="NONE" value="0"> + <doc>NONE: Do not write any output.</doc> + </value> + <value name="R" value="1"> + <doc>R: Write the red channel only.</doc> + </value> + <value name="G" value="2"> + <doc>G: Write the green channel only.</doc> + </value> + <value name="RG" value="3"> + <doc>RG: Write the red and green channels.</doc> + </value> + <value name="B" value="4"> + <doc>B: Write the blue channel only.</doc> + </value> + <value name="RB" value="5"> + <doc>RB: Write the red and blue channels.</doc> + </value> + <value name="GB" value="6"> + <doc>GB: Write the green and blue channels.</doc> + </value> + <value name="RGB" value="7"> + <doc>RGB: Write the red, green, and blue channels.</doc> + </value> + </enum> + <enum name="ENUM298"> + <value name="NONE" value="0"> + <doc>NONE: Do not modify source address</doc> + </value> + <value name="RELATIVE" value="1"> + <doc>RELATIVE: Add aL before lookup.</doc> + </value> + </enum> + <enum name="ENUM299"> + <value name="USE_R_CHANNEL_AS_S_COORDINATE" value="0"> + <doc>Use R channel as S coordinate</doc> + </value> + <value name="USE_G_CHANNEL_AS_S_COORDINATE" value="1"> + <doc>Use G channel as S coordinate</doc> + </value> + <value name="USE_B_CHANNEL_AS_S_COORDINATE" value="2"> + <doc>Use B channel as S coordinate</doc> + </value> + <value name="USE_A_CHANNEL_AS_S_COORDINATE" value="3"> + <doc>Use A channel as S coordinate</doc> + </value> + </enum> + <enum name="ENUM300"> + <value name="USE_R_CHANNEL_AS_T_COORDINATE" value="0"> + <doc>Use R channel as T coordinate</doc> + </value> + <value name="USE_G_CHANNEL_AS_T_COORDINATE" value="1"> + <doc>Use G channel as T coordinate</doc> + </value> + <value name="USE_B_CHANNEL_AS_T_COORDINATE" value="2"> + <doc>Use B channel as T coordinate</doc> + </value> + <value name="USE_A_CHANNEL_AS_T_COORDINATE" value="3"> + <doc>Use A channel as T coordinate</doc> + </value> + </enum> + <enum name="ENUM301"> + <value name="USE_R_CHANNEL_AS_R_COORDINATE" value="0"> + <doc>Use R channel as R coordinate</doc> + </value> + <value name="USE_G_CHANNEL_AS_R_COORDINATE" value="1"> + <doc>Use G channel as R coordinate</doc> + </value> + <value name="USE_B_CHANNEL_AS_R_COORDINATE" value="2"> + <doc>Use B channel as R coordinate</doc> + </value> + <value name="USE_A_CHANNEL_AS_R_COORDINATE" value="3"> + <doc>Use A channel as R coordinate</doc> + </value> + </enum> + <enum name="ENUM302"> + <value name="USE_R_CHANNEL_AS_Q_COORDINATE" value="0"> + <doc>Use R channel as Q coordinate</doc> + </value> + <value name="USE_G_CHANNEL_AS_Q_COORDINATE" value="1"> + <doc>Use G channel as Q coordinate</doc> + </value> + <value name="USE_B_CHANNEL_AS_Q_COORDINATE" value="2"> + <doc>Use B channel as Q coordinate</doc> + </value> + <value name="USE_A_CHANNEL_AS_Q_COORDINATE" value="3"> + <doc>Use A channel as Q coordinate</doc> + </value> + </enum> + <group name="rX00_regs"> + <reg32 access="rw" name="RB3D_AARESOLVE_OFFSET" + offset="0x4E80"> + <doc>Resolve buffer destination address. The cache must be + empty before changing this register if the cb is in resolve + mode. Unpipelined</doc> + <bitfield high="31" low="5" name="AARESOLVE_OFFSET" /> + <doc>256-bit aligned 3D resolve destination offset.</doc> + </reg32> + <reg32 access="rw" name="RB3D_AARESOLVE_PITCH" offset="0x4E84"> + <doc>Resolve Buffer Pitch and Tiling Control. The cache must + be empty before changing this register if the cb is in + resolve mode. Unpipelined</doc> + <bitfield high="13" low="1" name="AARESOLVE_PITCH" /> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + </reg32> + <reg32 access="rw" name="RB3D_ABLENDCNTL" offset="0x4E08"> + <doc>Alpha Blend Control for Alpha Channel. Pipelined through + the blender.</doc> + <bitfield high="14" low="12" name="COMB_FCN"> + <use-enum ref="ENUM2" /> + </bitfield> + <doc>Combine Function , Allows modification of how the + SRCBLEND and DESTBLEND are combined.</doc> + <bitfield high="21" low="16" name="SRCBLEND"> + <use-enum ref="ENUM3" /> + </bitfield> + <doc>Source Blend Function , Alpha blending function + (SRC).</doc> + <bitfield high="29" low="24" name="DESTBLEND"> + <use-enum ref="ENUM4" /> + </bitfield> + <doc>Destination Blend Function , Alpha blending function + (DST).</doc> + </reg32> + <reg32 access="rw" name="RB3D_CLRCMP_CLR" offset="0x4E20"> + <doc>Color Compare Color. Stalls the 2d/3d datapath until it + is idle.</doc> + </reg32> + <reg32 access="rw" name="RB3D_CLRCMP_FLIPE" offset="0x4E1C"> + <doc>Color Compare Flip. Stalls the 2d/3d datapath until it + is idle.</doc> + </reg32> + <reg32 access="rw" name="RB3D_CLRCMP_MSK" offset="0x4E24"> + <doc>Color Compare Mask. Stalls the 2d/3d datapath until it + is idle.</doc> + </reg32> + <stripe length="4" offset="0x4E28" stride="0x0004"> + <reg32 access="rw" name="RB3D_COLOROFFSET" offset="0x0"> + <doc>Color Buffer Address Offset of multibuffer 0. + Unpipelined.</doc> + <bitfield high="31" low="5" name="COLOROFFSET" /> + <doc>256-bit aligned 3D destination offset address. The + cache must be empty before this is changed.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="RB3D_DITHER_CTL" offset="0x4E50"> + <doc>Dithering control register. Pipelined through the + blender.</doc> + <bitfield high="1" low="0" name="DITHER_MODE"> + <use-enum ref="ENUM17" /> + </bitfield> + <doc>Dither mode</doc> + <bitfield high="3" low="2" name="ALPHA_DITHER_MODE"> + <use-enum ref="ENUM17" /> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="RB3D_DSTCACHE_CTLSTAT" + offset="0x4E4C"> + <doc>Destination Color Buffer Cache Control/Status. If the cb + is in e2 mode, then a flush or free will not occur upon a + write to this register, but a sync will be immediately sent + if one is requested. If both DC_FLUSH and DC_FREE are zero + but DC_FINISH is one, then a sync will be sent immediately -- + the cb will not wait for all the previous operations to + complete before sending the sync. Unpipelined except when + DC_FINISH and DC_FREE are both set to zero.</doc> + <bitfield high="1" low="0" name="DC_FLUSH"> + <value name="NO_EFFECT" value="0"> + <doc>No effect</doc> + </value> + <value name="NO_EFFECT" value="1"> + <doc>No effect</doc> + </value> + <value name="FLUSHES_DIRTY_3D_DATA" value="2"> + <doc>Flushes dirty 3D data</doc> + </value> + <value name="FLUSHES_DIRTY_3D_DATA" value="3"> + <doc>Flushes dirty 3D data</doc> + </value> + </bitfield> + <doc>Setting this bit flushes dirty data from the 3D Dst + Cache. Unless the DC_FREE bits are also set, the tags in the + cache remain valid. A purge is achieved by setting both + DC_FLUSH and DC_FREE.</doc> + <bitfield high="3" low="2" name="DC_FREE"> + <value name="NO_EFFECT" value="0"> + <doc>No effect</doc> + </value> + <value name="NO_EFFECT" value="1"> + <doc>No effect</doc> + </value> + <value name="FREE_3D_TAGS" value="2"> + <doc>Free 3D tags</doc> + </value> + <value name="FREE_3D_TAGS" value="3"> + <doc>Free 3D tags</doc> + </value> + </bitfield> + <doc>Setting this bit invalidates the 3D Dst Cache tags. + Unless the DC_FLUSH bit is also set, the cache lines are not + written to memory. A purge is achieved by setting both + DC_FLUSH and DC_FREE.</doc> + <bitfield high="4" low="4" name="DC_FINISH"> + <value name="DO_NOT_SEND_A_FINISH_SIGNAL_TO_THE_CP" + value="0"> + <doc>do not send a finish signal to the CP</doc> + </value> + <value name="SEND_A_FINISH_SIGNAL_TO_THE_CP_AFTER_THE_END_OF_OPERATION" + value="1"> + <doc>send a finish signal to the CP after the end of + operation</doc> + </value> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="RB3D_ROPCNTL" offset="0x4E18"> + <doc>3D ROP Control. Stalls the 2d/3d datapath until it is + idle.</doc> + <bitfield high="2" low="2" name="ROP_ENABLE"> + <value name="DISABLE_ROP" value="0"> + <doc>Disable ROP. (Forces ROP2 to be 0xC).</doc> + </value> + <value name="ENABLED" value="1"> + <doc>Enabled</doc> + </value> + </bitfield> + <doc /> + <bitfield high="11" low="8" name="ROP" /> + <doc>ROP2 code for 3D fragments. This value is replicated + into 2 nibbles to form the equivalent ROP3 code to control + the ROP3 logic. These are the GDI ROP2 codes.</doc> + </reg32> + <reg32 access="rw" name="FG_DEPTH_SRC" offset="0x4BD8"> + <doc>Where does depth come from?</doc> + <bitfield high="0" low="0" name="DEPTH_SRC"> + <value name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE_EQUATION" + value="0"> + <doc>Depth comes from scan converter as plane + equation.</doc> + </value> + <value name="DEPTH_COMES_FROM_SHADER_AS_FOUR_DISCRETE_VALUES" + value="1"> + <doc>Depth comes from shader as four discrete + values.</doc> + </value> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="FG_FOG_BLEND" offset="0x4BC0"> + <doc>Fog Blending Enable</doc> + <bitfield high="0" low="0" name="ENABLE"> + <value name="DISABLES_FOG" value="0"> + <doc>Disables fog (output matches input color).</doc> + </value> + <value name="ENABLES_FOG" value="1"> + <doc>Enables fog.</doc> + </value> + </bitfield> + <doc>Enable for fog blending</doc> + <bitfield high="2" low="1" name="FN"> + <value name="FOG_FUNCTION_IS_LINEAR" value="0"> + <doc>Fog function is linear</doc> + </value> + <value name="FOG_FUNCTION_IS_EXPONENTIAL" value="1"> + <doc>Fog function is exponential</doc> + </value> + <value name="FOG_FUNCTION_IS_EXPONENTIAL_SQUARED" + value="2"> + <doc>Fog function is exponential squared</doc> + </value> + <value name="FOG_IS_DERIVED_FROM_CONSTANT_FOG_FACTOR" + value="3"> + <doc>Fog is derived from constant fog factor</doc> + </value> + </bitfield> + <doc>Fog generation function</doc> + </reg32> + <reg32 access="rw" name="GA_COLOR_CONTROL" offset="0x4278"> + <doc>Specifies per RGB or Alpha shading method.</doc> + <bitfield high="1" low="0" name="RGB0_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="3" low="2" name="ALPHA0_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="5" low="4" name="RGB1_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="7" low="6" name="ALPHA1_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="9" low="8" name="RGB2_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="11" low="10" name="ALPHA2_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="13" low="12" name="RGB3_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="15" low="14" name="ALPHA3_SHADING"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies solid, flat or Gouraud shading.</doc> + <bitfield high="17" low="16" name="PROVOKING_VERTEX"> + <value name="PROVOKING_IS_FIRST_VERTEX" value="0"> + <doc>Provoking is first vertex</doc> + </value> + <value name="PROVOKING_IS_SECOND_VERTEX" value="1"> + <doc>Provoking is second vertex</doc> + </value> + <value name="PROVOKING_IS_THIRD_VERTEX" value="2"> + <doc>Provoking is third vertex</doc> + </value> + <value name="PROVOKING_IS_ALWAYS_LAST_VERTEX" value="3"> + <doc>Provoking is always last vertex</doc> + </value> + </bitfield> + <doc>Specifies, for flat shaded polygons, which vertex holds + the polygon color.</doc> + </reg32> + <reg32 access="rw" name="GA_FOG_OFFSET" offset="0x4298"> + <doc>Specifies the offset to apply to fog.</doc> + </reg32> + <reg32 access="rw" name="GA_FOG_SCALE" offset="0x4294"> + <doc>Specifies the scale to apply to fog.</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_S0" offset="0x4264"> + <doc>S Texture Coordinate Value for Vertex 0 of Line (stuff + textures -- i.e. AA)</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_S1" offset="0x4268"> + <doc>S Texture Coordinate Value for Vertex 1 of Lines (V2 of + parallelogram -- stuff textures -- i.e. AA)</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_STIPPLE_CONFIG" + offset="0x4238"> + <doc>Line Stipple configuration information.</doc> + <bitfield high="1" low="0" name="LINE_RESET"> + <value name="NO_RESETING" value="0"> + <doc>No reseting</doc> + </value> + <value name="RESET_PER_LINE" value="1"> + <doc>Reset per line</doc> + </value> + <value name="RESET_PER_PACKET" value="2"> + <doc>Reset per packet</doc> + </value> + </bitfield> + <doc>Specify type of reset to use for stipple + accumulation.</doc> + <bitfield high="31" low="2" name="STIPPLE_SCALE" /> + <doc>Specifies, in truncated (30b) floating point, scale to + apply to generated texture coordinates.</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_STIPPLE_VALUE" + offset="0x4260"> + <doc>Current value of stipple accumulator.</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_MINMAX" offset="0x4230"> + <doc>Specifies maximum and minimum point & sprite sizes + for per vertex size specification.</doc> + <bitfield high="15" low="0" name="MIN_SIZE" /> + <doc>Minimum point & sprite radius (in subsamples) size + to allow.</doc> + <bitfield high="31" low="16" name="MAX_SIZE" /> + <doc>Maximum point & sprite radius (in subsamples) size + to allow.</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_S0" offset="0x4200"> + <doc>S Texture Coordinate of Vertex 0 for Point texture + stuffing (LLC)</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_S1" offset="0x4208"> + <doc>S Texture Coordinate of Vertex 2 for Point texture + stuffing (URC)</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_T0" offset="0x4204"> + <doc>T Texture Coordinate of Vertex 0 for Point texture + stuffing (LLC)</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_T1" offset="0x420C"> + <doc>T Texture Coordinate of Vertex 2 for Point texture + stuffing (URC)</doc> + </reg32> + <reg32 access="rw" name="GA_POLY_MODE" offset="0x4288"> + <doc>Polygon Mode</doc> + <bitfield high="1" low="0" name="POLY_MODE"> + <value name="DISABLE_POLY_MODE" value="0"> + <doc>Disable poly mode (render triangles).</doc> + </value> + <value name="DUAL_MODE" value="1"> + <doc>Dual mode (send 2 sets of 3 polys with specified + poly type).</doc> + </value> + </bitfield> + <doc>Polygon mode enable.</doc> + <bitfield high="6" low="4" name="FRONT_PTYPE"> + <use-enum ref="ENUM37" /> + </bitfield> + <doc>Specifies how to render front-facing polygons.</doc> + <bitfield high="9" low="7" name="BACK_PTYPE"> + <use-enum ref="ENUM37" /> + </bitfield> + <doc>Specifies how to render back-facing polygons.</doc> + </reg32> + <reg32 access="rw" name="GA_TRIANGLE_STIPPLE" offset="0x4214"> + <doc>Specifies amount to shift integer position of vertex + (screen space) before converting to float for triangle + stipple.</doc> + <bitfield high="3" low="0" name="X_SHIFT" /> + <doc>Amount to shift x position before conversion to + SPFP.</doc> + <bitfield high="19" low="16" name="Y_SHIFT" /> + <doc>Amount to shift y position before conversion to + SPFP.</doc> + </reg32> + <reg32 access="rw" name="GB_AA_CONFIG" offset="0x4020"> + <doc>Specifies the graphics pipeline configuration for + antialiasing.</doc> + <bitfield high="0" low="0" name="AA_ENABLE"> + <value name="ANTIALIASING_DISABLED" value="0"> + <doc>Antialiasing disabled(def)</doc> + </value> + <value name="ANTIALIASING_ENABLED" value="1"> + <doc>Antialiasing enabled</doc> + </value> + </bitfield> + <doc>Enables antialiasing.</doc> + <bitfield high="2" low="1" name="NUM_AA_SUBSAMPLES"> + <value name="2_SUBSAMPLES" value="0"> + <doc>2 subsamples</doc> + </value> + <value name="3_SUBSAMPLES" value="1"> + <doc>3 subsamples</doc> + </value> + <value name="4_SUBSAMPLES" value="2"> + <doc>4 subsamples</doc> + </value> + <value name="6_SUBSAMPLES" value="3"> + <doc>6 subsamples</doc> + </value> + </bitfield> + <doc>Specifies the number of subsamples to use while + antialiasing.</doc> + </reg32> + <reg32 access="rw" name="SC_CLIP_0_A" offset="0x43B0"> + <doc>OpenGL Clip rectangles</doc> + <bitfield high="12" low="0" name="XS0" /> + <doc>Left hand edge of clip rectangle</doc> + <bitfield high="25" low="13" name="YS0" /> + <doc>Upper edge of clip rectangle</doc> + </reg32> + <reg32 access="rw" name="SC_CLIP_0_B" offset="0x43B4"> + <doc>OpenGL Clip rectangles</doc> + <bitfield high="12" low="0" name="XS1" /> + <doc>Right hand edge of clip rectangle</doc> + <bitfield high="25" low="13" name="YS1" /> + <doc>Lower edge of clip rectangle</doc> + </reg32> + <reg32 access="rw" name="SC_CLIP_1_A" offset="0x43B8" /> + <reg32 access="rw" name="SC_CLIP_1_B" offset="0x43BC" /> + <reg32 access="rw" name="SC_CLIP_2_A" offset="0x43C0" /> + <reg32 access="rw" name="SC_CLIP_2_B" offset="0x43C4" /> + <reg32 access="rw" name="SC_CLIP_3_A" offset="0x43C8" /> + <reg32 access="rw" name="SC_CLIP_3_B" offset="0x43CC" /> + <reg32 access="rw" name="SC_CLIP_RULE" offset="0x43D0"> + <doc>OpenGL Clip boolean function</doc> + <bitfield high="15" low="0" name="CLIP_RULE" /> + <doc>OpenGL Clip boolean function. The `inside` flags for + each of the four clip rectangles form a 4-bit binary number. + The corresponding bit in this 16-bit number specifies whether + the pixel is visible.</doc> + </reg32> + <reg32 access="rw" name="SC_HYPERZ_EN" offset="0x43A4"> + <doc>Hierarchical Z Enable</doc> + <bitfield high="0" low="0" name="HZ_EN"> + <value name="DISABLES_HYPER" value="0"> + <doc>Disables Hyper-Z.</doc> + </value> + <value name="ENABLES_HYPER" value="1"> + <doc>Enables Hyper-Z.</doc> + </value> + </bitfield> + <doc>Enable for hierarchical Z.</doc> + <bitfield high="1" low="1" name="HZ_MAX"> + <value name="HZ_BLOCK_COMPUTES_MINIMUM_Z_VALUE" value="0"> + <doc>HZ block computes minimum z value</doc> + </value> + <value name="HZ_BLOCK_COMPUTES_MAXIMUM_Z_VALUE" value="1"> + <doc>HZ block computes maximum z value</doc> + </value> + </bitfield> + <doc>Specifies whether to compute min or max z value</doc> + <bitfield high="4" low="2" name="HZ_ADJ"> + <value name="ADD_OR_SUBTRACT_1" value="0"> + <doc>Add or Subtract 1/256 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="1"> + <doc>Add or Subtract 1/128 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="2"> + <doc>Add or Subtract 1/64 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="3"> + <doc>Add or Subtract 1/32 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="4"> + <doc>Add or Subtract 1/16 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="5"> + <doc>Add or Subtract 1/8 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="6"> + <doc>Add or Subtract 1/4 << ze</doc> + </value> + <value name="ADD_OR_SUBTRACT_1" value="7"> + <doc>Add or Subtract 1/2 << ze</doc> + </value> + </bitfield> + <doc>Specifies adjustment to get added or subtracted from + computed z value</doc> + <bitfield high="5" low="5" name="HZ_Z0MIN"> + <value name="VERTEX_0_DOES_NOT_CONTAIN_MINIMUM_Z_VALUE" + value="0"> + <doc>Vertex 0 does not contain minimum z value</doc> + </value> + <value name="VERTEX_0_DOES_CONTAIN_MINIMUM_Z_VALUE" + value="1"> + <doc>Vertex 0 does contain minimum z value</doc> + </value> + </bitfield> + <doc>Specifies whether vertex 0 z contains minimum z + value</doc> + <bitfield high="6" low="6" name="HZ_Z0MAX"> + <value name="VERTEX_0_DOES_NOT_CONTAIN_MAXIMUM_Z_VALUE" + value="0"> + <doc>Vertex 0 does not contain maximum z value</doc> + </value> + <value name="VERTEX_0_DOES_CONTAIN_MAXIMUM_Z_VALUE" + value="1"> + <doc>Vertex 0 does contain maximum z value</doc> + </value> + </bitfield> + <doc>Specifies whether vertex 0 z contains maximum z + value</doc> + </reg32> + <reg32 access="rw" name="SC_SCISSOR0" offset="0x43E0"> + <doc>Scissor rectangle specification</doc> + <bitfield high="12" low="0" name="XS0" /> + <doc>Left hand edge of scissor rectangle</doc> + <bitfield high="25" low="13" name="YS0" /> + <doc>Upper edge of scissor rectangle</doc> + </reg32> + <reg32 access="rw" name="SC_SCISSOR1" offset="0x43E4"> + <doc>Scissor rectangle specification</doc> + <bitfield high="12" low="0" name="XS1" /> + <doc>Right hand edge of scissor rectangle</doc> + <bitfield high="25" low="13" name="YS1" /> + <doc>Lower edge of scissor rectangle</doc> + </reg32> + <reg32 access="rw" name="SC_SCREENDOOR" offset="0x43E8"> + <doc>Screen door sample mask</doc> + <bitfield high="23" low="0" name="SCREENDOOR" /> + <doc>Screen door sample mask - 1 means sample may be covered, + 0 means sample is not covered</doc> + </reg32> + <reg32 access="rw" name="SU_CULL_MODE" offset="0x42B8"> + <doc>Culling Enables</doc> + <bitfield high="0" low="0" name="CULL_FRONT"> + <value name="DO_NOT_CULL_FRONT" value="0"> + <doc>Do not cull front-facing triangles.</doc> + </value> + <value name="CULL_FRONT" value="1"> + <doc>Cull front-facing triangles.</doc> + </value> + </bitfield> + <doc>Enable for front-face culling.</doc> + <bitfield high="1" low="1" name="CULL_BACK"> + <value name="DO_NOT_CULL_BACK" value="0"> + <doc>Do not cull back-facing triangles.</doc> + </value> + <value name="CULL_BACK" value="1"> + <doc>Cull back-facing triangles.</doc> + </value> + </bitfield> + <doc>Enable for back-face culling.</doc> + <bitfield high="2" low="2" name="FACE"> + <value name="POSITIVE_CROSS_PRODUCT_IS_FRONT" value="0"> + <doc>Positive cross product is front (CCW).</doc> + </value> + <value name="NEGATIVE_CROSS_PRODUCT_IS_FRONT" value="1"> + <doc>Negative cross product is front (CW).</doc> + </value> + </bitfield> + <doc>X-Ored with cross product sign to determine positive + facing</doc> + </reg32> + <reg32 access="rw" name="SU_DEPTH_OFFSET" offset="0x42C4"> + <doc>SU Depth Offset value</doc> + </reg32> + <reg32 access="rw" name="SU_DEPTH_SCALE" offset="0x42C0"> + <doc>SU Depth Scale value</doc> + </reg32> + <reg32 access="rw" name="SU_POLY_OFFSET_BACK_OFFSET" + offset="0x42B0"> + <doc>Back-Facing Polygon Offset Offset</doc> + </reg32> + <reg32 access="rw" name="SU_POLY_OFFSET_BACK_SCALE" + offset="0x42AC"> + <doc>Back-Facing Polygon Offset Scale</doc> + </reg32> + <reg32 access="rw" name="SU_POLY_OFFSET_ENABLE" + offset="0x42B4"> + <doc>Enables for polygon offset</doc> + <bitfield high="0" low="0" name="FRONT_ENABLE"> + <value name="DISABLE_FRONT_OFFSET" value="0"> + <doc>Disable front offset.</doc> + </value> + <value name="ENABLE_FRONT_OFFSET" value="1"> + <doc>Enable front offset.</doc> + </value> + </bitfield> + <doc>Enables front facing polygon`s offset.</doc> + <bitfield high="1" low="1" name="BACK_ENABLE"> + <value name="DISABLE_BACK_OFFSET" value="0"> + <doc>Disable back offset.</doc> + </value> + <value name="ENABLE_BACK_OFFSET" value="1"> + <doc>Enable back offset.</doc> + </value> + </bitfield> + <doc>Enables back facing polygon`s offset.</doc> + <bitfield high="2" low="2" name="PARA_ENABLE"> + <value name="DISABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS" + value="0"> + <doc>Disable front offset for parallelograms.</doc> + </value> + <value name="ENABLE_FRONT_OFFSET_FOR_PARALLELOGRAMS" + value="1"> + <doc>Enable front offset for parallelograms.</doc> + </value> + </bitfield> + <doc>Forces all parallelograms to have FRONT_FACING for poly + offset -- Need to have FRONT_ENABLE also set to have Z offset + for parallelograms.</doc> + </reg32> + <reg32 access="rw" name="SU_POLY_OFFSET_FRONT_OFFSET" + offset="0x42A8"> + <doc>Front-Facing Polygon Offset Offset</doc> + </reg32> + <reg32 access="rw" name="SU_POLY_OFFSET_FRONT_SCALE" + offset="0x42A4"> + <doc>Front-Facing Polygon Offset Scale</doc> + </reg32> + <reg32 access="rw" name="TX_INVALTAGS" offset="0x4100"> + <doc>Invalidate texture cache tags</doc> + </reg32> + <reg32 access="rw" name="VAP_GB_HORZ_CLIP_ADJ" offset="0x2228"> + <doc>Horizontal Guard Band Clip Adjust Register</doc> + </reg32> + <reg32 access="rw" name="VAP_GB_HORZ_DISC_ADJ" offset="0x222C"> + <doc>Horizontal Guard Band Discard Adjust Register</doc> + </reg32> + <reg32 access="rw" name="VAP_GB_VERT_CLIP_ADJ" offset="0x2220"> + <doc>Vertical Guard Band Clip Adjust Register</doc> + </reg32> + <reg32 access="rw" name="VAP_GB_VERT_DISC_ADJ" offset="0x2224"> + <doc>Vertical Guard Band Discard Adjust Register</doc> + </reg32> + <reg32 access="rw" name="VAP_OUT_VTX_FMT_0" offset="0x2090"> + <doc>VAP Out/GA Vertex Format Register 0</doc> + <bitfield high="0" low="0" name="VTX_POS_PRESENT" /> + <doc>Output the Position Vector</doc> + <bitfield high="1" low="1" name="VTX_COLOR_0_PRESENT" /> + <doc>Output Color 0 Vector</doc> + <bitfield high="2" low="2" name="VTX_COLOR_1_PRESENT" /> + <doc>Output Color 1 Vector</doc> + <bitfield high="3" low="3" name="VTX_COLOR_2_PRESENT" /> + <doc>Output Color 2 Vector</doc> + <bitfield high="4" low="4" name="VTX_COLOR_3_PRESENT" /> + <doc>Output Color 3 Vector</doc> + <bitfield high="16" low="16" name="VTX_PT_SIZE_PRESENT" /> + <doc>Output Point Size Vector</doc> + </reg32> + <reg32 access="rw" name="VAP_OUT_VTX_FMT_1" offset="0x2094"> + <doc>VAP Out/GA Vertex Format Register 1</doc> + <bitfield high="2" low="0" name="TEX_0_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="5" low="3" name="TEX_1_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="8" low="6" name="TEX_2_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="11" low="9" name="TEX_3_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="14" low="12" name="TEX_4_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="17" low="15" name="TEX_5_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="20" low="18" name="TEX_6_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + <bitfield high="23" low="21" name="TEX_7_COMP_CNT" /> + <doc>Number of words in texture 0 = Not Present 1 = 1 + component 2 = 2 components 3 = 3 components 4 = 4 + components</doc> + </reg32> + <stripe length="16" offset="0x2000" stride="0x0004"> + <reg32 access="w" name="VAP_PORT_DATA" offset="0x0"> + <doc>Setup Engine Data Port 0 through 15.</doc> + </reg32> + </stripe> + <reg32 access="w" name="VAP_PORT_DATA_IDX_128" offset="0x20B8"> + <doc>128-bit Data Port for Indexed Primitives.</doc> + </reg32> + <stripe length="16" offset="0x2040" stride="0x0004"> + <reg32 access="w" name="VAP_PORT_IDX" offset="0x0"> + <doc>Setup Engine Index Port 0 through 15.</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x21E0" stride="0x0004"> + <reg32 access="rw" name="VAP_PROG_STREAM_CNTL_EXT" + offset="0x0"> + <doc>Programmable Stream Control Extension Word 0</doc> + <bitfield high="2" low="0" name="SWIZZLE_SELECT_X_0" /> + <doc>X-Component Swizzle Select 0 = SELECT_X 1 = SELECT_Y 2 + = SELECT_Z 3 = SELECT_W 4 = SELECT_FP_ZERO (Floating Point + 0.0) 5 = SELECT_FP_ONE (Floating Point 1.0) 6,7 + RESERVED</doc> + <bitfield high="5" low="3" name="SWIZZLE_SELECT_Y_0" /> + <doc>Y-Component Swizzle Select (See Above)</doc> + <bitfield high="8" low="6" name="SWIZZLE_SELECT_Z_0" /> + <doc>Z-Component Swizzle Select (See Above)</doc> + <bitfield high="11" low="9" name="SWIZZLE_SELECT_W_0" /> + <doc>W-Component Swizzle Select (See Above)</doc> + <bitfield high="15" low="12" name="WRITE_ENA_0" /> + <doc>4-bit write enable. Bit 0 maps to X Bit 1 maps to Y + Bit 2 maps to Z Bit 3 maps to W</doc> + <bitfield high="18" low="16" name="SWIZZLE_SELECT_X_1" /> + <doc>See SWIZZLE_SELECT_X_0</doc> + <bitfield high="21" low="19" name="SWIZZLE_SELECT_Y_1" /> + <doc>See SWIZZLE_SELECT_Y_0</doc> + <bitfield high="24" low="22" name="SWIZZLE_SELECT_Z_1" /> + <doc>See SWIZZLE_SELECT_Z_0</doc> + <bitfield high="27" low="25" name="SWIZZLE_SELECT_W_1" /> + <doc>See SWIZZLE_SELECT_W_0</doc> + <bitfield high="31" low="28" name="WRITE_ENA_1" /> + <doc>See WRITE_ENA_0</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_PSC_SGN_NORM_CNTL" + offset="0x21DC"> + <doc>Programmable Stream Control Signed Normalize + Control</doc> + <bitfield high="1" low="0" name="SGN_NORM_METHOD_0"> + <value name="SGN_NORM_ZERO" value="0"> + <doc>SGN_NORM_ZERO : value / (2^(n-1)-1), so - 128/127 + will be less that -1.0, -127/127 will yeild -1.0, 0/127 + will yield 0, and 127/127 will yield 1.0 for 8-bit + numbers.</doc> + </value> + <value name="SGN_NORM_ZERO_CLAMP_MINUS_ONE" value="1"> + <doc>SGN_NORM_ZERO_CLAMP_MINUS_ONE: Same as SGN_NORM_ZERO + except -128/127 will yield -1.0 for 8-bit numbers.</doc> + </value> + <value name="SGN_NORM_NO_ZERO" value="2"> + <doc>SGN_NORM_NO_ZERO: (2 * value + 1)/2^n, so - 128 will + yield -255/255 = -1.0, 127 will yield 255/255 = 1.0, but + 0 will yield 1/255 != 0.</doc> + </value> + </bitfield> + <doc>There are 3 methods of normalizing signed numbers:</doc> + <bitfield high="3" low="2" name="SGN_NORM_METHOD_1" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="5" low="4" name="SGN_NORM_METHOD_2" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="7" low="6" name="SGN_NORM_METHOD_3" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="9" low="8" name="SGN_NORM_METHOD_4" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="11" low="10" name="SGN_NORM_METHOD_5" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="13" low="12" name="SGN_NORM_METHOD_6" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="15" low="14" name="SGN_NORM_METHOD_7" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="17" low="16" name="SGN_NORM_METHOD_8" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="19" low="18" name="SGN_NORM_METHOD_9" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="21" low="20" name="SGN_NORM_METHOD_10" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="23" low="22" name="SGN_NORM_METHOD_11" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="25" low="24" name="SGN_NORM_METHOD_12" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="27" low="26" name="SGN_NORM_METHOD_13" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="29" low="28" name="SGN_NORM_METHOD_14" /> + <doc>See SGN_NORM_METHOD_0</doc> + <bitfield high="31" low="30" name="SGN_NORM_METHOD_15" /> + <doc>See SGN_NORM_METHOD_0</doc> + </reg32> + <reg32 access="rw" name="VAP_PVS_CODE_CNTL_0" offset="0x22D0"> + <doc>Programmable Vertex Shader Code Control Register 0</doc> + <bitfield high="9" low="0" name="PVS_FIRST_INST" /> + <doc>First Instruction to Execute in PVS.</doc> + <bitfield high="19" low="10" name="PVS_XYZW_VALID_INST" /> + <doc>The PVS Instruction which updates the clip coordinate + position for the last time. This value is used to lower the + processing priority while trivial clip and back-face culling + decisions are made. This field must be set to valid + instruction.</doc> + <bitfield high="29" low="20" name="PVS_LAST_INST" /> + <doc>Last Instruction (Inclusive) for the PVS to + execute.</doc> + </reg32> + <reg32 access="rw" name="VAP_PVS_CODE_CNTL_1" offset="0x22D8"> + <doc>Programmable Vertex Shader Code Control Register 1</doc> + <bitfield high="9" low="0" name="PVS_LAST_VTX_SRC_INST" /> + <doc>The PVS Instruction which uses the Input Vertex Memory + for the last time. This value is used to free up the Input + Vertex Slots ASAP. This field must be set to a valid + instruction.</doc> + </reg32> + <reg32 access="rw" name="VAP_PVS_CONST_CNTL" offset="0x22D4"> + <doc>Programmable Vertex Shader Constant Control + Register</doc> + <bitfield high="7" low="0" name="PVS_CONST_BASE_OFFSET" /> + <doc>Vector Offset into PVS constant memory to the start of + the constants for the current shader</doc> + <bitfield high="23" low="16" name="PVS_MAX_CONST_ADDR" /> + <doc>The maximum constant address which should be generated + by the shader (Inst Const Addr + Addr Register). If the + address which is generated by the shader is outside the range + of 0 to PVS_MAX_CONST_ADDR, then (0,0,0,0) is returned as the + source operand data.</doc> + </reg32> + <stripe length="16" offset="0x2230" stride="0x0004"> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS" + offset="0x0"> + <doc>Programmable Vertex Shader Flow Control Addresses + Register 0</doc> + <bitfield high="7" low="0" name="PVS_FC_ACT_ADRS_0" /> + <doc>This field defines the last PVS instruction to execute + prior to the control flow redirection. JUMP - The last + instruction executed prior to the jump LOOP - The last + instruction executed prior to the loop (init loop + counter/inc) JSR - The last instruction executed prior to + the jump to the subroutine.</doc> + <bitfield high="15" low="8" + name="PVS_FC_LOOP_CNT_JMP_INST_0" /> + <doc>This field has multiple definitions as follows: JUMP - + The instruction address to jump to. LOOP - The loop count. + *Note loop count of 0 must be replaced by a jump. JSR - The + instruction address to jump to (first inst of + subroutine).</doc> + <bitfield high="23" low="16" name="PVS_FC_LAST_INST_0" /> + <doc>This field has multiple definitions as follows: JUMP - + Not Applicable LOOP - The last instruction of the loop. JSR + - The last instruction of the subroutine.</doc> + <bitfield high="31" low="24" name="PVS_FC_RTN_INST_0" /> + <doc>This field has multiple definitions as follows: JUMP - + Not Applicable LOOP - First Instruction of Loop (Typically + ACT_ADRS + 1) JSR - First Instruction After JSR (Typically + ACT_ADRS + 1)</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_OPC" + offset="0x22DC"> + <doc>Programmable Vertex Shader Flow Control Opcode + Register</doc> + <bitfield high="1" low="0" name="PVS_FC_OPC_0" /> + <doc>This opcode field determines what type of control flow + instruction to execute. 0 = NO_OP 1 = JUMP 2 = LOOP 3 = JSR + (Jump to Subroutine)</doc> + <bitfield high="3" low="2" name="PVS_FC_OPC_1" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="5" low="4" name="PVS_FC_OPC_2" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="7" low="6" name="PVS_FC_OPC_3" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="9" low="8" name="PVS_FC_OPC_4" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="11" low="10" name="PVS_FC_OPC_5" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="13" low="12" name="PVS_FC_OPC_6" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="15" low="14" name="PVS_FC_OPC_7" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="17" low="16" name="PVS_FC_OPC_8" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="19" low="18" name="PVS_FC_OPC_9" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="21" low="20" name="PVS_FC_OPC_10" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="23" low="22" name="PVS_FC_OPC_11" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="25" low="24" name="PVS_FC_OPC_12" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="27" low="26" name="PVS_FC_OPC_13" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="29" low="28" name="PVS_FC_OPC_14" /> + <doc>See PVS_FC_OPC_0.</doc> + <bitfield high="31" low="30" name="PVS_FC_OPC_15" /> + <doc>See PVS_FC_OPC_0.</doc> + </reg32> + <reg32 access="rw" name="VAP_PVS_STATE_FLUSH_REG" + offset="0x2284" /> + <reg32 access="rw" name="VAP_PVS_VECTOR_DATA_REG" + offset="0x2204" /> + <reg32 access="w" name="VAP_PVS_VECTOR_DATA_REG_128" + offset="0x2208" /> + <reg32 access="rw" name="VAP_PVS_VECTOR_INDX_REG" + offset="0x2200"> + <bitfield high="10" low="0" name="OCTWORD_OFFSET" /> + <doc>Octword offset to begin writing.</doc> + </reg32> + <reg32 access="rw" name="VAP_PVS_VTX_TIMEOUT_REG" + offset="0x2288" /> + <reg32 access="rw" name="VAP_VF_MAX_VTX_INDX" offset="0x2134"> + <doc>Maximum Vertex Indx Clamp</doc> + <bitfield high="23" low="0" name="MAX_INDX" /> + <doc>If index to be fetched is larger than this value, the + fetch indx is set to MAX_INDX</doc> + </reg32> + <reg32 access="rw" name="VAP_VF_MIN_VTX_INDX" offset="0x2138"> + <doc>Minimum Vertex Indx Clamp</doc> + <bitfield high="23" low="0" name="MIN_INDX" /> + <doc>If index to be fetched is smaller than this value, the + fetch indx is set to MIN_INDX</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_XOFFSET" offset="0x209C"> + <doc>Viewport Transform X Offset</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_XSCALE" offset="0x2098"> + <doc>Viewport Transform X Scale Factor</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_YOFFSET" offset="0x20A4"> + <doc>Viewport Transform Y Offset</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_YSCALE" offset="0x20A0"> + <doc>Viewport Transform Y Scale Factor</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_ZOFFSET" offset="0x20AC"> + <doc>Viewport Transform Z Offset</doc> + </reg32> + <reg32 access="rw" name="VAP_VPORT_ZSCALE" offset="0x20A8"> + <doc>Viewport Transform Z Scale Factor</doc> + </reg32> + <reg32 access="rw" name="VAP_VTE_CNTL" offset="0x20B0"> + <doc>Viewport Transform Engine Control</doc> + <bitfield high="0" low="0" name="VPORT_X_SCALE_ENA" /> + <doc>Viewport Transform Scale Enable for X component</doc> + <bitfield high="1" low="1" name="VPORT_X_OFFSET_ENA" /> + <doc>Viewport Transform Offset Enable for X component</doc> + <bitfield high="2" low="2" name="VPORT_Y_SCALE_ENA" /> + <doc>Viewport Transform Scale Enable for Y component</doc> + <bitfield high="3" low="3" name="VPORT_Y_OFFSET_ENA" /> + <doc>Viewport Transform Offset Enable for Y component</doc> + <bitfield high="4" low="4" name="VPORT_Z_SCALE_ENA" /> + <doc>Viewport Transform Scale Enable for Z component</doc> + <bitfield high="5" low="5" name="VPORT_Z_OFFSET_ENA" /> + <doc>Viewport Transform Offset Enable for Z component</doc> + <bitfield high="8" low="8" name="VTX_XY_FMT" /> + <doc>Indicates that the incoming X, Y have already been + multiplied by 1/W0. If OFF, the Setup Engine will bultiply + the X, Y coordinates by 1/W0.,</doc> + <bitfield high="9" low="9" name="VTX_Z_FMT" /> + <doc>Indicates that the incoming Z has already been + multiplied by 1/W0. If OFF, the Setup Engine will multiply + the Z coordinate by 1/W0.</doc> + <bitfield high="10" low="10" name="VTX_W0_FMT" /> + <doc>Indicates that the incoming W0 is not 1/W0. If ON, the + Setup Engine will perform the reciprocal to get 1/W0.</doc> + <bitfield high="11" low="11" name="SERIAL_PROC_ENA" /> + <doc>If set, x,y,z viewport transform are performed serially + through a single pipeline instead of in parallel. Used to + mimic RL300 design.</doc> + </reg32> + <stripe length="16" offset="0x20C8" stride="0x0005"> + <reg32 access="rw" name="VAP_VTX_AOS_ADDR" offset="0x0"> + <doc>Array-of-Structures Address 0</doc> + <bitfield high="31" low="2" name="VTX_AOS_ADDR0" /> + <doc>Base Address of the Array of Structures.</doc> + </reg32> + </stripe> + <stripe length="1415" offset="0x20C4" stride="0x0000"> + <reg32 access="rw" name="VAP_VTX_AOS_ATTR" offset="0x0"> + <doc>Array-of-Structures Attributes 0 & 1</doc> + <bitfield high="6" low="0" name="VTX_AOS_COUNT0" /> + <doc>Number of dwords in this structure.</doc> + <bitfield high="14" low="8" name="VTX_AOS_STRIDE0" /> + <doc>Number of dwords from one array element to the + next.</doc> + <bitfield high="22" low="16" name="VTX_AOS_COUNT1" /> + <doc>Number of dwords in this structure.</doc> + <bitfield high="30" low="24" name="VTX_AOS_STRIDE1" /> + <doc>Number of dwords from one array element to the + next.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_VTX_SIZE" offset="0x20B4"> + <doc>Vertex Size Specification Register</doc> + <bitfield high="6" low="0" name="DWORDS_PER_VTX" /> + <doc>This field specifies the number of DWORDS per vertex to + expect when VAP_VF_CNTL.PRIM_WALK is set to Vertex Data + (vertex data embedded in command stream). This field is not + used for any other PRIM_WALK settings. This field replaces + the usage of the VAP_VTX_FMT_0/1 for this purpose in prior + implementations.</doc> + </reg32> + <reg32 access="rw" name="ZB_DEPTHCLEARVALUE" offset="0x4F28"> + <doc>Z Buffer Clear Value</doc> + </reg32> + <reg32 access="rw" name="ZB_DEPTHOFFSET" offset="0x4F20"> + <doc>Z Buffer Address Offset</doc> + <bitfield high="31" low="5" name="DEPTHOFFSET" /> + <doc>2K aligned Z buffer address offset for macro + tiles.</doc> + </reg32> + <reg32 access="rw" name="ZB_DEPTHPITCH" offset="0x4F24"> + <doc>Z Buffer Pitch and Endian Control</doc> + <bitfield high="13" low="2" name="DEPTHPITCH" /> + <doc>Z buffer pitch in multiples of 4 pixels.</doc> + <bitfield high="16" low="16" name="DEPTHMACROTILE"> + <value name="MACRO_TILING_DISABLED" value="0"> + <doc>macro tiling disabled</doc> + </value> + <value name="MACRO_TILING_ENABLED" value="1"> + <doc>macro tiling enabled</doc> + </value> + </bitfield> + <doc>Specifies whether Z buffer is macro-tiled. macro-tiles + are 2K aligned</doc> + <bitfield high="18" low="17" name="DEPTHMICROTILE"> + <value name="32_BYTE_CACHE_LINE_IS_LINEAR" value="0"> + <doc>32 byte cache line is linear</doc> + </value> + <value name="32_BYTE_CACHE_LINE_IS_TILED" value="1"> + <doc>32 byte cache line is tiled</doc> + </value> + <value name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE" value="2"> + <doc>32 byte cache line is tiled square (only applies to + 16-bit pixels)</doc> + </value> + </bitfield> + <doc>Specifies whether Z buffer is micro-tiled. micro-tiles + is 32 bytes</doc> + <bitfield high="20" low="19" name="DEPTHENDIAN"> + <value name="NO_SWAP" value="0"> + <doc>No swap</doc> + </value> + <value name="WORD_SWAP" value="1"> + <doc>Word swap</doc> + </value> + <value name="DWORD_SWAP" value="2"> + <doc>Dword swap</doc> + </value> + <value name="HALF_DWORD_SWAP" value="3"> + <doc>Half Dword swap</doc> + </value> + </bitfield> + <doc>Specifies endian control for the Z buffer.</doc> + </reg32> + <reg32 access="rw" name="ZB_DEPTHXY_OFFSET" offset="0x4F60"> + <doc>Depth buffer X and Y coordinate offset</doc> + <bitfield high="11" low="1" name="DEPTHX_OFFSET" /> + <doc>X coordinate offset. multiple of 32 . Bits 4:0 have to + be zero</doc> + <bitfield high="27" low="17" name="DEPTHY_OFFSET" /> + <doc>Y coordinate offset. multiple of 32 . Bits 4:0 have to + be zero</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_DWORD" offset="0x4F4C"> + <doc>Hierarchical Z Data</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_PITCH" offset="0x4F54"> + <doc>Hierarchical Z Pitch</doc> + <bitfield high="13" low="4" name="HIZ_PITCH" /> + <doc>Pitch used in HiZ address computation.</doc> + </reg32> + <reg32 access="rw" name="ZB_STENCILREFMASK" offset="0x4F08"> + <doc>Stencil Reference Value and Mask</doc> + <bitfield high="7" low="0" name="STENCILREF" /> + <doc>Specifies the reference stencil value.</doc> + <bitfield high="15" low="8" name="STENCILMASK" /> + <doc>This value is ANDed with both the reference and the + current stencil value prior to the stencil test.</doc> + <bitfield high="23" low="16" name="STENCILWRITEMASK" /> + <doc>Specifies the write mask for the stencil planes.</doc> + </reg32> + <reg32 access="rw" name="ZB_ZCACHE_CTLSTAT" offset="0x4F18"> + <doc>Z Buffer Cache Control/Status</doc> + <bitfield high="0" low="0" name="ZC_FLUSH"> + <value name="NO_EFFECT" value="0"> + <doc>No effect</doc> + </value> + <value name="FLUSH_AND_FREE_Z_CACHE_LINES" value="1"> + <doc>Flush and Free Z cache lines</doc> + </value> + </bitfield> + <doc>Setting this bit flushes the dirty data from the Z + cache. Unless ZC_FREE bit is also set, the tags in the cache + remain valid. A purge is achieved by setting both ZC_FLUSH + and ZC_FREE. This is a sticky bit and it clears itself at the + end of the operation.</doc> + <bitfield high="1" low="1" name="ZC_FREE"> + <value name="NO_EFFECT" value="0"> + <doc>No effect</doc> + </value> + <value name="FREE_Z_CACHE_LINES" value="1"> + <doc>Free Z cache lines (invalidate)</doc> + </value> + </bitfield> + <doc>Setting this bit invalidates the Z cache tags. Unless + ZC_FLUSH bit is also set, the cachelines are not written to + memory. A purge is achieved by setting both ZC_FLUSH and + ZC_FREE. This is a sticky bit that clears itself at the end + of the operation.</doc> + <bitfield high="31" low="31" name="ZC_BUSY"> + <value name="IDLE" value="0"> + <doc>Idle</doc> + </value> + <value name="BUSY" value="1"> + <doc>Busy</doc> + </value> + </bitfield> + <doc>This bit is unused ...</doc> + </reg32> + <reg32 access="rw" name="ZB_ZPASS_ADDR" offset="0x4F5C"> + <doc>Z Buffer Z Pass Counter Address</doc> + <bitfield high="31" low="2" name="ZPASS_ADDR" /> + <doc>Writing this location with a DWORD address causes the + value in ZB_ZPASS_DATA to be written to main memory at the + location pointed to by this address. NOTE: R300 has 2 pixel + pipes. Broadcasting this address causes both pipes to write + their ZPASS value to the same address. There is no guarantee + which pipe will write last. So when writing to this register, + the GA needs to be programmed to send the write command to + pipe 0. Then a different address needs to be written to pipe + 1. Then both pipes should be enabled for further register + writes.</doc> + </reg32> + <reg32 access="rw" name="ZB_ZPASS_DATA" offset="0x4F58"> + <doc>Z Buffer Z Pass Counter Data</doc> + </reg32> + <reg32 access="rw" name="ZB_ZTOP" offset="0x4F14"> + <bitfield high="0" low="0" name="ZTOP"> + <value name="Z_IS_AT_THE_BOTTOM_OF_THE_PIPE" value="0"> + <doc>Z is at the bottom of the pipe, after the fog + unit.</doc> + </value> + <value name="Z_IS_AT_THE_TOP_OF_THE_PIPE" value="1"> + <doc>Z is at the top of the pipe, after the scan + unit.</doc> + </value> + </bitfield> + <doc /> + </reg32> + </group> + <group name="r300_regs"> + <reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88"> + <doc>Resolve Buffer Control. Unpipelined</doc> + <bitfield high="0" low="0" name="AARESOLVE_MODE" /> + <doc>Specifies if the color buffer is in resolve mode. The + cache must be empty before changing this register.</doc> + <bitfield high="1" low="1" name="AARESOLVE_GAMMA"> + <use-enum ref="ENUM1" /> + </bitfield> + <doc>Specifies the gamma and degamma to be applied to the + samples before and after filtering, respectively.</doc> + </reg32> + <reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04"> + <doc>Alpha Blend Control for Color Channels. Pipelined + through the blender.</doc> + <bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Allow alpha blending with the destination.</doc> + <bitfield high="1" low="1" name="SEPARATE_ALPHA_ENABLE"> + <use-enum ref="ENUM6" /> + </bitfield> + <doc>Enables use of RB3D_ABLENDCNTL</doc> + <bitfield high="2" low="2" name="READ_ENABLE"> + <use-enum ref="ENUM7" /> + </bitfield> + <doc>When blending is enabled, this enables memory reads. + Memory reads will still occur when this is disabled if they + are for reasons not related to blending.</doc> + <bitfield high="5" low="3" name="DISCARD_SRC_PIXELS"> + <value name="DISABLE" value="0"> + <doc>Disable</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="1"> + <doc>Discard pixels if src alpha == 0</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_COLOR" value="2"> + <doc>Discard pixels if src color == 0</doc> + </value> + <value name="DISCARD_PIXELS_IF" value="3"> + <doc>Discard pixels if (src alpha == 0) && (src + color == 0)</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="4"> + <doc>Discard pixels if src alpha == 1</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_COLOR" value="5"> + <doc>Discard pixels if src color == 1</doc> + </value> + <value name="DISCARD_PIXELS_IF" value="6"> + <doc>Discard pixels if (src alpha == 1) && (src + color == 1)</doc> + </value> + </bitfield> + <doc>Discard pixels when blending is enabled based on the src + color.</doc> + <bitfield high="14" low="12" name="COMB_FCN"> + <use-enum ref="ENUM2" /> + </bitfield> + <doc>Combine Function , Allows modification of how the + SRCBLEND and DESTBLEND are combined.</doc> + <bitfield high="21" low="16" name="SRCBLEND"> + <use-enum ref="ENUM3" /> + </bitfield> + <doc>Source Blend Function , Alpha blending function + (SRC).</doc> + <bitfield high="29" low="24" name="DESTBLEND"> + <use-enum ref="ENUM4" /> + </bitfield> + <doc>Destination Blend Function , Alpha blending function + (DST).</doc> + </reg32> + <reg32 access="rw" name="RB3D_CCTL" offset="0x4E00"> + <doc>Unpipelined.</doc> + <bitfield high="6" low="5" name="NUM_MULTIWRITES"> + <use-enum ref="ENUM9" /> + </bitfield> + <doc>A quad is replicated and written to this many + buffers.</doc> + <bitfield high="7" low="7" name="CLRCMP_FLIPE_ENABLE"> + <use-enum ref="ENUM10" /> + </bitfield> + <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare + mode. This is used to ensure 3D data does not get chromakeyed + away by logic in the backend.</doc> + <bitfield high="9" low="9" name="AA_COMPRESSION_ENABLE"> + <use-enum ref="ENUM11" /> + </bitfield> + <doc>Enables AA color compression. The cache must be empty + before this is changed.</doc> + <bitfield high="10" low="10" name="Reserved" /> + <doc>Set to 0</doc> + </reg32> + <stripe length="4" offset="0x4E38" stride="0x0004"> + <reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0"> + <doc>Color buffer format and tiling control for all the + multibuffers and the pitch of multibuffer 0. Unpipelined. + The cache must be empty before any of the registers are + changed.</doc> + <bitfield high="13" low="1" name="COLORPITCH" /> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + <bitfield high="16" low="16" name="COLORTILE"> + <use-enum ref="ENUM12" /> + </bitfield> + <doc>Denotes whether the 3D destination is in macrotiled + format.</doc> + <bitfield high="18" low="17" name="COLORMICROTILE"> + <use-enum ref="ENUM13" /> + </bitfield> + <doc>Denotes whether the 3D destination is in microtiled + format.</doc> + <bitfield high="20" low="19" name="COLORENDIAN"> + <use-enum ref="ENUM14" /> + </bitfield> + <doc>Specifies endian control for the color buffer.</doc> + <bitfield high="24" low="21" name="COLORFORMAT"> + <value name="ARGB1555" value="3"> + <doc>ARGB1555</doc> + </value> + <value name="RGB565" value="4"> + <doc>RGB565</doc> + </value> + <value name="ARGB8888" value="6"> + <doc>ARGB8888</doc> + </value> + <value name="ARGB32323232" value="7"> + <doc>ARGB32323232</doc> + </value> + <value name="I8" value="9"> + <doc>I8</doc> + </value> + <value name="ARGB16161616" value="10"> + <doc>ARGB16161616</doc> + </value> + <value name="YUV422_PACKED" value="11"> + <doc>YUV422 packed (VYUY)</doc> + </value> + <value name="YUV422_PACKED" value="12"> + <doc>YUV422 packed (YVYU)</doc> + </value> + <value name="UV88" value="13"> + <doc>UV88</doc> + </value> + <value name="ARGB4444" value="15"> + <doc>ARGB4444</doc> + </value> + </bitfield> + <doc>3D destination color format.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" + offset="0x4E0C"> + <doc>3D Color Channel Mask. If all the channels used in the + current color format are disabled, then the cb will discard + all the incoming quads. Pipelined through the blender.</doc> + <bitfield high="0" low="0" name="BLUE_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for blue channel</doc> + <bitfield high="1" low="1" name="GREEN_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for green channel</doc> + <bitfield high="2" low="2" name="RED_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for red channel</doc> + <bitfield high="3" low="3" name="ALPHA_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for alpha channel</doc> + </reg32> + <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" + offset="0x4E14"> + <doc>Clear color that is used when the color mask is set to + 00. Unpipelined.</doc> + </reg32> + <reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10"> + <doc>Constant color used by the blender. Pipelined through + the blender.</doc> + <bitfield high="7" low="0" name="BLUE" /> + <doc>blue constant color</doc> + <bitfield high="15" low="8" name="GREEN" /> + <doc>green constant color</doc> + <bitfield high="23" low="16" name="RED" /> + <doc>red constant color</doc> + <bitfield high="31" low="24" name="ALPHA" /> + <doc>alpha constant color</doc> + </reg32> + <reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4"> + <doc>Alpha Function</doc> + <bitfield high="7" low="0" name="AF_VAL" /> + <doc>Specifies the alpha compare value.</doc> + <bitfield high="10" low="8" name="AF_FUNC"> + <use-enum ref="ENUM22" /> + </bitfield> + <doc>Specifies the alpha compare function.</doc> + <bitfield high="11" low="11" name="AF_EN"> + <use-enum ref="ENUM23" /> + </bitfield> + <doc>Enables/Disables alpha compare function.</doc> + <bitfield high="16" low="16" name="AM_EN"> + <use-enum ref="ENUM24" /> + </bitfield> + <doc>Enables/Disables alpha-to-mask function.</doc> + <bitfield high="17" low="17" name="AM_CFG"> + <use-enum ref="ENUM25" /> + </bitfield> + <doc>Specfies number of sub-pixel samples for alpha-to-mask + function.</doc> + <bitfield high="20" low="20" name="DITH_EN"> + <use-enum ref="ENUM26" /> + </bitfield> + <doc>Enables/Disables RGB Dithering.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0"> + <doc>Blue Component of Fog Color</doc> + <bitfield high="9" low="0" name="BLUE" /> + <doc>Blue component of fog color; (0.9) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC"> + <doc>Green Component of Fog Color</doc> + <bitfield high="9" low="0" name="GREEN" /> + <doc>Green component of fog color; (0.9) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8"> + <doc>Red Component of Fog Color</doc> + <bitfield high="9" low="0" name="RED" /> + <doc>Red component of fog color; (0.9) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4"> + <doc>Constant Factor for Fog Blending</doc> + <bitfield high="9" low="0" name="FACTOR" /> + <doc>Constant fog factor; fixed (0.9) format.</doc> + </reg32> + <reg32 access="rw" name="GA_ENHANCE" offset="0x4274"> + <doc>GA Enhancement Register</doc> + <bitfield high="0" low="0" name="DEADLOCK_CNTL"> + <use-enum ref="ENUM32" /> + </bitfield> + <doc>TCL/GA Deadlock control.</doc> + <bitfield high="1" low="1" name="FASTSYNC_CNTL"> + <use-enum ref="ENUM33" /> + </bitfield> + <doc>Enables Fast register/primitive switching</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234"> + <doc>Line control</doc> + <bitfield high="15" low="0" name="WIDTH" /> + <doc>1/2 width of line, in subpixels; (16.0) fixed + format.</doc> + <bitfield high="17" low="16" name="END_TYPE"> + <use-enum ref="ENUM34" /> + </bitfield> + <doc>Specifies how ends of lines should be drawn.</doc> + </reg32> + <reg32 access="rw" name="GA_OFFSET" offset="0x4290"> + <doc>Specifies x & y offsets for vertex data after + conversion to FP.</doc> + <bitfield high="15" low="0" name="X_OFFSET" /> + <doc>Specifies X offset in S15 format (subpixels).</doc> + <bitfield high="31" low="16" name="Y_OFFSET" /> + <doc>Specifies Y offset in S15 format (subpixels).</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C"> + <doc>Dimensions for Points</doc> + <bitfield high="15" low="0" name="HEIGHT" /> + <doc>1/2 Height of point; fixed (16.0), subpixel + format.</doc> + <bitfield high="31" low="16" name="WIDTH" /> + <doc>1/2 Width of point; fixed (16.0), subpixel format.</doc> + </reg32> + <reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C"> + <doc>Specifies the rouding mode for geometry & color SPFP + to FP conversions.</doc> + <bitfield high="1" low="0" name="GEOMETRY_ROUND"> + <use-enum ref="ENUM38" /> + </bitfield> + <doc>Trunc (0) or round to nearest (1) for geometry + (XY).</doc> + <bitfield high="3" low="2" name="COLOR_ROUND"> + <use-enum ref="ENUM38" /> + </bitfield> + <doc>Trunc (0) or round to nearest (1) for colors + (RGBA).</doc> + <bitfield high="4" low="4" name="RGB_CLAMP"> + <value name="CLAMP_TO" value="0"> + <doc>Clamp to [0,1.0] for RGB</doc> + </value> + <value name="CLAMP_TO" value="1"> + <doc>Clamp to [-7.9999, 7.9999] for RGB</doc> + </value> + </bitfield> + <doc>Specifies SPFP color clamp range of [0,1] or [-8,8] for + RGB.</doc> + <bitfield high="5" low="5" name="ALPHA_CLAMP"> + <value name="CLAMP_TO" value="0"> + <doc>Clamp to [0,1.0] for Alpha</doc> + </value> + <value name="CLAMP_TO" value="1"> + <doc>Clamp to [-7.9999, 7.9999] for Alpha</doc> + </value> + </bitfield> + <doc>Specifies SPFP alpha clamp range of [0,1] or + [-8,8].</doc> + </reg32> + <reg32 access="rw" name="GA_SOFT_RESET" offset="0x429C"> + <doc>Specifies number of cycles to assert reset, and also + causes RB3D soft reset to assert.</doc> + <bitfield high="15" low="0" name="SOFT_RESET_COUNT" /> + <doc>Count in cycles (def 256).</doc> + </reg32> + <reg32 access="rw" name="GA_SOLID_BA" offset="0x4280"> + <doc>Specifies blue & alpha components of fill + color.</doc> + <bitfield high="15" low="0" name="COLOR_ALPHA" /> + <doc>Component alpha value. (S3.12)</doc> + <bitfield high="31" low="16" name="COLOR_BLUE" /> + <doc>Component blue value. (S3.12)</doc> + </reg32> + <reg32 access="rw" name="GA_SOLID_RG" offset="0x427C"> + <doc>Specifies red & green components of fill + color.</doc> + <bitfield high="15" low="0" name="COLOR_GREEN" /> + <doc>Component green value (S3.12).</doc> + <bitfield high="31" low="16" name="COLOR_RED" /> + <doc>Component red value (S3.12).</doc> + </reg32> + <reg32 access="rw" name="GB_ENABLE" offset="0x4008"> + <doc>Specifies top of Raster pipe specific enable + controls.</doc> + <bitfield high="0" low="0" name="POINT_STUFF_ENABLE"> + <use-enum ref="ENUM43" /> + </bitfield> + <doc>Specifies if points will have stuffed texture + coordinates.</doc> + <bitfield high="1" low="1" name="LINE_STUFF_ENABLE"> + <use-enum ref="ENUM44" /> + </bitfield> + <doc>Specifies if lines will have stuffed texture + coordinates.</doc> + <bitfield high="2" low="2" name="TRIANGLE_STUFF_ENABLE"> + <use-enum ref="ENUM45" /> + </bitfield> + <doc>Specifies if triangles will have stuffed texture + coordinates.</doc> + <bitfield high="5" low="4" name="STENCIL_AUTO"> + <use-enum ref="ENUM46" /> + </bitfield> + <doc>Specifies if the auto dec/inc stencil mode should be + enabled, and how.</doc> + <bitfield high="17" low="16" name="TEX0_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_0" + value="0"> + <doc>Replicate VAP source texture coordinates 0 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="19" low="18" name="TEX1_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_1" + value="0"> + <doc>Replicate VAP source texture coordinates 1 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="21" low="20" name="TEX2_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_2" + value="0"> + <doc>Replicate VAP source texture coordinates 2 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="23" low="22" name="TEX3_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_3" + value="0"> + <doc>Replicate VAP source texture coordinates 3 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="25" low="24" name="TEX4_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_4" + value="0"> + <doc>Replicate VAP source texture coordinates 4 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="27" low="26" name="TEX5_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_5" + value="0"> + <doc>Replicate VAP source texture coordinates 5 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="29" low="28" name="TEX6_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_6" + value="0"> + <doc>Replicate VAP source texture coordinates 6 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + <bitfield high="31" low="30" name="TEX7_SOURCE"> + <value name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_7" + value="0"> + <doc>Replicate VAP source texture coordinates 7 + (S,T,[R,Q]).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="1"> + <doc>Stuff with source texture coordinates (S,T).</doc> + </value> + <value name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES" + value="2"> + <doc>Stuff with source texture coordinates (S,T,R).</doc> + </value> + </bitfield> + <doc>Specifies the source of the texture coordinates for this + texture.</doc> + </reg32> + <reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024"> + <doc>Specifies the sizes of the various FIFO`s in the + sc/rs/us. This register must be the first one written</doc> + <bitfield high="1" low="0" name="SC_IFIFO_SIZE"> + <use-enum ref="ENUM55" /> + </bitfield> + <doc>Size of scan converter input FIFO (XYZ)</doc> + <bitfield high="3" low="2" name="SC_TZFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of scan converter top-of-pipe Z FIFO</doc> + <bitfield high="5" low="4" name="SC_BFIFO_SIZE"> + <use-enum ref="ENUM55" /> + </bitfield> + <doc>Size of scan converter input FIFO (B)</doc> + <bitfield high="7" low="6" name="RS_TFIFO_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of ras input FIFO (Texture)</doc> + <bitfield high="9" low="8" name="RS_CFIFO_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of ras input FIFO (Color)</doc> + <bitfield high="11" low="10" name="US_RAM_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of us RAM</doc> + <bitfield high="13" low="12" name="US_OFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of us output FIFO (RGBA)</doc> + <bitfield high="15" low="14" name="US_WFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of us output FIFO (W)</doc> + <bitfield high="18" low="16" name="RS_HIGHWATER_COL" /> + <doc>High water mark for RS color FIFO (0-7, default 7)</doc> + <bitfield high="21" low="19" name="RS_HIGHWATER_TEX" /> + <doc>High water mark for RS texture FIFO (0-7, default + 7)</doc> + <bitfield high="23" low="22" name="US_OFIFO_HIGHWATER"> + <use-enum ref="ENUM58" /> + </bitfield> + <doc>High water mark for US output FIFO (0-12, default + 4)</doc> + <bitfield high="27" low="24" name="US_CUBE_FIFO_HIGHWATER" /> + <doc>High water mark for US texture output FIFO (0-15, + default 11)</doc> + </reg32> + <reg32 access="rw" name="GB_MSPOS0" offset="0x4010"> + <doc>Specifies the position of multisamples 0 through 2</doc> + <bitfield high="3" low="0" name="MS_X0" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 0</doc> + <bitfield high="7" low="4" name="MS_Y0" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 0</doc> + <bitfield high="11" low="8" name="MS_X1" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 1</doc> + <bitfield high="15" low="12" name="MS_Y1" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 1</doc> + <bitfield high="19" low="16" name="MS_X2" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 2</doc> + <bitfield high="23" low="20" name="MS_Y2" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 2</doc> + <bitfield high="27" low="24" name="MSBD0_Y" /> + <doc>Specifies the minimum y distance (in subpixels) between + the pixel edge and the multisample bounding box. This value + is used in the tile scan converter</doc> + <bitfield high="31" low="28" name="MSBD0_X" /> + <doc>msbd0_x[2:0] specifies the minimum x distance (in + subpixels) between the pixel edge and the multisample + bounding box. This value is used in the tile scan converter. + The special case value of 8 is represented by msbd0_x[2:0]=7. + msbd0_x[3] is used to force a bounding box based tile scan + conversion instead of an intercept based one. This value + should always be set to 0.</doc> + </reg32> + <reg32 access="rw" name="GB_MSPOS1" offset="0x4014"> + <doc>Specifies the position of multisamples 3 through 5</doc> + <bitfield high="3" low="0" name="MS_X3" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 3</doc> + <bitfield high="7" low="4" name="MS_Y3" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 3</doc> + <bitfield high="11" low="8" name="MS_X4" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 4</doc> + <bitfield high="15" low="12" name="MS_Y4" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 4</doc> + <bitfield high="19" low="16" name="MS_X5" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 5</doc> + <bitfield high="23" low="20" name="MS_Y5" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 5</doc> + <bitfield high="27" low="24" name="MSBD1" /> + <doc>Specifies the minimum distance (in subpixels) between + the pixel edge and the multisample bounding box. This value + is used in the quad scan converter</doc> + </reg32> + <reg32 access="rw" name="GB_SELECT" offset="0x401C"> + <doc>Specifies various polygon specific selects (fog, depth, + perspective).</doc> + <bitfield high="2" low="0" name="FOG_SELECT"> + <use-enum ref="ENUM59" /> + </bitfield> + <doc>Specifies source for outgoing (GA to SU) fog + value.</doc> + <bitfield high="3" low="3" name="DEPTH_SELECT"> + <use-enum ref="ENUM60" /> + </bitfield> + <doc>Specifies source for outgoing (GA/SU & SU/RAS) depth + value.</doc> + <bitfield high="4" low="4" name="W_SELECT"> + <use-enum ref="ENUM61" /> + </bitfield> + <doc>Specifies source for outgoing (1/W) value, used to + disable perspective correct colors/textures.</doc> + </reg32> + <reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018"> + <doc>Specifies the graphics pipeline configuration for + rasterization</doc> + <bitfield high="0" low="0" name="ENABLE"> + <use-enum ref="ENUM62" /> + </bitfield> + <doc>Enables tiling, otherwise all tiles receive all + polygons.</doc> + <bitfield high="3" low="1" name="PIPE_COUNT"> + <value name="RV350" value="0"> + <doc>RV350</doc> + </value> + <value name="R300" value="3"> + <doc>R300</doc> + </value> + </bitfield> + <doc>Specifies the number of active pipes and contexts.</doc> + <bitfield high="5" low="4" name="TILE_SIZE"> + <value name="8_PIXELS" value="0"> + <doc>8 pixels (not supported by zb/cb)</doc> + </value> + <value name="16_PIXELS" value="1"> + <doc>16 pixels</doc> + </value> + <value name="32_PIXELS" value="2"> + <doc>32 pixels (not supported by zb/cb)</doc> + </value> + </bitfield> + <doc>Specifies width & height (square), in pixels.</doc> + <bitfield high="8" low="6" name="SUPER_SIZE"> + <use-enum ref="ENUM65" /> + </bitfield> + <doc>Specifies number of tiles and config in super chip + configuration.</doc> + <bitfield high="11" low="9" name="SUPER_X" /> + <doc>X Location of chip within super tile.</doc> + <bitfield high="14" low="12" name="SUPER_Y" /> + <doc>Y Location of chip within super tile.</doc> + <bitfield high="15" low="15" name="SUPER_TILE"> + <use-enum ref="ENUM66" /> + </bitfield> + <doc>Tile location of chip in a multi super tile config + (Super size of 2,8,32 or 128).</doc> + <bitfield high="16" low="16" name="SUBPIXEL"> + <use-enum ref="ENUM67" /> + </bitfield> + <doc>Specifies the subpixel precision.</doc> + <bitfield high="18" low="17" name="QUADS_PER_RAS" /> + <doc>unused</doc> + <bitfield high="19" low="19" name="BB_SCAN" /> + <doc>unused</doc> + </reg32> + <reg32 access="rw" name="RS_COUNT" offset="0x4300"> + <doc>This register specifies the rasterizer input packet + configuration</doc> + <bitfield high="6" low="0" name="IT_COUNT" /> + <doc>Specifies the total number of texture address components + contained in the rasterizer input packet (0:32).</doc> + <bitfield high="10" low="7" name="IC_COUNT" /> + <doc>Specifies the total number of colors contained in the + rasterizer input packet (0:4).</doc> + <bitfield high="11" low="11" name="W_COUNT" /> + <doc>Specifies the total number of w values contained in the + rasterizer input packet (0 or 1).</doc> + <bitfield high="17" low="12" name="W_ADDR" /> + <doc>Specifies the relative rasterizer input packet location + of w (if w_count==1)</doc> + <bitfield high="18" low="18" name="HIRES_EN" /> + <doc>Enable high resolution texture coordinate output when q + is equal to 1</doc> + </reg32> + <stripe length="16" offset="0x4330" stride="0x0004"> + <reg32 access="rw" name="RS_INST" offset="0x0"> + <doc>This table specifies what happens during each + rasterizer instruction</doc> + <bitfield high="2" low="0" name="TEX_ID" /> + <doc>Specifies the index (into the RS_IP table) of the + texture address output during this rasterizer + instruction</doc> + <bitfield high="5" low="3" name="TEX_CN"> + <use-enum ref="ENUM68" /> + </bitfield> + <doc>Write enable for texture address</doc> + <bitfield high="10" low="6" name="TEX_ADDR" /> + <doc>Specifies the destination address (within the current + pixel stack frame) of the texture address output during + this rasterizer instruction</doc> + <bitfield high="13" low="11" name="COL_ID" /> + <doc>Specifies the index (into the RS_IP table) of the + color output during this rasterizer instruction</doc> + <bitfield high="16" low="14" name="COL_CN"> + <value name="NO_WRITE" value="0"> + <doc>No write - color not valid</doc> + </value> + <value name="WRITE" value="1"> + <doc>write - color valid</doc> + </value> + </bitfield> + <doc>Write enable for color</doc> + <bitfield high="21" low="17" name="COL_ADDR" /> + <doc>Specifies the destination address (within the current + pixel stack frame) of the color output during this + rasterizer instruction</doc> + <bitfield high="22" low="22" name="TEX_ADJ"> + <use-enum ref="ENUM70" /> + </bitfield> + <doc>Specifies whether to sample texture coordinates at the + real or adjusted pixel centers</doc> + <bitfield high="24" low="23" name="COL_BIAS" /> + <doc>unused</doc> + </reg32> + </stripe> + <reg32 access="rw" name="RS_INST_COUNT" offset="0x4304"> + <doc>This register specifies the number of rasterizer + instructions</doc> + <bitfield high="3" low="0" name="INST_COUNT" /> + <doc>Number of rasterizer instructions (1:16)</doc> + <bitfield high="4" low="4" name="W_EN" /> + <doc>Specifies that the rasterizer needs to generate w</doc> + <bitfield high="7" low="5" name="TX_OFFSET"> + <value name="0" value="0"> + <doc>0.0</doc> + </value> + <value name="RANGE" value="1"> + <doc>range/8K</doc> + </value> + <value name="RANGE" value="2"> + <doc>range/16K</doc> + </value> + <value name="RANGE" value="3"> + <doc>range/32K</doc> + </value> + <value name="RANGE" value="4"> + <doc>range/64K</doc> + </value> + <value name="RANGE" value="5"> + <doc>range/128K</doc> + </value> + <value name="RANGE" value="6"> + <doc>range/256K</doc> + </value> + <value name="RANGE" value="7"> + <doc>range/512K</doc> + </value> + </bitfield> + <doc>Defines texture coordinate offset (based on min/max + coordinate range of triangle) used to minimize or eliminate + peroidic errors on texels sampled right on their edges</doc> + </reg32> + <stripe length="8" offset="0x4310" stride="0x0000"> + <reg32 access="rw" name="RS_IP" offset="0x0"> + <doc>This table specifies the source location and format + for up to 8 texture addresses (i[0]:i[7]) and four colors + (c[0]:c[3])</doc> + <bitfield high="5" low="0" name="TEX_PTR" /> + <doc>Specifies the relative rasterizer input packet + location of texture address (i[i]).</doc> + <bitfield high="8" low="6" name="COL_PTR" /> + <doc>Specifies the relative rasterizer input packet + location of the color (c[i]).</doc> + <bitfield high="12" low="9" name="COL_FMT"> + <use-enum ref="ENUM72" /> + </bitfield> + <doc>Specifies the format of the color (c[i]).</doc> + <bitfield high="15" low="13" name="SEL_S"> + <use-enum ref="ENUM73" /> + </bitfield> + <doc>Source select for S, T, R, and Q</doc> + <bitfield high="18" low="16" name="SEL_T"> + <use-enum ref="ENUM73" /> + </bitfield> + <doc>Source select for S, T, R, and Q</doc> + <bitfield high="21" low="19" name="SEL_R"> + <use-enum ref="ENUM73" /> + </bitfield> + <doc>Source select for S, T, R, and Q</doc> + <bitfield high="24" low="22" name="SEL_Q"> + <use-enum ref="ENUM73" /> + </bitfield> + <doc>Source select for S, T, R, and Q</doc> + </reg32> + </stripe> + <reg32 access="rw" name="SC_EDGERULE" offset="0x43A8"> + <doc>Edge rules - what happens when an edge falls exactly on + a sample point</doc> + <bitfield high="4" low="0" name="ER_TRI"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="9" low="5" name="ER_POINT"> + <use-enum ref="ENUM75" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="14" low="10" name="ER_LINE_LR"> + <use-enum ref="ENUM75" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="19" low="15" name="ER_LINE_RL"> + <use-enum ref="ENUM75" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="24" low="20" name="ER_LINE_TB"> + <use-enum ref="ENUM75" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="29" low="25" name="ER_LINE_BT"> + <use-enum ref="ENUM75" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + </reg32> + <reg32 access="rw" name="SU_REG_DEST" offset="0x42C8"> + <doc>SU Raster pipe destination select for registers</doc> + <bitfield high="3" low="0" name="SELECT"> + <value name="P0_ENABLE" value="0"> + <doc>P0 enable, b</doc> + </value> + <value name="P1_ENABLE" value="3"> + <doc>P1 enable</doc> + </value> + </bitfield> + <doc>Select which of the 2 pipes (enable per pipe) to send + register read/write to. b0: P0 enable, b3: P1 enable</doc> + </reg32> + <reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0"> + <doc>Enables for Cylindrical Wrapping</doc> + <bitfield high="0" low="0" name="T0C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 0 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 0 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="1" low="1" name="T0C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 0 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 0 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="2" low="2" name="T0C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 0 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 0 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="3" low="3" name="T0C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 0 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 0 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="4" low="4" name="T1C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 1 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 1 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="5" low="5" name="T1C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 1 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 1 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="6" low="6" name="T1C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 1 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 1 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="7" low="7" name="T1C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 1 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_1_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 1 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="8" low="8" name="T2C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 2 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 2 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="9" low="9" name="T2C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 2 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 2 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="10" low="10" name="T2C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 2 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 2 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="11" low="11" name="T2C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 2 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_2_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 2 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="12" low="12" name="T3C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 3 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 3 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="13" low="13" name="T3C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 3 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 3 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="14" low="14" name="T3C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 3 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 3 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="15" low="15" name="T3C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 3 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_3_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 3 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="16" low="16" name="T4C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 4 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 4 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="17" low="17" name="T4C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 4 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 4 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="18" low="18" name="T4C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 4 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 4 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="19" low="19" name="T4C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 4 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_4_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 4 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="20" low="20" name="T5C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 5 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 5 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="21" low="21" name="T5C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 5 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 5 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="22" low="22" name="T5C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 5 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 5 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="23" low="23" name="T5C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 5 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_5_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 5 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="24" low="24" name="T6C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 6 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 6 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="25" low="25" name="T6C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 6 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 6 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="26" low="26" name="T6C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 6 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 6 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="27" low="27" name="T6C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 6 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_6_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 6 comp 3.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="28" low="28" name="T7C0"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0" + value="0"> + <doc>Disable cylindrical wrapping for tex 7 comp 0.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_0" + value="1"> + <doc>Enable cylindrical wrapping for tex 7 comp 0.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="29" low="29" name="T7C1"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1" + value="0"> + <doc>Disable cylindrical wrapping for tex 7 comp 1.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_1" + value="1"> + <doc>Enable cylindrical wrapping for tex 7 comp 1.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="30" low="30" name="T7C2"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2" + value="0"> + <doc>Disable cylindrical wrapping for tex 7 comp 2.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_2" + value="1"> + <doc>Enable cylindrical wrapping for tex 7 comp 2.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="31" low="31" name="T7C3"> + <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3" + value="0"> + <doc>Disable cylindrical wrapping for tex 7 comp 3.</doc> + </value> + <value name="ENABLE_CYLINDRICAL_WRAPPING_FOR_TEX_7_COMP_3" + value="1"> + <doc>Enable cylindrical wrapping for tex 7 comp 3.</doc> + </value> + </bitfield> + <doc /> + </reg32> + <stripe length="16" offset="0x45C0" stride="0x0004"> + <reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0"> + <doc>Border Color for Map 0</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4580" stride="0x0004"> + <reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0"> + <doc>Texture Chroma Key for Map 0</doc> + </reg32> + </stripe> + <reg32 access="rw" name="TX_ENABLE" offset="0x4104"> + <doc>Texture Enables for Maps 0 to 15</doc> + <bitfield high="0" low="0" name="TEX_0_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T0(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 0 Enable.</doc> + <bitfield high="1" low="1" name="TEX_1_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T1(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 1 Enable.</doc> + <bitfield high="2" low="2" name="TEX_2_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T2(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 2 Enable.</doc> + <bitfield high="3" low="3" name="TEX_3_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T3(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 3 Enable.</doc> + <bitfield high="4" low="4" name="TEX_4_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T4(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 4 Enable.</doc> + <bitfield high="5" low="5" name="TEX_5_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T5(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 5 Enable.</doc> + <bitfield high="6" low="6" name="TEX_6_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T6(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 6 Enable.</doc> + <bitfield high="7" low="7" name="TEX_7_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T7(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 7 Enable.</doc> + <bitfield high="8" low="8" name="TEX_8_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T8(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 8 Enable.</doc> + <bitfield high="9" low="9" name="TEX_9_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T9(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 9 Enable.</doc> + <bitfield high="10" low="10" name="TEX_10_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T10(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 10 Enable.</doc> + <bitfield high="11" low="11" name="TEX_11_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T11(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 11 Enable.</doc> + <bitfield high="12" low="12" name="TEX_12_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T12(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 12 Enable.</doc> + <bitfield high="13" low="13" name="TEX_13_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T13(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 13 Enable.</doc> + <bitfield high="14" low="14" name="TEX_14_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T14(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 14 Enable.</doc> + <bitfield high="15" low="15" name="TEX_15_ENABLE"> + <value name="DISABLE" value="0"> + <doc>Disable, T15(ARGB) = 1,0,0,0</doc> + </value> + <value name="ENABLE" value="1"> + <doc>Enable</doc> + </value> + </bitfield> + <doc>Texture Map 15 Enable.</doc> + </reg32> + <stripe length="16" offset="0x4400" stride="0x0004"> + <reg32 access="rw" name="TX_FILTER0" offset="0x0"> + <doc>Texture Filter State for Map 0</doc> + <bitfield high="2" low="0" name="CLAMP_S"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for first texture coordinate</doc> + <bitfield high="5" low="3" name="CLAMP_T"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for second texture coordinate</doc> + <bitfield high="8" low="6" name="CLAMP_R"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for third texture coordinate</doc> + <bitfield high="10" low="9" name="MAG_FILTER"> + <use-enum ref="ENUM137" /> + </bitfield> + <doc>Filter used when texture is magnified</doc> + <bitfield high="12" low="11" name="MIN_FILTER"> + <use-enum ref="ENUM137" /> + </bitfield> + <doc>Filter used when texture is minified</doc> + <bitfield high="14" low="13" name="MIP_FILTER"> + <use-enum ref="ENUM138" /> + </bitfield> + <doc>Filter used between mipmap levels</doc> + <bitfield high="16" low="15" name="VOL_FILTER"> + <use-enum ref="ENUM139" /> + </bitfield> + <doc>Filter used between layers of a volume</doc> + <bitfield high="20" low="17" name="MAX_MIP_LEVEL" /> + <doc>LOD index of largest (finest) mipmap to use (0 is + largest). Ranges from 0 to NUM_LEVELS.</doc> + <bitfield high="31" low="28" name="ID" /> + <doc>Logical id for this physical texture</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4440" stride="0x0004"> + <reg32 access="rw" name="TX_FILTER1" offset="0x0"> + <doc>Texture Filter State for Map 0</doc> + <bitfield high="1" low="0" name="CHROMA_KEY_MODE"> + <use-enum ref="ENUM140" /> + </bitfield> + <doc>Chroma Key Mode</doc> + <bitfield high="2" low="2" name="MC_ROUND"> + <use-enum ref="ENUM141" /> + </bitfield> + <doc>Bilinear rounding mode</doc> + <bitfield high="12" low="3" name="LOD_BIAS" /> + <doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias + measured in mipmap levels. Added to the signed, computed + LOD before the LOD is clamped.</doc> + <bitfield high="14" low="14" name="MC_COORD_TRUNCATE"> + <use-enum ref="ENUM142" /> + </bitfield> + <doc>MPEG coordinate truncation mode</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4480" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT0" offset="0x0"> + <doc>Texture Format State for Map 0</doc> + <bitfield high="10" low="0" name="TXWIDTH" /> + <doc>Image width - 1. The largest image is 2048 texels. + When wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power of 2 + in memory. Can always be non-square, except for cube maps + which must be square.</doc> + <bitfield high="21" low="11" name="TXHEIGHT" /> + <doc>Image height - 1. The largest image is 2048 texels. + When wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power of 2 + in memory. Can always be non-square, except for cube maps + which must be square.</doc> + <bitfield high="25" low="22" name="TXDEPTH" /> + <doc>LOG2(depth) of volume texture</doc> + <bitfield high="29" low="26" name="NUM_LEVELS" /> + <doc>Number of mipmap levels minus 1. Ranges from 0 to 11. + Equivalent to LOD index of smallest (coarsest) mipmap to + use.</doc> + <bitfield high="30" low="30" name="PROJECTED"> + <use-enum ref="ENUM143" /> + </bitfield> + <doc>Specifies whether texture coords are projected.</doc> + <bitfield high="31" low="31" name="TXPITCH_EN"> + <use-enum ref="ENUM144" /> + </bitfield> + <doc>Indicates when TXPITCH should be used instead of + TXWIDTH for image addressing</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x44C0" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT1" offset="0x0"> + <doc>Texture Format State for Map 0</doc> + <bitfield high="4" low="0" name="TXFORMAT"> + <value name="TX_FMT_8" value="0"> + <doc>TX_FMT_8</doc> + </value> + <value name="TX_FMT_16" value="1"> + <doc>TX_FMT_16</doc> + </value> + <value name="TX_FMT_4_4" value="2"> + <doc>TX_FMT_4_4</doc> + </value> + <value name="TX_FMT_8_8" value="3"> + <doc>TX_FMT_8_8</doc> + </value> + <value name="TX_FMT_16_16" value="4"> + <doc>TX_FMT_16_16</doc> + </value> + <value name="TX_FMT_3_3_2" value="5"> + <doc>TX_FMT_3_3_2</doc> + </value> + <value name="TX_FMT_5_6_5" value="6"> + <doc>TX_FMT_5_6_5</doc> + </value> + <value name="TX_FMT_6_5_5" value="7"> + <doc>TX_FMT_6_5_5</doc> + </value> + <value name="TX_FMT_11_11_10" value="8"> + <doc>TX_FMT_11_11_10</doc> + </value> + <value name="TX_FMT_10_11_11" value="9"> + <doc>TX_FMT_10_11_11</doc> + </value> + <value name="TX_FMT_4_4_4_4" value="10"> + <doc>TX_FMT_4_4_4_4</doc> + </value> + <value name="TX_FMT_1_5_5_5" value="11"> + <doc>TX_FMT_1_5_5_5</doc> + </value> + <value name="TX_FMT_8_8_8_8" value="12"> + <doc>TX_FMT_8_8_8_8</doc> + </value> + <value name="TX_FMT_2_10_10_10" value="13"> + <doc>TX_FMT_2_10_10_10</doc> + </value> + <value name="TX_FMT_16_16_16_16" value="14"> + <doc>TX_FMT_16_16_16_16</doc> + </value> + <value name="TX_FMT_Y8" value="18"> + <doc>TX_FMT_Y8</doc> + </value> + <value name="TX_FMT_AVYU444" value="19"> + <doc>TX_FMT_AVYU444</doc> + </value> + <value name="TX_FMT_VYUY422" value="20"> + <doc>TX_FMT_VYUY422</doc> + </value> + <value name="TX_FMT_YVYU422" value="21"> + <doc>TX_FMT_YVYU422</doc> + </value> + <value name="TX_FMT_16_MPEG" value="22"> + <doc>TX_FMT_16_MPEG</doc> + </value> + <value name="TX_FMT_16_16_MPEG" value="23"> + <doc>TX_FMT_16_16_MPEG</doc> + </value> + <value name="TX_FMT_16F" value="24"> + <doc>TX_FMT_16f</doc> + </value> + <value name="TX_FMT_16F_16F" value="25"> + <doc>TX_FMT_16f_16f</doc> + </value> + <value name="TX_FMT_16F_16F_16F_16F" value="26"> + <doc>TX_FMT_16f_16f_16f_16f</doc> + </value> + <value name="TX_FMT_32F" value="27"> + <doc>TX_FMT_32f</doc> + </value> + <value name="TX_FMT_32F_32F" value="28"> + <doc>TX_FMT_32f_32f</doc> + </value> + <value name="TX_FMT_32F_32F_32F_32F" value="29"> + <doc>TX_FMT_32f_32f_32f_32f</doc> + </value> + <value name="TX_FMT_W24_FP" value="30"> + <doc>TX_FMT_W24_FP</doc> + </value> + </bitfield> + <doc>Texture Format. Components are numbered right to left. + Parenthesis indicate typical uses of each format.</doc> + <bitfield high="5" low="5" name="SIGNED_COMP0"> + <value name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" + value="0"> + <doc>Component0 filter should interpret texel data as + unsigned</doc> + </value> + <value name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" + value="1"> + <doc>Component0 filter should interpret texel data as + signed</doc> + </value> + </bitfield> + <doc>Component0 filter should interpret texel data as + signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="6" low="6" name="SIGNED_COMP1"> + <value name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" + value="0"> + <doc>Component1 filter should interpret texel data as + unsigned</doc> + </value> + <value name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" + value="1"> + <doc>Component1 filter should interpret texel data as + signed</doc> + </value> + </bitfield> + <doc>Component1 filter should interpret texel data as + signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="7" low="7" name="SIGNED_COMP2"> + <value name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" + value="0"> + <doc>Component2 filter should interpret texel data as + unsigned</doc> + </value> + <value name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" + value="1"> + <doc>Component2 filter should interpret texel data as + signed</doc> + </value> + </bitfield> + <doc>Component2 filter should interpret texel data as + signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="8" low="8" name="SIGNED_COMP3"> + <value name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED" + value="0"> + <doc>Component3 filter should interpret texel data as + unsigned</doc> + </value> + <value name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED" + value="1"> + <doc>Component3 filter should interpret texel data as + signed</doc> + </value> + </bitfield> + <doc>Component3 filter should interpret texel data as + signed or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="11" low="9" name="SEL_ALPHA"> + <value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_ALPHA_CHANNEL" + value="0"> + <doc>Select Texture Component0 for the Alpha + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_ALPHA_CHANNEL" + value="1"> + <doc>Select Texture Component1 for the Alpha + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_ALPHA_CHANNEL" + value="2"> + <doc>Select Texture Component2 for the Alpha + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_ALPHA_CHANNEL" + value="3"> + <doc>Select Texture Component3 for the Alpha + Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_0_FOR_THE_ALPHA_CHANNEL" + value="4"> + <doc>Select the value 0 for the Alpha Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_1_FOR_THE_ALPHA_CHANNEL" + value="5"> + <doc>Select the value 1 for the Alpha Channel.</doc> + </value> + </bitfield> + <doc>Specifies swizzling for alpha channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="14" low="12" name="SEL_RED"> + <value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_RED_CHANNEL" + value="0"> + <doc>Select Texture Component0 for the Red + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_RED_CHANNEL" + value="1"> + <doc>Select Texture Component1 for the Red + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_RED_CHANNEL" + value="2"> + <doc>Select Texture Component2 for the Red + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_RED_CHANNEL" + value="3"> + <doc>Select Texture Component3 for the Red + Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_0_FOR_THE_RED_CHANNEL" + value="4"> + <doc>Select the value 0 for the Red Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_1_FOR_THE_RED_CHANNEL" + value="5"> + <doc>Select the value 1 for the Red Channel.</doc> + </value> + </bitfield> + <doc>Specifies swizzling for red channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="17" low="15" name="SEL_GREEN"> + <value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_GREEN_CHANNEL" + value="0"> + <doc>Select Texture Component0 for the Green + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_GREEN_CHANNEL" + value="1"> + <doc>Select Texture Component1 for the Green + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_GREEN_CHANNEL" + value="2"> + <doc>Select Texture Component2 for the Green + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_GREEN_CHANNEL" + value="3"> + <doc>Select Texture Component3 for the Green + Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_0_FOR_THE_GREEN_CHANNEL" + value="4"> + <doc>Select the value 0 for the Green Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_1_FOR_THE_GREEN_CHANNEL" + value="5"> + <doc>Select the value 1 for the Green Channel.</doc> + </value> + </bitfield> + <doc>Specifies swizzling for green channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="20" low="18" name="SEL_BLUE"> + <value name="SELECT_TEXTURE_COMPONENT0_FOR_THE_BLUE_CHANNEL" + value="0"> + <doc>Select Texture Component0 for the Blue + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1_FOR_THE_BLUE_CHANNEL" + value="1"> + <doc>Select Texture Component1 for the Blue + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2_FOR_THE_BLUE_CHANNEL" + value="2"> + <doc>Select Texture Component2 for the Blue + Channel.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3_FOR_THE_BLUE_CHANNEL" + value="3"> + <doc>Select Texture Component3 for the Blue + Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_0_FOR_THE_BLUE_CHANNEL" + value="4"> + <doc>Select the value 0 for the Blue Channel.</doc> + </value> + <value name="SELECT_THE_VALUE_1_FOR_THE_BLUE_CHANNEL" + value="5"> + <doc>Select the value 1 for the Blue Channel.</doc> + </value> + </bitfield> + <doc>Specifies swizzling for blue channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="21" low="21" name="GAMMA"> + <use-enum ref="ENUM154" /> + </bitfield> + <doc>Optionally remove gamma from texture before passing to + shader. Only apply to 8bit or less components.</doc> + <bitfield high="23" low="22" name="YUV_TO_RGB"> + <use-enum ref="ENUM155" /> + </bitfield> + <doc>YUV to RGB conversion mode</doc> + <bitfield high="24" low="24" name="SWAP_YUV"> + <use-enum ref="ENUM156" /> + </bitfield> + <doc /> + <bitfield high="26" low="25" name="TEX_COORD_TYPE"> + <use-enum ref="ENUM157" /> + </bitfield> + <doc>Specifies coordinate type.</doc> + <bitfield high="31" low="27" name="CACHE"> + <use-enum ref="ENUM158" /> + </bitfield> + <doc>Multi-texture performance can be optimized and made + deterministic by assigning textures to separate regions + under sw control.</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4500" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT2" offset="0x0"> + <doc>Texture Format State for Map 0</doc> + <bitfield high="13" low="0" name="TXPITCH" /> + <doc>Used instead of TXWIDTH for image addressing when + TXPITCH_EN is asserted. Pitch is given as number of texels + minus one. Maximum pitch is 16K texels.</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4540" stride="0x0004"> + <reg32 access="rw" name="TX_OFFSET" offset="0x0"> + <doc>Texture Offset State for Map 0</doc> + <bitfield high="1" low="0" name="ENDIAN_SWAP"> + <use-enum ref="ENUM159" /> + </bitfield> + <doc>Endian Control</doc> + <bitfield high="2" low="2" name="MACRO_TILE"> + <use-enum ref="ENUM160" /> + </bitfield> + <doc>Macro Tile Control</doc> + <bitfield high="4" low="3" name="MICRO_TILE"> + <use-enum ref="ENUM161" /> + </bitfield> + <doc>Micro Tile Control</doc> + <bitfield high="31" low="5" name="TXOFFSET" /> + <doc>32-byte aligned pointer to base map</doc> + </reg32> + </stripe> + <stripe length="64" offset="0x47C0" stride="0x0004"> + <reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0"> + <doc>This table specifies the Alpha source addresses for up + to 64 ALU instruction. The ALU expects 6 source operands - + three for color (rgb0, rgb1, rgb2) and three for alpha (a0, + a1, a2).</doc> + <bitfield high="5" low="0" name="ADDR0" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="11" low="6" name="ADDR1" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="17" low="12" name="ADDR2" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="22" low="18" name="ADDRD" /> + <doc>Specifies the address of the pixel stack frame + register to which the Alpha result of this instruction is + to be written.</doc> + <bitfield high="23" low="23" name="WMASK"> + <value name="NONE" value="0"> + <doc>NONE: No not write register.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only.</doc> + </value> + </bitfield> + <doc>Specifies whether or not to write the Alpha component + of the result for this instruction to the pixel stack + frame.</doc> + <bitfield high="24" low="24" name="OMASK"> + <value name="NONE" value="0"> + <doc>NONE: No not write output.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only.</doc> + </value> + </bitfield> + <doc>Specifies whether or not to write the Alpha component + of the result of this instruction to the output fifo.</doc> + <bitfield high="26" low="25" name="TARGET"> + <use-enum ref="ENUM164" /> + </bitfield> + <doc>Specifies which frame buffer target to write to.</doc> + <bitfield high="27" low="27" name="OMASK_W"> + <value name="NONE" value="0"> + <doc>NONE: No not write output to w.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only.</doc> + </value> + </bitfield> + <doc>Specifies whether or not to write the Alpha component + of the result of this instuction to the depth output + fifo.</doc> + <bitfield high="31" low="28" name="STAT_WE" /> + <doc>Specifies which components (R,G,B,A) contribute to the + stat count (see performance counter field in + US_CONFIG).</doc> + </reg32> + </stripe> + <stripe length="64" offset="0x49C0" stride="0x0004"> + <reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0"> + <doc>ALU Alpha Instruction</doc> + <bitfield high="4" low="0" name="SEL_A"> + <use-enum ref="ENUM166" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="6" low="5" name="MOD_A"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="11" low="7" name="SEL_B"> + <use-enum ref="ENUM166" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="13" low="12" name="MOD_B"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="18" low="14" name="SEL_C"> + <use-enum ref="ENUM166" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="20" low="19" name="MOD_C"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="22" low="21" name="SRCP_OP"> + <use-enum ref="ENUM168" /> + </bitfield> + <doc>Specifies how the pre-subtract value (SRCP) is + computed</doc> + <bitfield high="26" low="23" name="OP"> + <value name="OP_MAD" value="0"> + <doc>OP_MAD: Result = A*B + C</doc> + </value> + <value name="OP_DP" value="1"> + <doc>OP_DP: Result = dot product from RGB ALU</doc> + </value> + <value name="OP_MIN" value="2"> + <doc>OP_MIN: Result = min(A,B)</doc> + </value> + <value name="OP_MAX" value="3"> + <doc>OP_MAX: Result = max(A,B)</doc> + </value> + <value name="OP_CND" value="5"> + <doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> + </value> + <value name="OP_CMP" value="6"> + <doc>OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B</doc> + </value> + <value name="OP_FRC" value="7"> + <doc>OP_FRC: Result = fractional(A)</doc> + </value> + <value name="OP_EX" value="8"> + <doc>OP_EX</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result = 2^^A</doc> + </value> + <value name="OP_LN" value="9"> + <doc>OP_LN</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result = log2(A)</doc> + </value> + <value name="OP_RCP" value="10"> + <doc>OP_RCP: Result = 1/A</doc> + </value> + <value name="OP_RSQ" value="11"> + <doc>OP_RSQ: Result = 1/sqrt(A)</doc> + </value> + </bitfield> + <doc>Specifies the operand for this instruction.</doc> + <bitfield high="29" low="27" name="OMOD"> + <use-enum ref="ENUM170" /> + </bitfield> + <doc>Specifies the output modifier for this + instruction.</doc> + <bitfield high="30" low="30" name="CLAMP"> + <use-enum ref="ENUM171" /> + </bitfield> + <doc>Specifies clamp mode for this instruction.</doc> + </reg32> + </stripe> + <stripe length="64" offset="0x46C0" stride="0x0004"> + <reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0"> + <doc>This table specifies the RGB source and destination + addresses for up to 64 ALU instructions. The ALU expects 6 + source operands - three for color (rgb0, rgb1, rgb2) and + three for alpha (a0, a1, a2).</doc> + <bitfield high="5" low="0" name="ADDR0" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="11" low="6" name="ADDR1" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="17" low="12" name="ADDR2" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. Values 0 through 31 specify a location within the + current pixel stack frame. Values 32 through 63 specify a + constant.</doc> + <bitfield high="22" low="18" name="ADDRD" /> + <doc>Specifies the address of the pixel stack frame + register to which the RGB result of this instruction is to + be written.</doc> + <bitfield high="25" low="23" name="WMASK"> + <use-enum ref="ENUM172" /> + </bitfield> + <doc>Specifies which of the R, G, and B components of the + result of this instruction are written to the pixel stack + frame.</doc> + <bitfield high="28" low="26" name="OMASK"> + <use-enum ref="ENUM172" /> + </bitfield> + <doc>Specifies which of the R, G, and B components of the + result of this instruction are written to the output + fifo.</doc> + <bitfield high="30" low="29" name="TARGET"> + <use-enum ref="ENUM164" /> + </bitfield> + <doc>Specifies which frame buffer target to write to.</doc> + </reg32> + </stripe> + <stripe length="64" offset="0x48C0" stride="0x0004"> + <reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0"> + <doc>ALU RGB Instruction</doc> + <bitfield high="4" low="0" name="SEL_A"> + <use-enum ref="ENUM173" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="6" low="5" name="MOD_A"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="11" low="7" name="SEL_B"> + <use-enum ref="ENUM173" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="13" low="12" name="MOD_B"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="18" low="14" name="SEL_C"> + <use-enum ref="ENUM173" /> + </bitfield> + <doc>Specifies the operand and component select for inputs + A, B, and C.</doc> + <bitfield high="20" low="19" name="MOD_C"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the modifier for inputs A, B, and C.</doc> + <bitfield high="22" low="21" name="SRCP_OP"> + <use-enum ref="ENUM174" /> + </bitfield> + <doc>Specifies how the pre-subtract value (SRCP) is + computed</doc> + <bitfield high="26" low="23" name="OP"> + <value name="OP_MAD" value="0"> + <doc>OP_MAD: Result = A*B + C</doc> + </value> + <value name="OP_DP" value="1"> + <doc>OP_DP</doc> + </value> + <value name="RESULT" value="3"> + <doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc> + </value> + <value name="OP_DP" value="2"> + <doc>OP_DP</doc> + </value> + <value name="RESULT" value="4"> + <doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + + A.a*B.a</doc> + </value> + <value name="OP_D2A" value="3"> + <doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc> + </value> + <value name="OP_MIN" value="4"> + <doc>OP_MIN: Result = min(A,B)</doc> + </value> + <value name="OP_MAX" value="5"> + <doc>OP_MAX: Result = max(A,B)</doc> + </value> + <value name="OP_CND" value="7"> + <doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> + </value> + <value name="OP_CMP" value="8"> + <doc>OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B</doc> + </value> + <value name="OP_FRC" value="9"> + <doc>OP_FRC: Result = frac(A)</doc> + </value> + <value name="OP_SOP" value="10"> + <doc>OP_SOP: Result = ex2,ln2,rcp,rsq from Alpha + ALU</doc> + </value> + </bitfield> + <doc>Specifies the operand for this instruction.</doc> + <bitfield high="29" low="27" name="OMOD"> + <use-enum ref="ENUM170" /> + </bitfield> + <doc>Specifies the output modifier for this + instruction.</doc> + <bitfield high="30" low="30" name="CLAMP"> + <use-enum ref="ENUM171" /> + </bitfield> + <doc>Specifies clamp mode for this instruction.</doc> + <bitfield high="31" low="31" name="NOP"> + <value name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE" + value="0"> + <doc>Do not insert NOP instruction after this one</doc> + </value> + <value name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE" + value="1"> + <doc>Insert a NOP instruction after this one</doc> + </value> + </bitfield> + <doc>Specifies whether to insert a NOP instruction after + this. This would get specified in order to meet dependency + requirements for the pre-subtract inputs.</doc> + </reg32> + </stripe> + <stripe length="4" offset="0x4610" stride="0x0004"> + <reg32 access="rw" name="US_CODE_ADDR" offset="0x0"> + <doc>Code Address for Indirection Levels 0 to 3</doc> + <bitfield high="5" low="0" name="ALU_START" /> + <doc>Specifies the start address of the ALU microcode + segment associated with the current indirection level + (0:63)</doc> + <bitfield high="11" low="6" name="ALU_SIZE" /> + <doc>Specifies the size of the ALU microcode segment + associated with the current indirection level (1:64)</doc> + <bitfield high="16" low="12" name="TEX_START" /> + <doc>Specifies the start address of the texture microcode + segment associated with the current indirection level + (0:31)</doc> + <bitfield high="21" low="17" name="TEX_SIZE" /> + <doc>Specifies the size of the texture microcode segment + associated with the current indirection level (1:32)</doc> + <bitfield high="22" low="22" name="RGBA_OUT" /> + <doc>Indicates at least one RGBA output instruction at this + level</doc> + <bitfield high="23" low="23" name="W_OUT" /> + <doc>Indicates at least one W output instruction at this + level</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_CODE_OFFSET" offset="0x4608"> + <doc>Specifies the offset and size for the ALU and Texture + micrcode. These values are used to support relocatable code, + and to support register writes to the code store without + requiring a pipeline flush.</doc> + <bitfield high="5" low="0" name="ALU_OFFSET" /> + <doc>Specifies the offset for the ALU code. This value is + added to the ALU_START field in the US_CODE_ADDR registers + (0:63)</doc> + <bitfield high="12" low="6" name="ALU_SIZE" /> + <doc>Specifies the total size for the ALU code for all levels + (0:64)</doc> + <bitfield high="17" low="13" name="TEX_OFFSET" /> + <doc>Specifies the offset for the Texture code. This value is + added to the TEX_START field in the US_CODE_ADDR registers + (0:31)</doc> + <bitfield high="23" low="18" name="TEX_SIZE" /> + <doc>Specifies the total size for the Texture code for all + levels (0:32)</doc> + </reg32> + <reg32 access="rw" name="US_CONFIG" offset="0x4600"> + <doc>Shader Configuration</doc> + <bitfield high="2" low="0" name="NLEVEL"> + <value name="LEVEL_3_ONLY" value="0"> + <doc>Level 3 only (normal DX7-style texturing)</doc> + </value> + <value name="LEVELS_2_AND_3" value="1"> + <doc>Levels 2 and 3 (DX8-style bump mapping)</doc> + </value> + <value name="LEVELS_1" value="2"> + <doc>Levels 1, 2, and 3</doc> + </value> + <value name="LEVELS_0" value="3"> + <doc>Levels 0, 1, 2, and 3</doc> + </value> + </bitfield> + <doc>Specifies the valid indirection levels.</doc> + <bitfield high="3" low="3" name="FIRST_TEX"> + <use-enum ref="ENUM178" /> + </bitfield> + <doc>Specifies whether or not the texture code for the first + valid level is enabled</doc> + </reg32> + <stripe length="4" offset="0x46A4" stride="0x0004"> + <reg32 access="rw" name="US_OUT_FMT" offset="0x0"> + <doc>Specifies how the shader output is written to the fog + unit for each of up to four render targets</doc> + <bitfield high="4" low="0" name="OUT_FMT"> + <use-enum ref="ENUM179" /> + </bitfield> + <doc>Specifies the number and size of components</doc> + <bitfield high="9" low="8" name="C0_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc>Specifies the source for components C0, C1, C2, + C3</doc> + <bitfield high="11" low="10" name="C1_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc>Specifies the source for components C0, C1, C2, + C3</doc> + <bitfield high="13" low="12" name="C2_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc>Specifies the source for components C0, C1, C2, + C3</doc> + <bitfield high="15" low="14" name="C3_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc>Specifies the source for components C0, C1, C2, + C3</doc> + <bitfield high="19" low="16" name="OUT_SIGN" /> + <doc>Mask specifying whether components C3, C2, C1 and C0 + are signed (C4_8, C_16, C2_16 and C4_16 formats only)</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_PIXSIZE" offset="0x4604"> + <doc>Shader pixel size. This register specifies the size and + partitioning of the current pixel stack frame</doc> + <bitfield high="4" low="0" name="PIX_SIZE" /> + <doc>Specifies the total size of the current pixel stack + frame (1:32)</doc> + </reg32> + <stripe length="32" offset="0x4620" stride="0x0004"> + <reg32 access="rw" name="US_TEX_INST" offset="0x0"> + <doc>Texture Instruction</doc> + <bitfield high="4" low="0" name="SRC_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the texture address for this instruction</doc> + <bitfield high="10" low="6" name="DST_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the returned texture data for this + instruction</doc> + <bitfield high="14" low="11" name="TEX_ID" /> + <doc>Specifies the id of the texture map used for this + instruction</doc> + <bitfield high="17" low="15" name="INST"> + <value name="NOP" value="0"> + <doc>NOP: Do nothing</doc> + </value> + <value name="LD" value="1"> + <doc>LD: Do Texture Lookup (S,T,R)</doc> + </value> + <value name="TEXKILL" value="2"> + <doc>TEXKILL: Kill pixel if any component is < + 0</doc> + </value> + <value name="PROJ" value="3"> + <doc>PROJ: Do projected texture lookup + (S/Q,T/Q,R/Q)</doc> + </value> + <value name="LODBIAS" value="4"> + <doc>LODBIAS: Do texture lookup with lod bias</doc> + </value> + </bitfield> + <doc>Specifies the operation taking place for this + instruction</doc> + <bitfield high="18" low="18" name="OMOD" /> + <doc>unused</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_W_FMT" offset="0x46B4"> + <doc>Specifies the source and format for the Depth (W) value + output by the shader</doc> + <bitfield high="1" low="0" name="W_FMT"> + <value name="W" value="0"> + <doc>W</doc> + </value> + <value name="W_IS_ALWAYS_ZERO" value="0"> + <doc>W is always zero</doc> + </value> + <value name="W" value="1"> + <doc>W</doc> + </value> + <value name="24" value="24"> + <doc>24-bit fixed point</doc> + </value> + <value name="W24_FP" value="2"> + <doc>W24_FP - 24-bit floating point</doc> + </value> + </bitfield> + <doc>Format for W</doc> + <bitfield high="2" low="2" name="W_SRC"> + <use-enum ref="ENUM183" /> + </bitfield> + <doc>Source for W</doc> + </reg32> + <stripe length="32" offset="0x4C0C" stride="0x0010"> + <reg32 access="rw" name="US_ALU_CONST_A" offset="0x0"> + <doc>Shader Constant Color 0 Alpha Component</doc> + <bitfield high="23" low="0" name="KA" /> + <doc>Specifies the alpha component; (S16E7) fixed + format.</doc> + </reg32> + </stripe> + <stripe length="32" offset="0x4C08" stride="0x0010"> + <reg32 access="rw" name="US_ALU_CONST_B" offset="0x0"> + <doc>Shader Constant Color 0 Blue Component</doc> + <bitfield high="23" low="0" name="KB" /> + <doc>Specifies the blue component; (S16E7) fixed + format.</doc> + </reg32> + </stripe> + <stripe length="32" offset="0x4C04" stride="0x0010"> + <reg32 access="rw" name="US_ALU_CONST_G" offset="0x0"> + <doc>Shader Constant Color 0 Green Component</doc> + <bitfield high="23" low="0" name="KG" /> + <doc>Specifies the green component; (S16E7) fixed + format.</doc> + </reg32> + </stripe> + <stripe length="32" offset="0x4C00" stride="0x0010"> + <reg32 access="rw" name="US_ALU_CONST_R" offset="0x0"> + <doc>Shader Constant Color 0 Red Component</doc> + <bitfield high="23" low="0" name="KR" /> + <doc>Specifies the red component; (S16E7) fixed + format.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C"> + <doc>Control Bits for User Clip Planes and Clipping</doc> + <bitfield high="0" low="0" name="UCP_ENA_0" /> + <doc>Enable User Clip Plane 0</doc> + <bitfield high="1" low="1" name="UCP_ENA_1" /> + <doc>Enable User Clip Plane 1</doc> + <bitfield high="2" low="2" name="UCP_ENA_2" /> + <doc>Enable User Clip Plane 2</doc> + <bitfield high="3" low="3" name="UCP_ENA_3" /> + <doc>Enable User Clip Plane 3</doc> + <bitfield high="4" low="4" name="UCP_ENA_4" /> + <doc>Enable User Clip Plane 4</doc> + <bitfield high="5" low="5" name="UCP_ENA_5" /> + <doc>Enable User Clip Plane 5</doc> + <bitfield high="15" low="14" name="PS_UCP_MODE" /> + <doc>0 = Cull using distance from center of point 1 = Cull + using radius-based distance from center of point 2 = Cull + using radius-based distance from center of point, Expand and + Clip on intersection 3 = Always expand and clip as + trifan</doc> + <bitfield high="16" low="16" name="CLIP_DISABLE" /> + <doc>Disables clip code generation and clipping process for + TCL</doc> + <bitfield high="17" low="17" name="UCP_CULL_ONLY_ENA" /> + <doc>Cull Primitives against UCPS, but don`t clip</doc> + <bitfield high="18" low="18" name="BOUNDARY_EDGE_FLAG_ENA" /> + <doc>If set, boundary edges are highlighted, else they are + not highlighted</doc> + </reg32> + <reg32 access="rw" name="VAP_CNTL" offset="0x2080"> + <doc>Vertex Assembler/Processor Control Register</doc> + <bitfield high="3" low="0" name="PVS_NUM_SLOTS" /> + <doc>Specifies the number of vertex slots to be used in the + VAP PVS process. A slot represents a single vertex storage + location1 across multiple engines (one vertex per engine). By + decreasing the number of slots, there is more memory for each + vertex, but less parallel processing. Similarly, by + increasing the number of slots, thre is less memory per + vertex but more vertices being processed in parallel.</doc> + <bitfield high="7" low="4" name="PVS_NUM_CNTLRS" /> + <doc>Specifies the maximum number of controllers to be + processing in parallel. In general should be set to max value + of TBD. Can be changed for performance analysis.</doc> + <bitfield high="11" low="8" name="PVS_NUM_FPUS" /> + <doc>Specifies the number of Floating Point Units + (Vector/Math Engines) to use when processing vertices.</doc> + <bitfield high="21" low="18" name="VF_MAX_VTX_NUM" /> + <doc>This field controls the number of vertices that the + vertex fetcher manages for the TCL and Setup Vertex Storage + memories (and therefore the number of vertices that can be + re-used). This value should be set to 12 for most operation, + This number may be modified for performance evaluation. The + value is the maximum vertex number used which is one less + than the number of vertices (i.e. a 12 means 13 vertices will + be used)</doc> + <bitfield high="22" low="22" name="DX_CLIP_SPACE_DEF"> + <use-enum ref="ENUM184" /> + </bitfield> + <doc>Clip space is defined as:</doc> + </reg32> + <reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140"> + <doc>Vertex Assemblen/Processor Control Status</doc> + <bitfield high="1" low="0" name="VC_SWAP" /> + <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: + 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD + becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes + 0xCCDDAABB Default = 0</doc> + <bitfield high="8" low="8" name="PVS_BYPASS" /> + <doc>The TCL engine is logically or physically removed from + the circuit.</doc> + <bitfield high="11" low="11" name="PVS_BUSY" /> + <doc>Transform/Clip/Light (TCL) Engine is Busy. + Read-only.</doc> + <bitfield high="24" low="24" name="VS_BUSY" /> + <doc>Vertex Store is Busy. Read-only.</doc> + <bitfield high="25" low="25" name="RCP_BUSY" /> + <doc>Reciprocal Engine is Busy. Read-only.</doc> + <bitfield high="26" low="26" name="VTE_BUSY" /> + <doc>ViewPort Transform Engine is Busy. Read-only.</doc> + <bitfield high="27" low="27" name="MIU_BUSY" /> + <doc>Memory Interface Unit is Busy. Read-only.</doc> + <bitfield high="28" low="28" name="VC_BUSY" /> + <doc>Vertex Cache is Busy. Read-only.</doc> + <bitfield high="29" low="29" name="VF_BUSY" /> + <doc>Vertex Fetcher is Busy. Read-only.</doc> + <bitfield high="30" low="30" name="REGPIPE_BUSY" /> + <doc>Register Pipeline is Busy. Read-only.</doc> + <bitfield high="31" low="31" name="VAP_BUSY" /> + <doc>VAP Engine is Busy. Read-only.</doc> + </reg32> + <stripe length="8" offset="0x2150" stride="0x0004"> + <reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0"> + <doc>Programmable Stream Control Word 0</doc> + <bitfield high="3" low="0" name="DATA_TYPE_0" /> + <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE + Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE + Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 + 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = + [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except + has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y + = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD + with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], + Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per + dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 + [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT + * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y + = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 + DWORD with 2 11-bit and 1 10-bit fixed point values) (X = + [10:0], Y = [21:11], Z = [31:22], W = 1.0) * These data + types use the SIGNED and NORMALIZE flags described + below.</doc> + <bitfield high="7" low="4" name="SKIP_DWORDS_0" /> + <doc>The number of DWORDS to skip (discard) after + processing the current element.</doc> + <bitfield high="12" low="8" name="DST_VEC_LOC_0" /> + <doc>The vector address in the input memory to write this + element</doc> + <bitfield high="13" low="13" name="LAST_VEC_0" /> + <doc>If set, indicates the last vector of the current + vertex stream</doc> + <bitfield high="14" low="14" name="SIGNED_0" /> + <doc>Determines whether fixed point data types are unsigned + (0) or 2`s complement signed (1) data types. See NORMALIZE + for complete description of affect</doc> + <bitfield high="15" low="15" name="NORMALIZE_0"> + <use-enum ref="ENUM185" /> + </bitfield> + <doc>Determines whether the fixed to floating point + conversion will normalize the value (i.e. fixed point value + is all fractional bits) or not (i.e. fixed point value is + all integer bits). This table describes the fixed to float + conversion results SIGNED NORMALIZE FLT RANGE 0 0 0.0 - + (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 0.0 - 1.0 1 0 + -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - 127.0) + 1 1 -1.0 - 1.0 where n is the number of bits in the + associated fixed point value For signed, normalize + conversion, since the fixed point range is not evenly + distributed around 0, there are 3 different methods + supported by R300. See the VAP_PSC_SGN_NORM_CNTL + description for details.</doc> + <bitfield high="23" low="20" name="SKIP_DWORDS_1" /> + <doc>See SKIP_DWORDS_0</doc> + <bitfield high="28" low="24" name="DST_VEC_LOC_1" /> + <doc>See DST_VEC_LOC_0</doc> + <bitfield high="29" low="29" name="LAST_VEC_1" /> + <doc>See LAST_VEC_0</doc> + <bitfield high="30" low="30" name="SIGNED_1" /> + <doc>See SIGNED_0</doc> + <bitfield high="31" low="31" name="NORMALIZE_1" /> + <doc>See NORMALIZE_0</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x2290" stride="0x0004"> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" + offset="0x0"> + <doc>Programmable Vertex Shader Flow Control Loop Index + Register 0</doc> + <bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" /> + <doc>This field stores the automatic loop index register + init value. This is an 8-bit unsigned value 0-255. This + field is only used if the corresponding control flow + instruction is a loop.</doc> + <bitfield high="15" low="8" + name="PVS_FC_LOOP_STEP_VAL_0" /> + <doc>This field stores the automatic loop index register + step value. This is an 8-bit 2`s comp signed value + -128-127. This field is only used if the corresponding + control flow instruction is a loop.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084"> + <doc>Vertex Fetcher Control</doc> + <bitfield high="3" low="0" name="PRIM_TYPE" /> + <doc>Primitive Type 0 : None (will not trigger Setup Engine + to run) 1 : Point List 2 : Line List 3 : Line Strip 4 : + Triangle List 5 : Triangle Fan 6 : Triangle Strip 7 : + Triangle with wFlags (aka, Rage128 `Type-2` triangles) * 8-11 + : Unused 12 : Line Loop 13 : Quad List 14 : Quad Strip 15 : + Polygon *Encoding 7 indicates whether a 16-bit word of wFlags + is present in the stream of indices arriving when the + VTX_AMODE is programmed as a `0`. The Setup Engine just steps + over the wFlags word; ignoring it. 0 = Stream contains just + indices, as: [ Index1, Index0] [ Index3, Index2] [ Index5, + Index4 ] etc... 1 = Stream contains indices and wFlags: [ + Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ + wFlags, Index5 ] etc...</doc> + <bitfield high="5" low="4" name="PRIM_WALK" /> + <doc>Method of Passing Vertex Data. 0 : State-Based Vertex + Data. (Vertex data and tokens embedded in command stream.) 1 + = Indexes (Indices embedded in command stream; vertex data to + be fetched from memory.) 2 = Vertex List (Vertex data to be + fetched from memory.) 3 = Vertex Data (Vertex data embedded + in command stream.)</doc> + <bitfield high="11" low="11" name="INDEX_SIZE" /> + <doc>When set, vertex indices are 32-bits/indx, otherwise, + 16- bits/indx.</doc> + <bitfield high="12" low="12" name="VTX_REUSE_DIS" /> + <doc>When set, vertex reuse is disabled. DO NOT SET unless + PRIM_WALK is Indexes.</doc> + <bitfield high="13" low="13" name="DUAL_INDEX_MODE" /> + <doc>When set, the incoming index is treated as two separate + indices. Bits 23-16 are used as the index for AOS 0 (These + are 0 for 16-bit indices) Bits 15-0 are used as the index for + AOS 1-15. This mode was added specifically for HOS + usage</doc> + <bitfield high="31" low="16" name="NUM_VERTICES" /> + <doc>Number of vertices in the command packet.</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0"> + <doc>Vertex Array of Structures Control</doc> + <bitfield high="4" low="0" name="VTX_NUM_ARRAYS" /> + <doc>The number of arrays required to represent the current + vertex type. Each Array is described by the following three + fields: VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> + <bitfield high="5" low="5" name="VC_FORCE_PREFETCH" /> + <doc>Force Vertex Data Pre-fetching. If this bit is set, then + a 256-bit word will always be fetched, regardless of which + dwords are needed. Typically useful when + VAP_VF_CNTL.PRIM_WALK is set to Vertex List (Auto-incremented + indices).</doc> + <bitfield high="16" low="16" name="AOS_0_FETCH_SIZE" /> + <doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule + size 1 = 256-bit granule size This allows the driver to + program the fetch size based on DWORDS/VTX/AOS combined with + AGP vs. LOC Memory. The general belief is that the granule + size should always be 256-bits for LOC memory and AGP8X data, + but should be 128-bit for AGP2X/4X data if the DWORDS/VTX/AOS + is less than TBD (128?) bits.</doc> + <bitfield high="17" low="17" name="AOS_1_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="18" low="18" name="AOS_2_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="19" low="19" name="AOS_3_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="20" low="20" name="AOS_4_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="21" low="21" name="AOS_5_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="22" low="22" name="AOS_6_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="23" low="23" name="AOS_7_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="24" low="24" name="AOS_8_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="25" low="25" name="AOS_9_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="26" low="26" name="AOS_10_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="27" low="27" name="AOS_11_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="28" low="28" name="AOS_12_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="29" low="29" name="AOS_13_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180"> + <doc>VAP Vertex State Control Register</doc> + <bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="3" low="2" name="COLOR_1_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 1 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="5" low="4" name="COLOR_2_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 2 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="7" low="6" name="COLOR_3_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 3 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="9" low="8" name="COLOR_4_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 4 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="11" low="10" name="COLOR_5_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 5 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="13" low="12" name="COLOR_6_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 6 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="15" low="14" name="COLOR_7_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 7 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="16" low="16" + name="UPDATE_USER_COLOR_0_ENA" /> + <doc>0 : User Color 0 State is NOT updated when User Color 0 + is written. 1 : User Color 1 State IS updated when User Color + 0 is written.</doc> + <bitfield high="18" low="18" name="USE_ADDR_IND_TBL" /> + <doc>0 : Use vertex state addresses directly to write to + vertex state memory. 1 : Use Address Indirection table to + write to vertex state memory for lower 64 DWORD + addresses.</doc> + </reg32> + <stripe length="4" offset="0x2430" stride="0x0004"> + <reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x232C" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x2328" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x2324" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x2470" stride="0x0004"> + <reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x2320" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0" /> + </stripe> + <reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" + offset="0x2424" /> + <reg32 access="rw" name="VAP_VTX_ST_EDGE_FLAGS" + offset="0x245C" /> + <reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" + offset="0x24AC" /> + <reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" + offset="0x2498" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" + offset="0x2310" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" + offset="0x2314" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" + offset="0x2318" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" + offset="0x2450" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" + offset="0x2454" /> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" + offset="0x2458" /> + <reg32 access="rw" name="VAP_VTX_ST_PNT_SPRT_SZ" + offset="0x2420" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" + offset="0x230C" /> + <reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" + offset="0x2490" /> + <reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" + offset="0x24A0" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" + offset="0x2300" /> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" + offset="0x2494" /> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" + offset="0x24A4" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" + offset="0x2304" /> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" + offset="0x24A8" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" + offset="0x2308" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444" /> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448" /> + <reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C" /> + <reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" + offset="0x2428" /> + <reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" + offset="0x242C" /> + <stripe length="8" offset="0x23AC" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x23A8" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x23A0" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0" /> + </stripe> + <stripe length="8" offset="0x23A4" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0" /> + </stripe> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" + offset="0x246C" /> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" + offset="0x2468" /> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" + offset="0x2464" /> + <reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" + offset="0x249C" /> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" + offset="0x2460" /> + <reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C"> + <doc>Z Buffer Band-Width Control Bit Defa</doc> + <bitfield high="0" low="0" name="HIZ_ENABLE"> + <use-enum ref="ENUM187" /> + </bitfield> + <doc>Enables hierarchical Z.</doc> + <bitfield high="1" low="1" name="HIZ_MIN"> + <use-enum ref="ENUM188" /> + </bitfield> + <doc /> + <bitfield high="2" low="2" name="FAST_FILL"> + <use-enum ref="ENUM189" /> + </bitfield> + <doc /> + <bitfield high="3" low="3" name="RD_COMP_ENABLE"> + <use-enum ref="ENUM190" /> + </bitfield> + <doc>Enables reading of compressed Z data from memory to the + cache.</doc> + <bitfield high="4" low="4" name="WR_COMP_ENABLE"> + <use-enum ref="ENUM191" /> + </bitfield> + <doc>Enables writing of compressed Z data from cache to + memory,</doc> + <bitfield high="5" low="5" name="ZB_CB_CLEAR"> + <use-enum ref="ENUM192" /> + </bitfield> + <doc>This bit is set when the Z buffer is used to help the CB + in clearing a region. Part of the region is cleared by the + color buffer and part will be cleared by the Z buffer. Since + the Z buffer does not have any write masks in the cache, full + micro-tiles need to be written. If a partial micro-tile is + touched , then the un-touched part will be unknowns. The + cache will operate in write-allocate mode and quads will be + accumulated in the cache and then evicted to main memory. The + color value is supplied through the ZB_DEPTHCLEARVALUE + register.</doc> + <bitfield high="6" low="6" name="FORCE_COMPRESSED_STENCIL" /> + <doc>Enabling this bit will force all the compressed stencil + values to be</doc> + </reg32> + <reg32 access="rw" name="ZB_CNTL" offset="0x4F00"> + <doc>Z Buffer Control</doc> + <bitfield high="0" low="0" name="STENCIL_ENABLE"> + <use-enum ref="ENUM178" /> + </bitfield> + <doc>Enables stenciling.</doc> + <bitfield high="1" low="1" name="Z_ENABLE"> + <use-enum ref="ENUM178" /> + </bitfield> + <doc>Enables Z functions.</doc> + <bitfield high="2" low="2" name="ZWRITEENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables writing of the Z buffer.</doc> + <bitfield high="3" low="3" name="ZSIGNED_COMPARE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enable signed Z buffer comparison , for + W-buffering.</doc> + <bitfield high="4" low="4" name="STENCIL_FRONT_BACK"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK + bit to one specifies that + stencilfunc/stencilfail/stencilzpass/stencilzfail registers + are used if the quad is generated from front faced primitive + and + stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf + are used if the quad is generated from a back faced + primitive. If the STENCIL_FRONT_BACK is not set, then + stencilfunc/stencilfail/stencilzpass/stencilzfail registers + determine the operation independent of the front/back face + state of the quad.</doc> + </reg32> + <reg32 access="rw" name="ZB_FORMAT" offset="0x4F10"> + <doc>Format of the Data in the Z buffer</doc> + <bitfield high="3" low="0" name="DEPTHFORMAT"> + <use-enum ref="ENUM196" /> + </bitfield> + <doc>Specifies the format of the Z buffer.</doc> + <bitfield high="4" low="4" name="INVERT"> + <value name="IN_13E3_FORMAT" value="0"> + <doc>in 13E3 format , count leading 0`s</doc> + </value> + <value name="IN_13E3_FORMAT" value="1"> + <doc>in 13E3 format , count leading 1`s.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="5" low="5" name="PEQ8"> + <value name="7_BYTES_PER_PLANE_EQUATION" value="0"> + <doc>7 bytes per plane equation, 1 byte for stencil</doc> + </value> + <value name="8_BYTES_PER_PLANE_EQUATION" value="1"> + <doc>8 bytes per plane equation, no bytes for + stencil</doc> + </value> + </bitfield> + <doc>This bit is unused</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44"> + <doc>Hierarchical Z Memory Offset</doc> + <bitfield high="16" low="2" name="HIZ_OFFSET" /> + <doc>DWORD offset into HiZ RAM. A DWORD can hold an 8-bit HiZ + value for 4 blocks, so this offset is aligned on 4 4x4 + blocks. In each pipe, the HIZ RAM DWORD address is generated + from a pixel x[11:0] , y[11:0] as follows: + HIZ_DWORD_ADDRESS[13:0] = HIZ_OFFSET[16:3] + Y[11:3] * + HIZ_PITCH[13:5] + X[11:5].</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50"> + <doc>Hierarchical Z Read Index</doc> + <bitfield high="16" low="2" name="HIZ_RDINDEX" /> + <doc>Read index into HiZ RAM. The index must start on a DWORD + boundary. RDINDEX words much like WRINDEX. Every read from + HIZ_DWORD will increment the register by 2.</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48"> + <doc>Hierarchical Z Write Index</doc> + <bitfield high="16" low="2" name="HIZ_WRINDEX" /> + <doc>Self-incrementing write index into the HiZ RAM. Starting + write index must start on a DWORD boundary. Each time + ZB_HIZ_DWORD is written, this index will increment by two + DWORD, this due to the fact that there are 2 pipes and the + data is broadcasted to both pipes. HIZ_OFFSET and HIZ_PITCH + are not used to compute read/write address to HIZ ram, when + it is accessed through WRINDEX and DWORD</doc> + </reg32> + <reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04"> + <doc>Z and Stencil Function Control</doc> + <bitfield high="2" low="0" name="ZFUNC"> + <use-enum ref="ENUM202" /> + </bitfield> + <doc>Specifies the Z function.</doc> + <bitfield high="5" low="3" name="STENCILFUNC"> + <use-enum ref="ENUM203" /> + </bitfield> + <doc>Specifies the stencil function.</doc> + <bitfield high="8" low="6" name="STENCILFAIL"> + <use-enum ref="ENUM204" /> + </bitfield> + <doc>Specifies the stencil value to be written if the stencil + test fails.</doc> + <bitfield high="11" low="9" name="STENCILZPASS" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled).</doc> + <bitfield high="14" low="12" name="STENCILZFAIL" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails.</doc> + <bitfield high="17" low="15" name="STENCILFUNC_BF" /> + <doc>Same encoding as STENCILFUNC. Specifies the stencil + function for back faced quads , if STENCIL_FRONT_BACK = + 1.</doc> + <bitfield high="20" low="18" name="STENCILFAIL_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test fails for back faced + quads, if STENCIL_FRONT_BACK = 1</doc> + <bitfield high="23" low="21" name="STENCILZPASS_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled) for back faced quads, if + STENCIL_FRONT_BACK = 1</doc> + <bitfield high="26" low="24" name="STENCILZFAIL_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails for back faced quads, if STENCIL_FRONT_BACK =1</doc> + </reg32> + </group> + <group name="r500_regs"> + <reg32 access="r" name="CP_CSQ2_STAT" offset="0x07FC"> + <doc>(RO) Command Stream Indirect Queue 2 Status</doc> + <bitfield high="9" low="0" name="CSQ_WPTR_INDIRECT" /> + <doc>Current Write Pointer into the Indirect Queue. Default = + 0.</doc> + <bitfield high="19" low="10" name="CSQ_RPTR_INDIRECT2" /> + <doc>Current Read Pointer into the Indirect Queue. Default = + 0.</doc> + <bitfield high="29" low="20" name="CSQ_WPTR_INDIRECT2" /> + <doc>Current Write Pointer into the Indirect Queue. Default = + 0.</doc> + </reg32> + <reg32 access="w" name="CP_CSQ_ADDR" offset="0x07F0"> + <doc>(WO) Command Stream Queue Address</doc> + <bitfield high="11" low="2" name="CSQ_ADDR" /> + <doc>Address into the Command Stream Queue which is to be + read from. Used for debug, to read the contents of the + Command Stream Queue.</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_APER_INDIRECT" offset="0x1300"> + <doc>IB1 Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_APER_INDIRECT2" + offset="0x1200"> + <doc>IB2 Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_APER_PRIMARY" offset="0x1000"> + <doc>Primary Aperture map in RBBM - PIO</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_AVAIL" offset="0x07B8"> + <doc>Command Stream Queue Available Counts</doc> + <bitfield high="9" low="0" name="CSQ_CNT_PRIMARY" /> + <doc>Count of available dwords in the queue for the Primary + Stream. Read Only.</doc> + <bitfield high="19" low="10" name="CSQ_CNT_INDIRECT" /> + <doc>Count of available dwords in the queue for the Indirect + Stream. Read Only.</doc> + <bitfield high="29" low="20" name="CSQ_CNT_INDIRECT2" /> + <doc>Count of available dwords in the queue for the Indirect + Stream. Read Only.</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_CNTL" offset="0x0740"> + <doc>Command Stream Queue Control</doc> + <bitfield high="31" low="28" name="CSQ_MODE"> + <value name="PRIMARY_DISABLED" value="0"> + <doc>Primary Disabled, Indirect Disabled.</doc> + </value> + <value name="PRIMARY_PIO" value="1"> + <doc>Primary PIO, Indirect Disabled.</doc> + </value> + <value name="PRIMARY_BM" value="2"> + <doc>Primary BM, Indirect Disabled. 3,5,</doc> + </value> + <value name="PRIMARY_PIO" value="7"> + <doc>Primary PIO, Indirect BM. 4,6,</doc> + </value> + <value name="PRIMARY_BM" value="8"> + <doc>Primary BM, Indirect BM. 9-</doc> + </value> + <value name="PRIMARY_PIO" value="15"> + <doc>Primary PIO, Indirect PIO Default = 0</doc> + </value> + </bitfield> + <doc>Command Stream Queue Mode. Controls whether each command + stream is enabled, and whether it is in push mode (Programmed + I/O), or pull mode (Bus-Master). Encodings are chosen to be + compatible with Rage128. 0= Primary Disabled, Indirect + Disabled. 1= Primary PIO, Indirect Disabled. 2= Primary BM, + Indirect Disabled. 3,5,7= Primary PIO, Indirect BM. 4,6,8= + Primary BM, Indirect BM. 9-14= Reserved. 15= Primary PIO, + Indirect PIO Default = 0</doc> + </reg32> + <reg32 access="r" name="CP_CSQ_DATA" offset="0x07F4"> + <doc>(RO) Command Stream Queue Data</doc> + </reg32> + <reg32 access="rw" name="CP_CSQ_MODE" offset="0x0744"> + <doc>Alternate Command Stream Queue Control</doc> + <bitfield high="6" low="0" name="INDIRECT2_START" /> + <doc>Start location of Indirect Queue #2 in the command + cache. This value also sets the size in double octwords of + the Indirect Queue #1 cache that will reside in locations + INDIRECT1_START to (INDIRECT2_START - 1). The Indirect Queue + #2 will reside in locations INDIRECT2_START to 0x5f. The + minimum size of the Indirect Queues must be at least twice + the MAX_FETCH size as programmed in the CP_RB_CNTL + register.</doc> + <bitfield high="14" low="8" name="INDIRECT1_START" /> + <doc>Start location of Indirect Queue #1 in the command + cache. This value is also the size in double octwords of the + Primary Queue cache that will reside in locations 0 to + (INDIRECT1_START - 1). The minimum size of the Primary Queue + cache must be at least twice the MAX_FETCH size as programmed + in the CP_RB_CNTL register.</doc> + <bitfield high="26" low="26" name="CSQ_INDIRECT2_MODE"> + <use-enum ref="ENUM207" /> + </bitfield> + <doc /> + <bitfield high="27" low="27" name="CSQ_INDIRECT2_ENABLE" /> + <doc>Enables Indirect Buffer #2. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the CSQ_MODE + variable in the CP_CSQ_CNTL register.</doc> + <bitfield high="28" low="28" name="CSQ_INDIRECT1_MODE"> + <use-enum ref="ENUM207" /> + </bitfield> + <doc /> + <bitfield high="29" low="29" name="CSQ_INDIRECT1_ENABLE" /> + <doc>Enables Indirect Buffer #1. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the CSQ_MODE + variable in the CP_CSQ_CNTL register.</doc> + <bitfield high="30" low="30" name="CSQ_PRIMARY_MODE"> + <use-enum ref="ENUM207" /> + </bitfield> + <doc /> + <bitfield high="31" low="31" name="CSQ_PRIMARY_ENABLE" /> + <doc>Enables Primary Buffer. If this bit is set, the + CP_CSQ_MODE register overrides the operation of the CSQ_MODE + variable in the CP_CSQ_CNTL register.</doc> + </reg32> + <reg32 access="r" name="CP_CSQ_STAT" offset="0x07F8"> + <doc>(RO) Command Stream Queue Status</doc> + <bitfield high="9" low="0" name="CSQ_RPTR_PRIMARY" /> + <doc>Current Read Pointer into the Primary Queue. Default = + 0.</doc> + <bitfield high="19" low="10" name="CSQ_WPTR_PRIMARY" /> + <doc>Current Write Pointer into the Primary Queue. Default = + 0.</doc> + <bitfield high="29" low="20" name="CSQ_RPTR_INDIRECT" /> + <doc>Current Read Pointer into the Indirect Queue. Default = + 0.</doc> + </reg32> + <reg32 access="rw" name="CP_GUI_COMMAND" offset="0x0728"> + <doc>Command for PIO GUI DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_GUI_DST_ADDR" offset="0x0724"> + <doc>Destination Address for PIO GUI DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_GUI_SRC_ADDR" offset="0x0720"> + <doc>Source Address for PIO GUI DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_IB2_BASE" offset="0x0730"> + <doc>Indirect Buffer 2 Base</doc> + <bitfield high="31" low="2" name="IB2_BASE" /> + <doc>Indirect Buffer 2 Base. Address of the beginning of the + indirect buffer. Only DWORD access is allowed to this + register.</doc> + </reg32> + <reg32 access="rw" name="CP_IB2_BUFSZ" offset="0x0734"> + <doc>Indirect Buffer 2 Size</doc> + <bitfield high="22" low="0" name="IB2_BUFSZ" /> + <doc>Indirect Buffer 2 Size. This size is expressed in + dwords. This field is an initiator to begin fetching commands + from the Indirect Buffer. Only DWORD access is allowed to + this register. Default = 0</doc> + </reg32> + <reg32 access="rw" name="CP_IB_BASE" offset="0x0738"> + <doc>Indirect Buffer Base</doc> + <bitfield high="31" low="2" name="IB_BASE" /> + <doc>Indirect Buffer Base. Address of the beginning of the + indirect buffer. Only DWORD access is allowed to this + register.</doc> + </reg32> + <reg32 access="rw" name="CP_IB_BUFSZ" offset="0x073C"> + <doc>Indirect Buffer Size</doc> + <bitfield high="22" low="0" name="IB_BUFSZ" /> + <doc>Indirect Buffer Size. This size is expressed in dwords. + This field is an initiator to begin fetching commands from + the Indirect Buffer. Only DWORD access is allowed to this + register. Default = 0</doc> + </reg32> + <reg32 access="rw" name="CP_ME_CNTL" offset="0x07D0"> + <doc>Micro Engine Control</doc> + <bitfield high="15" low="0" name="ME_STAT" /> + <doc>Status of MicroEngine internal registers. This value + depends on the current value of the ME_STATMUX field. Read + Only.</doc> + <bitfield high="20" low="16" name="ME_STATMUX" /> + <doc>Selects which status is to be returned on the ME_STAT + field.</doc> + <bitfield high="29" low="29" name="ME_BUSY" /> + <doc>Busy indicator for the MicroEngine. 0 = MicroEngine not + busy. 1 = MicroEngine is active. Read Only.</doc> + <bitfield high="30" low="30" name="ME_MODE" /> + <doc>Run-Mode of MicroEngine. 0 = Single-Step Mode. 1 = + Free-running Mode. Default = 1</doc> + <bitfield high="31" low="31" name="ME_STEP" /> + <doc>Step the MicroEngine by one instruction. Writing a `1` + to this field causes the MicroEngine to step by one + instruction, if and only if the ME_MODE bit is a `0`. Write + Only.</doc> + </reg32> + <reg32 access="rw" name="CP_ME_RAM_ADDR" offset="0x07D4"> + <doc>MicroEngine RAM Address</doc> + <bitfield high="7" low="0" name="ME_RAM_ADDR" /> + <doc>MicroEngine RAM Address (Write Mode) Writing this</doc> + </reg32> + <reg32 access="rw" name="CP_ME_RAM_DATAH" offset="0x07DC"> + <doc>MicroEngine RAM Data High</doc> + <bitfield high="7" low="0" name="ME_RAM_DATAH" /> + <doc>MicroEngine RAM Data High Used to load the MicroEngine + RAM.</doc> + </reg32> + <reg32 access="rw" name="CP_ME_RAM_DATAL" offset="0x07E0"> + <doc>MicroEngine RAM Data Low</doc> + </reg32> + <reg32 access="rw" name="CP_ME_RAM_RADDR" offset="0x07D8"> + <doc>MicroEngine RAM Read Address</doc> + <bitfield high="7" low="0" name="ME_RAM_RADDR" /> + <doc>MicroEngine RAM Address (Read Mode) Writing</doc> + </reg32> + <reg32 access="rw" name="CP_RB_BASE" offset="0x0700"> + <doc>Ring Buffer Base</doc> + <bitfield high="31" low="2" name="RB_BASE" /> + <doc>Ring Buffer Base. Address of the beginning of the ring + buffer.</doc> + </reg32> + <reg32 access="rw" name="CP_RB_CNTL" offset="0x0704"> + <doc>Ring Buffer Control</doc> + <bitfield high="5" low="0" name="RB_BUFSZ" /> + <doc>Ring Buffer Size. This size is expressed in log2 of the + actual size. Values 0 and 1 are clamped to an 8 DWORD ring + buffer. A value of 2 to 22 will give a ring buffer: + 2^(RB_BUFSZ+1). Values greater than 22 will clamp to 22. + Default = 0</doc> + <bitfield high="13" low="8" name="RB_BLKSZ" /> + <doc>Ring Buffer Block Size. This defines the number of + quadwords that the Command Processor will read between + updates to the host`s copy of the Read Pointer. This size is + expressed in log2 of the actual size (in 64-bit quadwords). + For example, for a block of 1024 quadwords, you would program + this field to 10(decimal). Default = 0</doc> + <bitfield high="17" low="16" name="BUF_SWAP" /> + <doc>Endian Swap Control for Ring Buffer and Indirect Buffer. + Only affects the chip behavior if the buffer resides in + system memory. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD + becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes + 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB + Default = 0</doc> + <bitfield high="19" low="18" name="MAX_FETCH" /> + <doc>Maximum Fetch Size for any read request that the CP + makes to memory. 0 = 1 double octword. (32 bytes) 1 = 2 + double octwords. (64 bytes) 2 = 4 double octwords. (128 + bytes) 3 = 8 double octwords. (256 bytes). Default =0</doc> + <bitfield high="27" low="27" name="RB_NO_UPDATE"> + <value name="WRITE_TO_HOST" value="0"> + <doc>Write to Host`s copy of Read Pointer in system + memory.</doc> + </value> + <value name="DO_NOT_WRITE_TO_HOST" value="1"> + <doc>Do not write to Host`s copy of Read pointer. The + purpose of this control bit is to have a fall-back + position if the bus- mastered write to system memory + doesn`t work, in which case the driver will have to read + the Graphics Controller`s copy of the Read Pointer + directly, with some performance penalty. Default = + 0</doc> + </value> + </bitfield> + <doc>Ring Buffer No Write to Read Pointer 0= Write to Host`s + copy of Read Pointer in system memory. 1= Do not write to + Host`s copy of Read pointer. The purpose of this control bit + is to have a fall-back position if the bus- mastered write to + system memory doesn`t work, in which case the driver will + have to read the Graphics Controller`s copy of the Read + Pointer directly, with some performance penalty. Default = + 0</doc> + <bitfield high="31" low="31" name="RB_RPTR_WR_ENA" /> + <doc>Ring Buffer Read Pointer Write Transfer Enable. When set + the contents of the CP_RB_RPTR_WR register is transferred to + the active read pointer (CP_RB_RPTR) whenever the CP_RB_WPTR + register is written. Default =0</doc> + </reg32> + <reg32 access="rw" name="CP_RB_RPTR" offset="0x0710"> + <doc>Ring Buffer Read Pointer Address (RO)</doc> + <bitfield high="22" low="0" name="RB_RPTR" /> + <doc>Ring Buffer Read Pointer. This is an index (in dwords) + of the current element being read from the ring buffer.</doc> + </reg32> + <reg32 access="rw" name="CP_RB_RPTR_ADDR" offset="0x070C"> + <doc>Ring Buffer Read Pointer Address</doc> + <bitfield high="1" low="0" name="RB_RPTR_SWAP" /> + <doc>Swap control of the reported read pointer address. See + CP_RB_CNTL.BUF_SWAP for the encoding.</doc> + <bitfield high="31" low="2" name="RB_RPTR_ADDR" /> + <doc>Ring Buffer Read Pointer Address. Address of the Host`s + copy of the Read Pointer. CP_RB_RPTR (RO) Ring Buffer Read + Pointer</doc> + </reg32> + <reg32 access="rw" name="CP_RB_RPTR_WR" offset="0x071C"> + <doc>Writable Ring Buffer Read Pointer Address</doc> + <bitfield high="22" low="0" name="RB_RPTR_WR" /> + <doc>Writable Ring Buffer Read Pointer. Writable for updating + the RB_RPTR after an ACPI.</doc> + </reg32> + <reg32 access="rw" name="CP_RB_WPTR" offset="0x0714"> + <doc>(RO) Ring Buffer Write Pointer</doc> + <bitfield high="22" low="0" name="RB_WPTR" /> + <doc>Ring Buffer Write Pointer. This is an index (in dwords) + of the last known element to be written to the ring buffer + (by the host).</doc> + </reg32> + <reg32 access="rw" name="CP_RB_WPTR_DELAY" offset="0x0718"> + <doc>Ring Buffer Write Pointer Delay</doc> + <bitfield high="27" low="0" name="PRE_WRITE_TIMER" /> + <doc>Pre-Write Timer. The number of clocks that a write to + the CP_RB_WPTR register will be delayed until actually taking + effect. Default = 0</doc> + <bitfield high="31" low="28" name="PRE_WRITE_LIMIT" /> + <doc>Pre-Write Limit. The number of times that the CP_RB_WPTR + register can be written (while the PRE_WRITE_TIMER has not + expired) before the CP_RB_WPTR register is forced to be + updated with the most recently written value. Default = + 0</doc> + </reg32> + <reg32 access="rw" name="CP_RESYNC_ADDR" offset="0x0778"> + <doc>Raster Engine Sync Address (WO)</doc> + <bitfield high="2" low="0" name="RESYNC_ADDR" /> + <doc>Scratch Register Offset Address.</doc> + </reg32> + <reg32 access="rw" name="CP_RESYNC_DATA" offset="0x077C"> + <doc>Raster Engine Sync Data (WO)</doc> + </reg32> + <reg32 access="r" name="CP_STAT" offset="0x07C0"> + <doc>(RO) Busy Status Signals</doc> + <bitfield high="0" low="0" name="MRU_BUSY" /> + <doc>Memory Read Unit Busy.</doc> + <bitfield high="1" low="1" name="MWU_BUSY" /> + <doc>Memory Write Unit Busy.</doc> + <bitfield high="2" low="2" name="RSIU_BUSY" /> + <doc>Register Backbone Input Interface Busy.</doc> + <bitfield high="3" low="3" name="RCIU_BUSY" /> + <doc>RBBM Output Interface Busy.</doc> + <bitfield high="9" low="9" name="CSF_PRIMARY_BUSY" /> + <doc>Primary Command Stream Fetcher Busy.</doc> + <bitfield high="10" low="10" name="CSF_INDIRECT_BUSY" /> + <doc>Indirect #1 Command Stream Fetcher Busy.</doc> + <bitfield high="11" low="11" name="CSQ_PRIMARY_BUSY" /> + <doc>Data in Command Queue for Primary Stream.</doc> + <bitfield high="12" low="12" name="CSQ_INDIRECT_BUSY" /> + <doc>Data in Command Queue for Indirect #1 Stream.</doc> + <bitfield high="13" low="13" name="CSI_BUSY" /> + <doc>Command Stream Interpreter Busy.</doc> + <bitfield high="14" low="14" name="CSF_INDIRECT2_BUSY" /> + <doc>Indirect #2 Command Stream Fetcher Busy.</doc> + <bitfield high="15" low="15" name="CSQ_INDIRECT2_BUSY" /> + <doc>Data in Command Queue for Indirect #2 Stream.</doc> + <bitfield high="28" low="28" name="GUIDMA_BUSY" /> + <doc>GUI DMA Engine Busy.</doc> + <bitfield high="29" low="29" name="VIDDMA_BUSY" /> + <doc>VID DMA Engine Busy.</doc> + <bitfield high="30" low="30" name="CMDSTRM_BUSY" /> + <doc>Command Stream Busy.</doc> + <bitfield high="31" low="31" name="CP_BUSY" /> + <doc>CP Busy.</doc> + </reg32> + <reg32 access="rw" name="CP_VID_COMMAND" offset="0x07CC"> + <doc>Command for PIO VID DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_VID_DST_ADDR" offset="0x07C8"> + <doc>Destination Address for PIO VID DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_VID_SRC_ADDR" offset="0x07C4"> + <doc>Source Address for PIO VID DMAs</doc> + </reg32> + <reg32 access="rw" name="CP_VP_ADDR_CNTL" offset="0x07E8"> + <doc>Virtual vs Physical Address Control - Selects whether + the address corresponds to a physical or virtual address in + memory.</doc> + <bitfield high="0" low="0" name="SCRATCH_ALT_VP_WR"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="1" low="1" name="SCRATCH_VP_WR"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="2" low="2" name="RPTR_VP_UPDATE"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="3" low="3" name="VIDDMA_VP_WR"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="4" low="4" name="VIDDMA_VP_RD"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="5" low="5" name="GUIDMA_VP_WR"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="6" low="6" name="GUIDMA_VP_RD"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="7" low="7" name="INDR2_VP_FETCH"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="8" low="8" name="INDR1_VP_FETCH"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + <bitfield high="9" low="9" name="RING_VP_FETCH"> + <use-enum ref="ENUM209" /> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88"> + <doc>Resolve Buffer Control. Unpipelined</doc> + <bitfield high="0" low="0" name="AARESOLVE_MODE" /> + <doc>Specifies if the color buffer is in resolve mode. The + cache must be empty before changing this register.</doc> + <bitfield high="1" low="1" name="AARESOLVE_GAMMA"> + <use-enum ref="ENUM1" /> + </bitfield> + <doc>Specifies the gamma and degamma to be applied to the + samples before and after filtering, respectively.</doc> + <bitfield high="2" low="2" name="AARESOLVE_ALPHA"> + <value name="RESOLVED_ALPHA_VALUE_IS_TAKEN_FROM_SAMPLE_0" + value="0"> + <doc>Resolved alpha value is taken from sample 0.</doc> + </value> + <value name="RESOLVED_ALPHA_VALUE_IS_THE_AVERAGE_OF_THE_SAMPLES" + value="1"> + <doc>Resolved alpha value is the average of the samples. + The average is not gamma corrected.</doc> + </value> + </bitfield> + <doc>Controls whether alpha is averaged in the resolve. 0 + => the resolved alpha value is selected from the sample 0 + value. 1=> the resolved alpha value is a filtered + (average) result of of the samples.</doc> + </reg32> + <reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04"> + <doc>Alpha Blend Control for Color Channels. Pipelined + through the blender.</doc> + <bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Allow alpha blending with the destination.</doc> + <bitfield high="1" low="1" name="SEPARATE_ALPHA_ENABLE"> + <use-enum ref="ENUM6" /> + </bitfield> + <doc>Enables use of RB3D_ABLENDCNTL</doc> + <bitfield high="2" low="2" name="READ_ENABLE"> + <use-enum ref="ENUM7" /> + </bitfield> + <doc>When blending is enabled, this enables memory reads. + Memory reads will still occur when this is disabled if they + are for reasons not related to blending.</doc> + <bitfield high="5" low="3" name="DISCARD_SRC_PIXELS"> + <value name="DISABLE" value="0"> + <doc>Disable</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="1"> + <doc>Discard pixels if src alpha <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_COLOR" value="2"> + <doc>Discard pixels if src color <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ARGB" value="3"> + <doc>Discard pixels if src argb <= + RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ALPHA" value="4"> + <doc>Discard pixels if src alpha >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_COLOR" value="5"> + <doc>Discard pixels if src color >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> + </value> + <value name="DISCARD_PIXELS_IF_SRC_ARGB" value="6"> + <doc>Discard pixels if src argb >= + RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc> + </value> + </bitfield> + <doc>Discard pixels when blending is enabled based on the src + color.</doc> + <bitfield high="14" low="12" name="COMB_FCN"> + <use-enum ref="ENUM2" /> + </bitfield> + <doc>Combine Function , Allows modification of how the + SRCBLEND and DESTBLEND are combined.</doc> + <bitfield high="21" low="16" name="SRCBLEND"> + <use-enum ref="ENUM3" /> + </bitfield> + <doc>Source Blend Function , Alpha blending function + (SRC).</doc> + <bitfield high="29" low="24" name="DESTBLEND"> + <use-enum ref="ENUM4" /> + </bitfield> + <doc>Destination Blend Function , Alpha blending function + (DST).</doc> + <bitfield high="30" low="30" name="SRC_ALPHA_0_NO_READ"> + <value name="DISABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" + value="0"> + <doc>Disable source alpha zero performance optimization + to skip reads</doc> + </value> + <value name="ENABLE_SOURCE_ALPHA_ZERO_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" + value="1"> + <doc>Enable source alpha zero performance optimization to + skip reads</doc> + </value> + </bitfield> + <doc>Enables source alpha zero performance optimization to + skip reads.</doc> + <bitfield high="31" low="31" name="SRC_ALPHA_1_NO_READ"> + <value name="DISABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" + value="0"> + <doc>Disable source alpha one performance optimization to + skip reads</doc> + </value> + <value name="ENABLE_SOURCE_ALPHA_ONE_PERFORMANCE_OPTIMIZATION_TO_SKIP_READS" + value="1"> + <doc>Enable source alpha one performance optimization to + skip reads</doc> + </value> + </bitfield> + <doc>Enables source alpha one performance optimization to + skip reads.</doc> + </reg32> + <reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD" + offset="0x4EA4"> + <doc>Discard src pixels greater than or equal to + threshold.</doc> + <bitfield high="7" low="0" name="BLUE" /> + <doc>Blue</doc> + <bitfield high="15" low="8" name="GREEN" /> + <doc>Green</doc> + <bitfield high="23" low="16" name="RED" /> + <doc>Red</doc> + <bitfield high="31" low="24" name="ALPHA" /> + <doc>Alpha</doc> + </reg32> + <reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD" + offset="0x4EA0"> + <doc>Discard src pixels less than or equal to + threshold.</doc> + <bitfield high="7" low="0" name="BLUE" /> + <doc>Blue</doc> + <bitfield high="15" low="8" name="GREEN" /> + <doc>Green</doc> + <bitfield high="23" low="16" name="RED" /> + <doc>Red</doc> + <bitfield high="31" low="24" name="ALPHA" /> + <doc>Alpha</doc> + </reg32> + <reg32 access="rw" name="RB3D_CCTL" offset="0x4E00"> + <doc>Unpipelined.</doc> + <bitfield high="6" low="5" name="NUM_MULTIWRITES"> + <use-enum ref="ENUM9" /> + </bitfield> + <doc>A quad is replicated and written to this many + buffers.</doc> + <bitfield high="7" low="7" name="CLRCMP_FLIPE_ENABLE"> + <use-enum ref="ENUM10" /> + </bitfield> + <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare + mode. This is used to ensure 3D data does not get chromakeyed + away by logic in the backend.</doc> + <bitfield high="9" low="9" name="AA_COMPRESSION_ENABLE"> + <use-enum ref="ENUM11" /> + </bitfield> + <doc>Enables AA color compression. Cmask must also be enabled + when aa compression is enabled. The cache must be empty + before this is changed.</doc> + <bitfield high="10" low="10" name="CMASK_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables use of the cmask ram. The cache must be empty + before this is changed.</doc> + <bitfield high="11" low="11" name="Reserved" /> + <doc>Set to 0</doc> + <bitfield high="12" low="12" + name="INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables indepedent color channel masks for the MRTs. + Disabling this feature will cause all the MRTs to use color + channel mask 0.</doc> + <bitfield high="13" low="13" + name="WRITE_COMPRESSION_DISABLE"> + <value name="ENABLE_WRITE_COMPRESSION" value="0"> + <doc>Enable write compression</doc> + </value> + <value name="DISABLE_WRITE_COMPRESSION" value="1"> + <doc>Disable write compression</doc> + </value> + </bitfield> + <doc>Disables write compression.</doc> + <bitfield high="14" low="14" + name="INDEPENDENT_COLORFORMAT_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables independent color format for the MRTs. Disabling + this feature will cause all the MRTs to use color format + 0.</doc> + </reg32> + <stripe length="4" offset="0x4E38" stride="0x0004"> + <reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0"> + <doc>Color buffer format and tiling control for all the + multibuffers and the pitch of multibuffer 0. Unpipelined. + The cache must be empty before any of the registers are + changed.</doc> + <bitfield high="13" low="1" name="COLORPITCH" /> + <doc>3D destination pitch in multiples of 2-pixels.</doc> + <bitfield high="16" low="16" name="COLORTILE"> + <use-enum ref="ENUM12" /> + </bitfield> + <doc>Denotes whether the 3D destination is in macrotiled + format.</doc> + <bitfield high="18" low="17" name="COLORMICROTILE"> + <use-enum ref="ENUM13" /> + </bitfield> + <doc>Denotes whether the 3D destination is in microtiled + format.</doc> + <bitfield high="20" low="19" name="COLORENDIAN"> + <use-enum ref="ENUM14" /> + </bitfield> + <doc>Specifies endian control for the color buffer.</doc> + <bitfield high="24" low="21" name="COLORFORMAT"> + <value name="ARGB10101010" value="0"> + <doc>ARGB10101010</doc> + </value> + <value name="UV1010" value="1"> + <doc>UV1010</doc> + </value> + <value name="CI8" value="2"> + <doc>CI8 (2D ONLY)</doc> + </value> + <value name="ARGB1555" value="3"> + <doc>ARGB1555</doc> + </value> + <value name="RGB565" value="4"> + <doc>RGB565</doc> + </value> + <value name="ARGB2101010" value="5"> + <doc>ARGB2101010</doc> + </value> + <value name="ARGB8888" value="6"> + <doc>ARGB8888</doc> + </value> + <value name="ARGB32323232" value="7"> + <doc>ARGB32323232</doc> + </value> + <value name="I8" value="9"> + <doc>I8</doc> + </value> + <value name="ARGB16161616" value="10"> + <doc>ARGB16161616</doc> + </value> + <value name="YUV422_PACKED" value="11"> + <doc>YUV422 packed (VYUY)</doc> + </value> + <value name="YUV422_PACKED" value="12"> + <doc>YUV422 packed (YVYU)</doc> + </value> + <value name="UV88" value="13"> + <doc>UV88</doc> + </value> + <value name="I10" value="14"> + <doc>I10</doc> + </value> + <value name="ARGB4444" value="15"> + <doc>ARGB4444</doc> + </value> + </bitfield> + <doc>3D destination color format.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" + offset="0x4E0C"> + <doc>3D Color Channel Mask. If all the channels used in the + current color format are disabled, then the cb will discard + all the incoming quads. Pipelined through the blender.</doc> + <bitfield high="0" low="0" name="BLUE_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the blue channel</doc> + <bitfield high="1" low="1" name="GREEN_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the green channel</doc> + <bitfield high="2" low="2" name="RED_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the red channel</doc> + <bitfield high="3" low="3" name="ALPHA_MASK"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the alpha channel</doc> + <bitfield high="4" low="4" name="BLUE_MASK1"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the blue channel of MRT 1</doc> + <bitfield high="5" low="5" name="GREEN_MASK1"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the green channel of MRT 1</doc> + <bitfield high="6" low="6" name="RED_MASK1"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the red channel of MRT 1</doc> + <bitfield high="7" low="7" name="ALPHA_MASK1"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the alpha channel of MRT 1</doc> + <bitfield high="8" low="8" name="BLUE_MASK2"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the blue channel of MRT 2</doc> + <bitfield high="9" low="9" name="GREEN_MASK2"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the green channel of MRT 2</doc> + <bitfield high="10" low="10" name="RED_MASK2"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the red channel of MRT 2</doc> + <bitfield high="11" low="11" name="ALPHA_MASK2"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the alpha channel of MRT 2</doc> + <bitfield high="12" low="12" name="BLUE_MASK3"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the blue channel of MRT 3</doc> + <bitfield high="13" low="13" name="GREEN_MASK3"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the green channel of MRT 3</doc> + <bitfield high="14" low="14" name="RED_MASK3"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the red channel of MRT 3</doc> + <bitfield high="15" low="15" name="ALPHA_MASK3"> + <use-enum ref="ENUM16" /> + </bitfield> + <doc>mask bit for the alpha channel of MRT 3</doc> + </reg32> + <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" + offset="0x4E14"> + <doc>Clear color that is used when the color mask is set to + 00. Unpipelined. Program this register with a 32-bit value in + ARGB8888 or ARGB2101010 formats, ignoring the fields.</doc> + <bitfield high="7" low="0" name="BLUE" /> + <doc>blue clear color</doc> + <bitfield high="15" low="8" name="GREEN" /> + <doc>green clear color</doc> + <bitfield high="23" low="16" name="RED" /> + <doc>red clear color</doc> + <bitfield high="31" low="24" name="ALPHA" /> + <doc>alpha clear color</doc> + </reg32> + <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_AR" + offset="0x46C0"> + <doc>Alpha and red clear color values that are used when the + color mask is set to 00 in FP16 per component mode. + Unpipelined.</doc> + <bitfield high="15" low="0" name="RED" /> + <doc>red clear color</doc> + <bitfield high="31" low="16" name="ALPHA" /> + <doc>alpha clear color</doc> + </reg32> + <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_GB" + offset="0x46C4"> + <doc>Green and blue clear color values that are used when the + color mask is set to 00 in FP16 per component mode. + Unpipelined.</doc> + <bitfield high="15" low="0" name="BLUE" /> + <doc>blue clear color</doc> + <bitfield high="31" low="16" name="GREEN" /> + <doc>green clear color</doc> + </reg32> + <reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10"> + <doc>Constant color used by the blender. Pipelined through + the blender.</doc> + <bitfield high="7" low="0" name="BLUE" /> + <doc>blue constant color (For R520, this field is ignored, + use RB3D_CONSTANT_COLOR_GB__BLUE instead)</doc> + <bitfield high="15" low="8" name="GREEN" /> + <doc>green constant color (For R520, this field is ignored, + use RB3D_CONSTANT_COLOR_GB__GREEN instead)</doc> + <bitfield high="23" low="16" name="RED" /> + <doc>red constant color (For R520, this field is ignored, use + RB3D_CONSTANT_COLOR_AR__RED instead)</doc> + <bitfield high="31" low="24" name="ALPHA" /> + <doc>alpha constant color (For R520, this field is ignored, + use RB3D_CONSTANT_COLOR_AR__ALPHA instead)</doc> + </reg32> + <reg32 access="rw" name="RB3D_CONSTANT_COLOR_AR" + offset="0x4EF8"> + <doc>Constant color used by the blender. Pipelined through + the blender.</doc> + <bitfield high="15" low="0" name="RED" /> + <doc>red constant color in 0.10 fixed or FP16 format</doc> + <bitfield high="31" low="16" name="ALPHA" /> + <doc>alpha constant color in 0.10 fixed or FP16 format</doc> + </reg32> + <reg32 access="rw" name="RB3D_CONSTANT_COLOR_GB" + offset="0x4EFC"> + <doc>Constant color used by the blender. Pipelined through + the blender.</doc> + <bitfield high="15" low="0" name="BLUE" /> + <doc>blue constant color in 0.10 fixed or FP16 format</doc> + <bitfield high="31" low="16" name="GREEN" /> + <doc>green constant color in 0.10 fixed or FP16 format</doc> + </reg32> + <reg32 access="rw" name="RB3D_FIFO_SIZE" offset="0x4EF4"> + <doc>Sets the fifo sizes</doc> + <bitfield high="1" low="0" name="OP_FIFO_SIZE"> + <use-enum ref="ENUM216" /> + </bitfield> + <doc>Determines the size of the op fifo</doc> + </reg32> + <reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4"> + <doc>Alpha Function</doc> + <bitfield high="7" low="0" name="AF_VAL" /> + <doc>Specifies the 8-bit alpha compare value when AF_EN_8BIT + is enabled</doc> + <bitfield high="10" low="8" name="AF_FUNC"> + <use-enum ref="ENUM22" /> + </bitfield> + <doc>Specifies the alpha compare function.</doc> + <bitfield high="11" low="11" name="AF_EN"> + <use-enum ref="ENUM23" /> + </bitfield> + <doc>Enables/Disables alpha compare function.</doc> + <bitfield high="12" low="12" name="AF_EN_8BIT"> + <value name="DEFAULT_10" value="0"> + <doc>Default 10-bit alpha compare.</doc> + </value> + <value name="ENABLE_8" value="1"> + <doc>Enable 8-bit alpha compare.</doc> + </value> + </bitfield> + <doc>Enable 8-bit alpha compare function.</doc> + <bitfield high="16" low="16" name="AM_EN"> + <use-enum ref="ENUM24" /> + </bitfield> + <doc>Enables/Disables alpha-to-mask function.</doc> + <bitfield high="17" low="17" name="AM_CFG"> + <use-enum ref="ENUM25" /> + </bitfield> + <doc>Specfies number of sub-pixel samples for alpha-to-mask + function.</doc> + <bitfield high="20" low="20" name="DITH_EN"> + <use-enum ref="ENUM26" /> + </bitfield> + <doc>Enables/Disables RGB Dithering (Not supported in + R520)</doc> + <bitfield high="24" low="24" name="ALP_OFF_EN"> + <value name="DISABLES_ALPHA_OFFSET_OF_2" value="0"> + <doc>Disables alpha offset of 2 (default r300 & rv350 + behavior)</doc> + </value> + <value name="ENABLES_OFFSET_OF_2_ON_ALPHA_COMING_IN_FROM_THE_US" + value="1"> + <doc>Enables offset of 2 on alpha coming in from the + US</doc> + </value> + </bitfield> + <doc>Alpha offset enable/disable (Not supported in + R520)</doc> + <bitfield high="25" low="25" name="DISCARD_ZERO_MASK_QUAD"> + <value name="NO_DISCARD_OF_ZERO_COVERAGE_MASK_QUADS" + value="0"> + <doc>No discard of zero coverage mask quads</doc> + </value> + <value name="DISCARD_ZERO_COVERAGE_MASK_QUADS" value="1"> + <doc>Discard zero coverage mask quads</doc> + </value> + </bitfield> + <doc>Enable/Disable discard zero mask coverage quad to + ZB</doc> + <bitfield high="28" low="28" name="FP16_ENABLE"> + <value name="DEFAULT_10" value="0"> + <doc>Default 10-bit alpha compare and alpha-to-mask + function</doc> + </value> + <value name="ENABLE_FP16_ALPHA_COMPARE_AND_ALPHA" + value="1"> + <doc>Enable FP16 alpha compare and alpha-to-mask + function</doc> + </value> + </bitfield> + <doc>Enables/Disables FP16 alpha function</doc> + </reg32> + <reg32 access="rw" name="FG_ALPHA_VALUE" offset="0x4BE0"> + <doc>Alpha Compare Value</doc> + <bitfield high="15" low="0" name="AF_VAL" /> + <doc>Specifies the alpha compare value, 0.10 fixed or FP16 + format</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0"> + <doc>Blue Component of Fog Color</doc> + <bitfield high="9" low="0" name="BLUE" /> + <doc>Blue component of fog color; (0.10) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC"> + <doc>Green Component of Fog Color</doc> + <bitfield high="9" low="0" name="GREEN" /> + <doc>Green component of fog color; (0.10) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8"> + <doc>Red Component of Fog Color</doc> + <bitfield high="9" low="0" name="RED" /> + <doc>Red component of fog color; (0.10) fixed format.</doc> + </reg32> + <reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4"> + <doc>Constant Factor for Fog Blending</doc> + <bitfield high="9" low="0" name="FACTOR" /> + <doc>Constant fog factor; fixed (0.10) format.</doc> + </reg32> + <reg32 access="rw" name="GA_COLOR_CONTROL_PS3" offset="0x4258"> + <doc>Specifies color properties and mappings of + textures.</doc> + <bitfield high="1" low="0" name="TEX0_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="3" low="2" name="TEX1_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="5" low="4" name="TEX2_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="7" low="6" name="TEX3_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="9" low="8" name="TEX4_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="11" low="10" name="TEX5_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="13" low="12" name="TEX6_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="15" low="14" name="TEX7_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="17" low="16" name="TEX8_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="19" low="18" name="TEX9_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for each texture.</doc> + <bitfield high="21" low="20" name="TEX10_SHADING_PS3"> + <use-enum ref="ENUM30" /> + </bitfield> + <doc>Specifies undefined(0), flat(1) and Gouraud(2/def) + shading for tex10 components.</doc> + <bitfield high="25" low="22" name="COLOR0_TEX_OVERRIDE"> + <use-enum ref="ENUM221" /> + </bitfield> + <doc>Specifies if each color should come from a texture and + which one.</doc> + <bitfield high="29" low="26" name="COLOR1_TEX_OVERRIDE"> + <use-enum ref="ENUM221" /> + </bitfield> + <doc>Specifies if each color should come from a texture and + which one.</doc> + </reg32> + <reg32 access="rw" name="GA_ENHANCE" offset="0x4274"> + <doc>GA Enhancement Register</doc> + <bitfield high="0" low="0" name="DEADLOCK_CNTL"> + <use-enum ref="ENUM32" /> + </bitfield> + <doc>TCL/GA Deadlock control.</doc> + <bitfield high="1" low="1" name="FASTSYNC_CNTL"> + <use-enum ref="ENUM33" /> + </bitfield> + <doc>Enables Fast register/primitive switching</doc> + <bitfield high="2" low="2" name="REG_READWRITE"> + <value name="NO_EFFECT" value="0"> + <doc>No effect.</doc> + </value> + <value name="ENABLES_GA_SUPPORT_OF_SIMULTANEOUS_REGISTER_READS_AND_WRITES" + value="1"> + <doc>Enables GA support of simultaneous register reads + and writes.</doc> + </value> + </bitfield> + <doc>R520+: When set, GA supports simultaneous register reads + & writes</doc> + <bitfield high="3" low="3" name="REG_NOSTALL"> + <value name="NO_EFFECT" value="0"> + <doc>No effect.</doc> + </value> + <value name="ENABLES_GA_SUPPORT_OF_NO" value="1"> + <doc>Enables GA support of no-stall reads for register + read back.</doc> + </value> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="GA_FIFO_CNTL" offset="0x4270"> + <doc>GA Input fifo high water marks</doc> + <bitfield high="2" low="0" name="VERTEX_FIFO" /> + <doc>Number of words remaining in input vertex fifo before + asserting nearly full</doc> + <bitfield high="5" low="3" name="INDEX_FIFO" /> + <doc>Number of words remaining in input primitive fifo before + asserting nearly full</doc> + <bitfield high="13" low="6" name="REG_FIFO" /> + <doc>Number of words remaining in input register fifo before + asserting nearly full</doc> + </reg32> + <reg32 access="rw" name="GA_FILL_A" offset="0x422C"> + <doc>Alpha fill color</doc> + </reg32> + <reg32 access="rw" name="GA_FILL_B" offset="0x4228"> + <doc>Blue fill color</doc> + </reg32> + <reg32 access="rw" name="GA_FILL_G" offset="0x4224"> + <doc>Green fill color</doc> + </reg32> + <reg32 access="rw" name="GA_FILL_R" offset="0x4220"> + <doc>Red fill color</doc> + </reg32> + <reg32 access="rw" name="GA_IDLE" offset="0x425C"> + <doc>Returns idle status of various G3D block, captured when + GA_IDLE written or when hard or soft reset asserted.</doc> + <bitfield high="0" low="0" name="PIPE3_Z_IDLE" /> + <doc>Idle status of physical pipe 3 Z unit</doc> + <bitfield high="1" low="1" name="PIPE2_Z_IDLE" /> + <doc>Idle status of physical pipe 2 Z unit</doc> + <bitfield high="2" low="2" name="PIPE3_CB_IDLE" /> + <doc>Idle status of physical pipe 3 CB unit</doc> + <bitfield high="3" low="3" name="PIPE2_CB_IDLE" /> + <doc>Idle status of physical pipe 2 CB unit</doc> + <bitfield high="4" low="4" name="PIPE3_FG_IDLE" /> + <doc>Idle status of physical pipe 3 FG unit</doc> + <bitfield high="5" low="5" name="PIPE2_FG_IDLE" /> + <doc>Idle status of physical pipe 2 FG unit</doc> + <bitfield high="6" low="6" name="PIPE3_US_IDLE" /> + <doc>Idle status of physical pipe 3 US unit</doc> + <bitfield high="7" low="7" name="PIPE2_US_IDLE" /> + <doc>Idle status of physical pipe 2 US unit</doc> + <bitfield high="8" low="8" name="PIPE3_SC_IDLE" /> + <doc>Idle status of physical pipe 3 SC unit</doc> + <bitfield high="9" low="9" name="PIPE2_SC_IDLE" /> + <doc>Idle status of physical pipe 2 SC unit</doc> + <bitfield high="10" low="10" name="PIPE3_RS_IDLE" /> + <doc>Idle status of physical pipe 3 RS unit</doc> + <bitfield high="11" low="11" name="PIPE2_RS_IDLE" /> + <doc>Idle status of physical pipe 2 RS unit</doc> + <bitfield high="12" low="12" name="PIPE1_Z_IDLE" /> + <doc>Idle status of physical pipe 1 Z unit</doc> + <bitfield high="13" low="13" name="PIPE0_Z_IDLE" /> + <doc>Idle status of physical pipe 0 Z unit</doc> + <bitfield high="14" low="14" name="PIPE1_CB_IDLE" /> + <doc>Idle status of physical pipe 1 CB unit</doc> + <bitfield high="15" low="15" name="PIPE0_CB_IDLE" /> + <doc>Idle status of physical pipe 0 CB unit</doc> + <bitfield high="16" low="16" name="PIPE1_FG_IDLE" /> + <doc>Idle status of physical pipe 1 FG unit</doc> + <bitfield high="17" low="17" name="PIPE0_FG_IDLE" /> + <doc>Idle status of physical pipe 0 FG unit</doc> + <bitfield high="18" low="18" name="PIPE1_US_IDLE" /> + <doc>Idle status of physical pipe 1 US unit</doc> + <bitfield high="19" low="19" name="PIPE0_US_IDLE" /> + <doc>Idle status of physical pipe 0 US unit</doc> + <bitfield high="20" low="20" name="PIPE1_SC_IDLE" /> + <doc>Idle status of physical pipe 1 SC unit</doc> + <bitfield high="21" low="21" name="PIPE0_SC_IDLE" /> + <doc>Idle status of physical pipe 0 SC unit</doc> + <bitfield high="22" low="22" name="PIPE1_RS_IDLE" /> + <doc>Idle status of physical pipe 1 RS unit</doc> + <bitfield high="23" low="23" name="PIPE0_RS_IDLE" /> + <doc>Idle status of physical pipe 0 RS unit</doc> + <bitfield high="24" low="24" name="SU_IDLE" /> + <doc>Idle status of SU unit</doc> + <bitfield high="25" low="25" name="GA_IDLE" /> + <doc>Idle status of GA unit</doc> + <bitfield high="26" low="26" name="GA_UNIT2_IDLE" /> + <doc>Idle status of GA unit2</doc> + </reg32> + <reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234"> + <doc>Line control</doc> + <bitfield high="15" low="0" name="WIDTH" /> + <doc>1/2 width of line, in subpixels (1/12 or 1/16 only, even + in 8b subprecision); (16.0) fixed format.</doc> + <bitfield high="17" low="16" name="END_TYPE"> + <use-enum ref="ENUM34" /> + </bitfield> + <doc>Specifies how ends of lines should be drawn.</doc> + <bitfield high="18" low="18" name="SORT"> + <value name="NO_SORTING" value="0"> + <doc>No sorting (default)</doc> + </value> + <value name="SORT_ON_MINX_THAN_MINY" value="1"> + <doc>Sort on minX than MinY</doc> + </value> + </bitfield> + <doc>R520+: When enabled, all lines are sorted so that V0 is + vertex with smallest X, or if X equal, smallest Y.</doc> + </reg32> + <reg32 access="rw" name="GA_OFFSET" offset="0x4290"> + <doc>Specifies x & y offsets for vertex data after + conversion to FP.</doc> + <bitfield high="15" low="0" name="X_OFFSET" /> + <doc>Specifies X offset in S15 format (subpixels -- 1/12 or + 1/16, even in 8b subprecision).</doc> + <bitfield high="31" low="16" name="Y_OFFSET" /> + <doc>Specifies Y offset in S15 format (subpixels -- 1/12 or + 1/16, even in 8b subprecision).</doc> + </reg32> + <reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C"> + <doc>Dimensions for Points</doc> + <bitfield high="15" low="0" name="HEIGHT" /> + <doc>1/2 Height of point; fixed (16.0), subpixel format (1/12 + or 1/16, even if in 8b precision).</doc> + <bitfield high="31" low="16" name="WIDTH" /> + <doc>1/2 Width of point; fixed (16.0), subpixel format (1/12 + or 1/16, even if in 8b precision)</doc> + </reg32> + <reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C"> + <doc>Specifies the rouding mode for geometry & color SPFP + to FP conversions.</doc> + <bitfield high="1" low="0" name="GEOMETRY_ROUND"> + <use-enum ref="ENUM38" /> + </bitfield> + <doc>Trunc (0) or round to nearest (1) for geometry + (XY).</doc> + <bitfield high="3" low="2" name="COLOR_ROUND"> + <use-enum ref="ENUM38" /> + </bitfield> + <doc>When set, FP32 to FP20 using round to nearest; otherwise + trunc</doc> + <bitfield high="4" low="4" name="RGB_CLAMP"> + <value name="CLAMP_TO" value="0"> + <doc>Clamp to [0,1.0] for RGB</doc> + </value> + <value name="RGB_IS_FP20" value="1"> + <doc>RGB is FP20</doc> + </value> + </bitfield> + <doc>Specifies SPFP color clamp range of [0,1] or FP20 for + RGB.</doc> + <bitfield high="5" low="5" name="ALPHA_CLAMP"> + <value name="CLAMP_TO" value="0"> + <doc>Clamp to [0,1.0] for Alpha</doc> + </value> + <value name="ALPHA_IS_FP20" value="1"> + <doc>Alpha is FP20</doc> + </value> + </bitfield> + <doc>Specifies SPFP alpha clamp range of [0,1] or FP20.</doc> + <bitfield high="9" low="6" name="GEOMETRY_MASK" /> + <doc>4b negative polarity mask for subpixel precision. + Inverted version gets ANDed with subpixel X, Y masks.</doc> + </reg32> + <reg32 access="rw" name="GA_SOLID_BA" offset="0x4280"> + <doc>Specifies blue & alpha components of fill color -- + S312 format -- Backwards comp.</doc> + <bitfield high="15" low="0" name="COLOR_ALPHA" /> + <doc>Component alpha value. (S3.12)</doc> + <bitfield high="31" low="16" name="COLOR_BLUE" /> + <doc>Component blue value. (S3.12)</doc> + </reg32> + <reg32 access="rw" name="GA_SOLID_RG" offset="0x427C"> + <doc>Specifies red & green components of fill color -- + S312 format -- Backwards comp.</doc> + <bitfield high="15" low="0" name="COLOR_GREEN" /> + <doc>Component green value (S3.12).</doc> + <bitfield high="31" low="16" name="COLOR_RED" /> + <doc>Component red value (S3.12).</doc> + </reg32> + <reg32 access="rw" name="GA_US_VECTOR_DATA" offset="0x4254"> + <doc>Data register for loading US instructions and + constants</doc> + </reg32> + <reg32 access="rw" name="GA_US_VECTOR_INDEX" offset="0x4250"> + <doc>Used to load US instructions and constants</doc> + <bitfield high="8" low="0" name="INDEX" /> + <doc>Instruction (TYPE == GA_US_VECTOR_INST) or constant + (TYPE == GA_US_VECTOR_CONST) number at which to start + loading. The GA will then expect n*6 (instructions) or n*4 + (constants) writes to GA_US_VECTOR_DATA. The GA will + self-increment until this register is written again. For + instructions, the GA expects the dwords in the following + order: US_CMN_INST, US_ALU_RGB_ADDR, US_ALU_ALPHA_ADDR, + US_ALU_ALPHA, US_RGB_INST, US_ALPHA_INST, US_RGBA_INST. For + constants, the GA expects the dwords in RGBA order.</doc> + <bitfield high="16" low="16" name="TYPE"> + <value name="LOAD_INSTRUCTIONS" value="0"> + <doc>Load instructions - INDEX is an instruction + index</doc> + </value> + <value name="LOAD_CONSTANTS" value="1"> + <doc>Load constants - INDEX is a constant index</doc> + </value> + </bitfield> + <doc>Specifies if the GA should load instructions or + constants.</doc> + <bitfield high="17" low="17" name="CLAMP"> + <value name="NO_CLAMPING_OF_DATA" value="0"> + <doc>No clamping of data - Default</doc> + </value> + <value name="CLAMP_TO" value="1"> + <doc>Clamp to [-1.0,1.0] constant data</doc> + </value> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="GB_ENABLE" offset="0x4008"> + <doc>Specifies top of Raster pipe specific enable + controls.</doc> + <bitfield high="0" low="0" name="POINT_STUFF_ENABLE"> + <use-enum ref="ENUM43" /> + </bitfield> + <doc>Specifies if points will have stuffed texture + coordinates.</doc> + <bitfield high="1" low="1" name="LINE_STUFF_ENABLE"> + <use-enum ref="ENUM44" /> + </bitfield> + <doc>Specifies if lines will have stuffed texture + coordinates.</doc> + <bitfield high="2" low="2" name="TRIANGLE_STUFF_ENABLE"> + <use-enum ref="ENUM45" /> + </bitfield> + <doc>Specifies if triangles will have stuffed texture + coordinates.</doc> + <bitfield high="5" low="4" name="STENCIL_AUTO"> + <use-enum ref="ENUM46" /> + </bitfield> + <doc>Specifies if the auto dec/inc stencil mode should be + enabled, and how.</doc> + <bitfield high="17" low="16" name="TEX0_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="19" low="18" name="TEX1_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="21" low="20" name="TEX2_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="23" low="22" name="TEX3_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="25" low="24" name="TEX4_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="27" low="26" name="TEX5_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="29" low="28" name="TEX6_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + <bitfield high="31" low="30" name="TEX7_SOURCE"> + <use-enum ref="ENUM229" /> + </bitfield> + <doc>Specifies the sources of the texture coordinates for + each texture.</doc> + </reg32> + <reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024"> + <doc>Specifies the sizes of the various FIFO`s in the + sc/rs/us. This register must be the first one written</doc> + <bitfield high="1" low="0" name="SC_IFIFO_SIZE"> + <use-enum ref="ENUM55" /> + </bitfield> + <doc>Size of scan converter input FIFO (XYZ)</doc> + <bitfield high="3" low="2" name="SC_TZFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of scan converter top-of-pipe Z FIFO</doc> + <bitfield high="5" low="4" name="SC_BFIFO_SIZE"> + <use-enum ref="ENUM55" /> + </bitfield> + <doc>Size of scan converter input FIFO (B)</doc> + <bitfield high="7" low="6" name="RS_TFIFO_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of ras input FIFO (Texture)</doc> + <bitfield high="9" low="8" name="RS_CFIFO_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of ras input FIFO (Color)</doc> + <bitfield high="11" low="10" name="US_RAM_SIZE"> + <use-enum ref="ENUM57" /> + </bitfield> + <doc>Size of us RAM</doc> + <bitfield high="13" low="12" name="US_OFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of us output FIFO (RGBA)</doc> + <bitfield high="15" low="14" name="US_WFIFO_SIZE"> + <use-enum ref="ENUM56" /> + </bitfield> + <doc>Size of us output FIFO (W)</doc> + <bitfield high="18" low="16" name="RS_HIGHWATER_COL" /> + <doc>High water mark for RS colors` fifo -- NOT USED</doc> + <bitfield high="21" low="19" name="RS_HIGHWATER_TEX" /> + <doc>High water mark for RS textures` fifo -- NOT USED</doc> + <bitfield high="23" low="22" name="US_OFIFO_HIGHWATER"> + <use-enum ref="ENUM58" /> + </bitfield> + <doc>High water mark for US output fifo</doc> + <bitfield high="28" low="24" name="US_CUBE_FIFO_HIGHWATER" /> + <doc>High water mark for US cube map fifo</doc> + </reg32> + <reg32 access="rw" name="GB_FIFO_SIZE1" offset="0x4070"> + <doc>Specifies the sizes of the various FIFO`s in the + sc/rs.</doc> + <bitfield high="5" low="0" name="SC_HIGHWATER_IFIFO" /> + <doc>High water mark for SC input fifo</doc> + <bitfield high="11" low="6" name="SC_HIGHWATER_BFIFO" /> + <doc>High water mark for SC input fifo (B)</doc> + <bitfield high="17" low="12" name="RS_HIGHWATER_COL" /> + <doc>High water mark for RS colors` fifo</doc> + <bitfield high="23" low="18" name="RS_HIGHWATER_TEX" /> + <doc>High water mark for RS textures` fifo</doc> + </reg32> + <reg32 access="rw" name="GB_MSPOS0" offset="0x4010"> + <doc>Specifies the position of multisamples 0 through 2</doc> + <bitfield high="3" low="0" name="MS_X0" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 0</doc> + <bitfield high="7" low="4" name="MS_Y0" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 0</doc> + <bitfield high="11" low="8" name="MS_X1" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 1</doc> + <bitfield high="15" low="12" name="MS_Y1" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 1</doc> + <bitfield high="19" low="16" name="MS_X2" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 2</doc> + <bitfield high="23" low="20" name="MS_Y2" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 2</doc> + <bitfield high="27" low="24" name="MSBD0_Y" /> + <doc>Specifies the minimum x and y distance (in subpixels) + between the pixel edge and the multisamples. These values are + used in the first (coarse) scan converter</doc> + <bitfield high="31" low="28" name="MSBD0_X" /> + <doc>Specifies the minimum x and y distance (in subpixels) + between the pixel edge and the multisamples. These values are + used in the first (coarse) scan converter</doc> + </reg32> + <reg32 access="rw" name="GB_MSPOS1" offset="0x4014"> + <doc>Specifies the position of multisamples 3 through 5</doc> + <bitfield high="3" low="0" name="MS_X3" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 3</doc> + <bitfield high="7" low="4" name="MS_Y3" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 3</doc> + <bitfield high="11" low="8" name="MS_X4" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 4</doc> + <bitfield high="15" low="12" name="MS_Y4" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 4</doc> + <bitfield high="19" low="16" name="MS_X5" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 5</doc> + <bitfield high="23" low="20" name="MS_Y5" /> + <doc>Specifies the x and y position (in subpixels) of + multisample 5</doc> + <bitfield high="27" low="24" name="MSBD1" /> + <doc>Specifies the minimum distance (in subpixels) between + the pixel edge and the multisamples. This value is used in + the second (quad) scan converter</doc> + </reg32> + <reg32 access="rw" name="GB_PIPE_SELECT" offset="0x402C"> + <doc>Selects which of 4 pipes are active.</doc> + <bitfield high="1" low="0" name="PIPE0_ID" /> + <doc>Maps physical pipe 0 to logical pipe ID (def 0).</doc> + <bitfield high="3" low="2" name="PIPE1_ID" /> + <doc>Maps physical pipe 1 to logical pipe ID (def 1).</doc> + <bitfield high="5" low="4" name="PIPE2_ID" /> + <doc>Maps physical pipe 2 to logical pipe ID (def 2).</doc> + <bitfield high="7" low="6" name="PIPE3_ID" /> + <doc>Maps physical pipe 3 to logical pipe ID (def 3).</doc> + <bitfield high="11" low="8" name="PIPE_MASK"> + <value name="P3" value="3"> + <doc>P3, B</doc> + </value> + <value name="P2" value="2"> + <doc>P2, B</doc> + </value> + <value name="P1" value="1"> + <doc>P1, B</doc> + </value> + <value name="P0" value="0"> + <doc>P0. -- 1: enabled,</doc> + </value> + <value name="DISABLED" value="0"> + <doc>disabled</doc> + </value> + </bitfield> + <doc>4b mask, indicates which physical pipes are enabled (def + none=0x0) -- B3=P3, B2=P2, B1=P1, B0=P0. -- 1: enabled, 0: + disabled</doc> + <bitfield high="13" low="12" name="MAX_PIPE" /> + <doc>2b, indicates, by the fuses, the max number of allowed + pipes. 0 = 1 pipe ... 3 = 4 pipes -- Read Only</doc> + <bitfield high="17" low="14" name="BAD_PIPES"> + <value name="P3" value="3"> + <doc>P3, B</doc> + </value> + <value name="P2" value="2"> + <doc>P2, B</doc> + </value> + <value name="P1" value="1"> + <doc>P1, B</doc> + </value> + <value name="P0" value="0"> + <doc>P0 --</doc> + </value> + <value name="BAD" value="1"> + <doc>bad,</doc> + </value> + <value name="GOOD" value="0"> + <doc>good -- Read Only</doc> + </value> + </bitfield> + <doc>4b, indicates, by the fuses, the bad pipes: B3=P3, + B2=P2, B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only</doc> + <bitfield high="18" low="18" name="CONFIG_PIPES"> + <value name="DO_NOTHING" value="0"> + <doc>Do nothing</doc> + </value> + <value name="FORCE_SELF" value="1"> + <doc>Force self-configuration</doc> + </value> + </bitfield> + <doc>If this bit is set when writing this register, the + logical pipe ID values are assigned automatically based on + the values that are read back in the MAX_PIPE and BAD_PIPES + fields. This field is always read back as 0.</doc> + </reg32> + <reg32 access="rw" name="GB_SELECT" offset="0x401C"> + <doc>Specifies various polygon specific selects (fog, depth, + perspective).</doc> + <bitfield high="2" low="0" name="FOG_SELECT"> + <use-enum ref="ENUM59" /> + </bitfield> + <doc>Specifies source for outgoing (GA to SU) fog + value.</doc> + <bitfield high="3" low="3" name="DEPTH_SELECT"> + <use-enum ref="ENUM60" /> + </bitfield> + <doc>Specifies source for outgoing (GA/SU & SU/RAS) depth + value.</doc> + <bitfield high="4" low="4" name="W_SELECT"> + <use-enum ref="ENUM61" /> + </bitfield> + <doc>Specifies source for outgoing (1/W) value, used to + disable perspective correct colors/textures.</doc> + <bitfield high="5" low="5" name="FOG_STUFF_ENABLE"> + <value name="DISABLE_FOG_TEXTURE_STUFFING" value="0"> + <doc>Disable fog texture stuffing</doc> + </value> + <value name="ENABLE_FOG_TEXTURE_STUFFING" value="1"> + <doc>Enable fog texture stuffing</doc> + </value> + </bitfield> + <doc>Controls enabling of fog stuffing into texture + coordinate.</doc> + <bitfield high="9" low="6" name="FOG_STUFF_TEX" /> + <doc>Controls which texture gets fog value</doc> + <bitfield high="11" low="10" name="FOG_STUFF_COMP" /> + <doc>Controls which component of texture gets fog value</doc> + </reg32> + <reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018"> + <doc>Specifies the graphics pipeline configuration for + rasterization</doc> + <bitfield high="0" low="0" name="ENABLE"> + <use-enum ref="ENUM62" /> + </bitfield> + <doc>Enables tiling, otherwise all tiles receive all + polygons.</doc> + <bitfield high="3" low="1" name="PIPE_COUNT"> + <value name="RV350" value="0"> + <doc>RV350 (1 pipe, 1 ctx)</doc> + </value> + <value name="R300" value="3"> + <doc>R300 (2 pipes, 1 ctx) 06 – + R420-3P (3 pipes, 1 ctx) 07 – R420 (4 + pipes, 1 ctx)</doc> + </value> + </bitfield> + <doc>Specifies the number of active pipes and contexts (up to + 4 pipes, 1 ctx). When this field is written, it is + automatically reduced by hardware so as not to use more pipes + than the number indicated in GB_PIPE_SELECT.MAX_PIPES or the + number of pipes left unmasked GB_PIPE_SELECT.BAD_PIPES. The + potentially altered value is read back, rather than the + original value written by software.</doc> + <bitfield high="5" low="4" name="TILE_SIZE"> + <value name="8_PIXELS" value="0"> + <doc>8 pixels.</doc> + </value> + <value name="16_PIXELS" value="1"> + <doc>16 pixels.</doc> + </value> + <value name="32_PIXELS" value="2"> + <doc>32 pixels.</doc> + </value> + </bitfield> + <doc>Specifies width & height (square), in pixels (only + 16, 32 available).</doc> + <bitfield high="8" low="6" name="SUPER_SIZE"> + <use-enum ref="ENUM65" /> + </bitfield> + <doc>Specifies number of tiles and config in super chip + configuration.</doc> + <bitfield high="11" low="9" name="SUPER_X" /> + <doc>X Location of chip within super tile.</doc> + <bitfield high="14" low="12" name="SUPER_Y" /> + <doc>Y Location of chip within super tile.</doc> + <bitfield high="15" low="15" name="SUPER_TILE"> + <use-enum ref="ENUM66" /> + </bitfield> + <doc>Tile location of chip in a multi super tile config + (Super size of 2,8,32 or 128).</doc> + <bitfield high="16" low="16" name="SUBPIXEL"> + <use-enum ref="ENUM67" /> + </bitfield> + <doc>Specifies the precision of subpixels wrt pixels (12 or + 16).</doc> + <bitfield high="18" low="17" name="QUADS_PER_RAS"> + <value name="4_QUADS" value="0"> + <doc>4 Quads</doc> + </value> + <value name="8_QUADS" value="1"> + <doc>8 Quads</doc> + </value> + <value name="16_QUADS" value="2"> + <doc>16 Quads</doc> + </value> + <value name="32_QUADS" value="3"> + <doc>32 Quads</doc> + </value> + </bitfield> + <doc>Specifies the number of quads to be sent to each + rasterizer in turn when in RV300B or R300B mode</doc> + <bitfield high="19" low="19" name="BB_SCAN"> + <value name="USE_INTERCEPT_BASED_SCAN_CONVERTER" value="0"> + <doc>Use intercept based scan converter</doc> + </value> + <value name="USE_BOUNDING_BOX_BASED_SCAN_CONVERTER" + value="1"> + <doc>Use bounding box based scan converter</doc> + </value> + </bitfield> + <doc>Specifies whether to use an intercept or bounding box + based calculation for the first (coarse) scan converter</doc> + <bitfield high="20" low="20" name="ALT_SCAN_EN"> + <value name="USE_NORMAL_LEFT" value="0"> + <doc>Use normal left-right scan</doc> + </value> + <value name="USE_ALTERNATE_LEFT" value="1"> + <doc>Use alternate left-right-left scan</doc> + </value> + </bitfield> + <doc>Specifies whether to use an altenate scan pattern for + the coarse scan converter</doc> + <bitfield high="21" low="21" name="ALT_OFFSET"> + <value name="NOT_USED" value="0"> + <doc>Not used</doc> + </value> + <value name="NOT_USED" value="1"> + <doc>Not used</doc> + </value> + </bitfield> + <doc>Not used -- should be 0</doc> + <bitfield high="22" low="22" name="SUBPRECISION" /> + <doc>Set to 0</doc> + <bitfield high="23" low="23" name="ALT_TILING"> + <value name="USE_DEFAULT_TILING_IN_ALL_TILING_MODES" + value="0"> + <doc>Use default tiling in all tiling modes</doc> + </value> + <value name="USE_ALTERNATIVE_3X2_TILING_IN_3P_MODE" + value="1"> + <doc>Use alternative 3x2 tiling in 3P mode</doc> + </value> + </bitfield> + <doc>Support for 3x2 tiling in 3P mode</doc> + <bitfield high="24" low="24" name="Z_EXTENDED"> + <value name="USE" value="0"> + <doc>Use (24.1) Z format, with vertex clamp to + [1.0,0.0]</doc> + </value> + <value name="USE" value="1"> + <doc>Use (S25.1) format, with vertex clamp to [2.0,- 2.0] + and per pixel [1.0,0.0]</doc> + </value> + </bitfield> + <doc>Support for extended setup Z range from [0,1] to [-2,2] + with per pixel clamping</doc> + </reg32> + <reg32 access="rw" name="GB_Z_PEQ_CONFIG" offset="0x4028"> + <doc>Specifies the z plane equation configuration.</doc> + <bitfield high="0" low="0" name="Z_PEQ_SIZE"> + <value name="4X4_Z_PLANE_EQUATIONS" value="0"> + <doc>4x4 z plane equations (point-sampled or aa)</doc> + </value> + <value name="8X8_Z_PLANE_EQUATIONS" value="1"> + <doc>8x8 z plane equations (point-sampled only)</doc> + </value> + </bitfield> + <doc>Specifies the z plane equation size.</doc> + </reg32> + <reg32 access="rw" name="RS_COUNT" offset="0x4300"> + <doc>This register specifies the rasterizer input packet + configuration</doc> + <bitfield high="6" low="0" name="IT_COUNT" /> + <doc>Specifies the total number of texture address components + contained in the rasterizer input packet (0:32).</doc> + <bitfield high="10" low="7" name="IC_COUNT" /> + <doc>Specifies the total number of colors contained in the + rasterizer input packet (0:4).</doc> + <bitfield high="17" low="12" name="W_ADDR" /> + <doc>Specifies the relative rasterizer input packet location + of w (if w_count==1)</doc> + <bitfield high="18" low="18" name="HIRES_EN" /> + <doc>Enable high resolution texture coordinate output when q + is equal to 1</doc> + </reg32> + <stripe length="16" offset="0x4320" stride="0x0004"> + <reg32 access="rw" name="RS_INST" offset="0x0"> + <doc>This table specifies what happens during each + rasterizer instruction</doc> + <bitfield high="3" low="0" name="TEX_ID" /> + <doc>Specifies the index (into the RS_IP table) of the + texture address output during this rasterizer + instruction</doc> + <bitfield high="4" low="4" name="TEX_CN"> + <use-enum ref="ENUM68" /> + </bitfield> + <doc>Write enable for texture address</doc> + <bitfield high="11" low="5" name="TEX_ADDR" /> + <doc>Specifies the destination address (within the current + pixel stack frame) of the texture address output during + this rasterizer instruction</doc> + <bitfield high="15" low="12" name="COL_ID" /> + <doc>Specifies the index (into the RS_IP table) of the + color output during this rasterizer instruction</doc> + <bitfield high="17" low="16" name="COL_CN"> + <value name="NO_WRITE" value="0"> + <doc>No write - color not valid</doc> + </value> + <value name="WRITE" value="1"> + <doc>write - color valid</doc> + </value> + <value name="WRITE_FBUFFER" value="2"> + <doc>write fbuffer - XY00->RGBA</doc> + </value> + <value name="WRITE_BACKFACE" value="3"> + <doc>write backface - B000->RGBA</doc> + </value> + </bitfield> + <doc>Write enable for color</doc> + <bitfield high="24" low="18" name="COL_ADDR" /> + <doc>Specifies the destination address (within the current + pixel stack frame) of the color output during this + rasterizer instruction</doc> + <bitfield high="25" low="25" name="TEX_ADJ"> + <use-enum ref="ENUM70" /> + </bitfield> + <doc>Specifies whether to sample texture coordinates at the + real or adjusted pixel centers</doc> + <bitfield high="26" low="26" name="W_CN"> + <value name="NO_WRITE" value="0"> + <doc>No write - w not valid</doc> + </value> + <value name="WRITE" value="1"> + <doc>write - w valid</doc> + </value> + </bitfield> + <doc>Specifies that the rasterizer should output w</doc> + </reg32> + </stripe> + <reg32 access="rw" name="RS_INST_COUNT" offset="0x4304"> + <doc>This register specifies the number of rasterizer + instructions</doc> + <bitfield high="3" low="0" name="INST_COUNT" /> + <doc>Number of rasterizer instructions (1:16)</doc> + <bitfield high="7" low="5" name="TX_OFFSET" /> + <doc>Indicates range of texture offset to minimize peroidic + errors on texels sampled right on their edges</doc> + </reg32> + <stripe length="16" offset="0x4074" stride="0x0004"> + <reg32 access="rw" name="RS_IP" offset="0x0"> + <doc>This table specifies the source location and format + for up to 16 texture addresses (i[0]:i[15]) and four colors + (c[0]:c[3])</doc> + <bitfield high="5" low="0" name="TEX_PTR_S" /> + <doc>Specifies the relative rasterizer input packet + location of each component (S, T, R, and Q) of texture + address (i[i]). The values 62 and 63 select constant inputs + for the component: 62 selects K0 (0.0), and 63 selects K1 + (1.0).</doc> + <bitfield high="11" low="6" name="TEX_PTR_T" /> + <doc>Specifies the relative rasterizer input packet + location of each component (S, T, R, and Q) of texture + address (i[i]). The values 62 and 63 select constant inputs + for the component: 62 selects K0 (0.0), and 63 selects K1 + (1.0).</doc> + <bitfield high="17" low="12" name="TEX_PTR_R" /> + <doc>Specifies the relative rasterizer input packet + location of each component (S, T, R, and Q) of texture + address (i[i]). The values 62 and 63 select constant inputs + for the component: 62 selects K0 (0.0), and 63 selects K1 + (1.0).</doc> + <bitfield high="23" low="18" name="TEX_PTR_Q" /> + <doc>Specifies the relative rasterizer input packet + location of each component (S, T, R, and Q) of texture + address (i[i]). The values 62 and 63 select constant inputs + for the component: 62 selects K0 (0.0), and 63 selects K1 + (1.0).</doc> + <bitfield high="26" low="24" name="COL_PTR" /> + <doc>Specifies the relative rasterizer input packet + location of the color (c[i]).</doc> + <bitfield high="30" low="27" name="COL_FMT"> + <use-enum ref="ENUM72" /> + </bitfield> + <doc>Specifies the format of the color (c[i]).</doc> + <bitfield high="31" low="31" name="OFFSET_EN"> + <value name="DO_NOT_APPLY_THE_TX_OFFSET_IN_RS_INST_COUNT" + value="0"> + <doc>Do not apply the TX_OFFSET in RS_INST_COUNT</doc> + </value> + <value name="APPLY_THE_TX_OFFSET_SPECIFIED_BY_RS_INST_COUNT" + value="1"> + <doc>Apply the TX_OFFSET specified by + RS_INST_COUNT</doc> + </value> + </bitfield> + <doc>Enable application of the TX_OFFSET in + RS_INST_COUNT</doc> + </reg32> + </stripe> + <reg32 access="rw" name="SC_EDGERULE" offset="0x43A8"> + <doc>Edge rules - what happens when an edge falls exactly on + a sample point</doc> + <bitfield high="4" low="0" name="ER_TRI"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="9" low="5" name="ER_POINT"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="14" low="10" name="ER_LINE_LR"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="19" low="15" name="ER_LINE_RL"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="24" low="20" name="ER_LINE_TB"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + <bitfield high="29" low="25" name="ER_LINE_BT"> + <use-enum ref="ENUM74" /> + </bitfield> + <doc>Edge rules for triangles, points, left-right lines, + right-left lines, upper-bottom lines, bottom-upper lines. For + values 0 to 15, bit 0 specifies whether a sample on a + horizontal- bottom edge is in, bit 1 specifies whether a + sample on a horizontal-top edge is in, bit 2 species whether + a sample on a right edge is in, bit 3 specifies whether a + sample on a left edge is in. For values 16 to 31, bit 0 + specifies whether a sample on a vertical-right edge is in, + bit 1 specifies whether a sample on a vertical-left edge is + in, bit 2 species whether a sample on a bottom edge is in, + bit 3 specifies whether a sample on a top edge is in</doc> + </reg32> + <reg32 access="rw" name="SU_REG_DEST" offset="0x42C8"> + <doc>SU Raster pipe destination select for registers</doc> + <bitfield high="3" low="0" name="SELECT"> + <value name="LOGICAL_PIPE0" value="0"> + <doc>logical pipe0, b</doc> + </value> + <value name="LOGICAL_PIPE1" value="1"> + <doc>logical pipe1, b</doc> + </value> + <value name="LOGICAL_PIPE2_AND_B" value="2"> + <doc>logical pipe2 and b</doc> + </value> + <value name="LOGICAL_PIPE3" value="3"> + <doc>logical pipe3</doc> + </value> + </bitfield> + <doc>Register read/write destination select: b0: logical + pipe0, b1: logical pipe1, b2: logical pipe2 and b3: logical + pipe3</doc> + </reg32> + <reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0"> + <doc>Enables for Cylindrical Wrapping</doc> + <bitfield high="0" low="0" name="T0C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="1" low="1" name="T0C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="2" low="2" name="T0C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="3" low="3" name="T0C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="4" low="4" name="T1C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="5" low="5" name="T1C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="6" low="6" name="T1C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="7" low="7" name="T1C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="8" low="8" name="T2C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="9" low="9" name="T2C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="10" low="10" name="T2C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="11" low="11" name="T2C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="12" low="12" name="T3C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="13" low="13" name="T3C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="14" low="14" name="T3C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="15" low="15" name="T3C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="16" low="16" name="T4C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="17" low="17" name="T4C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="18" low="18" name="T4C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="19" low="19" name="T4C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="20" low="20" name="T5C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="21" low="21" name="T5C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="22" low="22" name="T5C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="23" low="23" name="T5C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="24" low="24" name="T6C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="25" low="25" name="T6C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="26" low="26" name="T6C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="27" low="27" name="T6C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="28" low="28" name="T7C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="29" low="29" name="T7C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="30" low="30" name="T7C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="31" low="31" name="T7C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + </reg32> + <reg32 access="rw" name="SU_TEX_WRAP_PS3" offset="0x4114"> + <doc>Specifies texture wrapping for new PS3 textures.</doc> + <bitfield high="0" low="0" name="T9C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="1" low="1" name="T9C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="2" low="2" name="T9C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="3" low="3" name="T9C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="4" low="4" name="T8C0"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="5" low="5" name="T8C1"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="6" low="6" name="T8C2"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + <bitfield high="7" low="7" name="T8C3"> + <use-enum ref="ENUM247" /> + </bitfield> + <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) + of texture N.</doc> + </reg32> + <stripe length="16" offset="0x45C0" stride="0x0004"> + <reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0"> + <doc>Border Color</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4580" stride="0x0004"> + <reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0"> + <doc>Texture Chroma Key</doc> + </reg32> + </stripe> + <reg32 access="rw" name="TX_ENABLE" offset="0x4104"> + <doc>Texture Enables for Maps 0 to 15</doc> + <bitfield high="0" low="0" name="TEX_0_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="1" low="1" name="TEX_1_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="2" low="2" name="TEX_2_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="3" low="3" name="TEX_3_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="4" low="4" name="TEX_4_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="5" low="5" name="TEX_5_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="6" low="6" name="TEX_6_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="7" low="7" name="TEX_7_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="8" low="8" name="TEX_8_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="9" low="9" name="TEX_9_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="10" low="10" name="TEX_10_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="11" low="11" name="TEX_11_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="12" low="12" name="TEX_12_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="13" low="13" name="TEX_13_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="14" low="14" name="TEX_14_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + <bitfield high="15" low="15" name="TEX_15_ENABLE"> + <use-enum ref="ENUM248" /> + </bitfield> + <doc>Texture Map Enables.</doc> + </reg32> + <stripe length="16" offset="0x4400" stride="0x0004"> + <reg32 access="rw" name="TX_FILTER0" offset="0x0"> + <doc>Texture Filter State</doc> + <bitfield high="2" low="0" name="CLAMP_S"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for texture coordinates</doc> + <bitfield high="5" low="3" name="CLAMP_T"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for texture coordinates</doc> + <bitfield high="8" low="6" name="CLAMP_R"> + <use-enum ref="ENUM136" /> + </bitfield> + <doc>Clamp mode for texture coordinates</doc> + <bitfield high="10" low="9" name="MAG_FILTER"> + <use-enum ref="ENUM249" /> + </bitfield> + <doc>Filter used when texture is magnified</doc> + <bitfield high="12" low="11" name="MIN_FILTER"> + <use-enum ref="ENUM249" /> + </bitfield> + <doc>Filter used when texture is minified</doc> + <bitfield high="14" low="13" name="MIP_FILTER"> + <use-enum ref="ENUM138" /> + </bitfield> + <doc>Filter used between mipmap levels</doc> + <bitfield high="16" low="15" name="VOL_FILTER"> + <use-enum ref="ENUM139" /> + </bitfield> + <doc>Filter used between layers of a volume</doc> + <bitfield high="20" low="17" name="MAX_MIP_LEVEL" /> + <doc>LOD index of largest (finest) mipmap to use (0 is + largest). Ranges from 0 to NUM_LEVELS.</doc> + <bitfield high="31" low="28" name="ID" /> + <doc>Logical id for this physical texture</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4440" stride="0x0004"> + <reg32 access="rw" name="TX_FILTER1" offset="0x0"> + <doc>Texture Filter State</doc> + <bitfield high="1" low="0" name="CHROMA_KEY_MODE"> + <use-enum ref="ENUM140" /> + </bitfield> + <doc>Chroma Key Mode</doc> + <bitfield high="2" low="2" name="MC_ROUND"> + <use-enum ref="ENUM141" /> + </bitfield> + <doc>Bilinear rounding mode</doc> + <bitfield high="12" low="3" name="LOD_BIAS" /> + <doc>(s4.5). Ranges from -16.0 to 15.99. Mipmap LOD bias + measured in mipmap levels. Added to the signed, computed + LOD before the LOD is clamped.</doc> + <bitfield high="14" low="14" name="MC_COORD_TRUNCATE"> + <use-enum ref="ENUM142" /> + </bitfield> + <doc>MPEG coordinate truncation mode</doc> + <bitfield high="16" low="15" name="TRI_PERF"> + <value name="BREAKPOINT" value="0"> + <doc>Breakpoint=0/8. lfrac_out = lfrac_in</doc> + </value> + <value name="BREAKPOINT" value="1"> + <doc>Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in - + 1/6)</doc> + </value> + <value name="BREAKPOINT" value="2"> + <doc>Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in - + 1/2)</doc> + </value> + <value name="BREAKPOINT" value="3"> + <doc>Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in - + 3/2)</doc> + </value> + </bitfield> + <doc>Apply slope and bias to trilerp fraction to reduce the + number of 2-level fetches for trilinear. Should only be + used if MIP_FILTER is LINEAR.</doc> + <bitfield high="19" low="17" name="Reserved" /> + <doc>Set to 0</doc> + <bitfield high="20" low="20" name="Reserved" /> + <doc>Set to 0</doc> + <bitfield high="21" low="21" name="Reserved" /> + <doc>Set to 0</doc> + <bitfield high="22" low="22" name="MACRO_SWITCH"> + <value name="RV350_MODE" value="0"> + <doc>RV350 mode</doc> + </value> + <value name="SWITCH_FROM_MACRO" value="1"> + <doc>Switch from macro-tiled to macro-linear when + (width <= 8 micro-tiles)</doc> + </value> + </bitfield> + <doc>If enabled, addressing switches to macro-linear when + image width is <= 8 micro-tiles. If disabled, + functionality is same as RV350, switch to macro-linear when + image width is < 8 micro-tiles.</doc> + <bitfield high="31" low="31" name="BORDER_FIX"> + <value name="R3XX_R4XX_MODE" value="0"> + <doc>R3xx R4xx mode</doc> + </value> + <value name="STOP_RIGHT_SHIFTING_COORD_ONCE_MIP_SIZE_IS_PINNED_TO_ONE" + value="1"> + <doc>Stop right shifting coord once mip size is pinned + to one</doc> + </value> + </bitfield> + <doc>To fix issues when using non-square mipmaps, with + border_color, and extreme minification.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="TX_FILTER4" offset="0x4110"> + <doc>Filter4 Kernel</doc> + <bitfield high="10" low="0" name="WEIGHT_1" /> + <doc>(s1.9). Bottom or Right weight of pair.</doc> + <bitfield high="21" low="11" name="WEIGHT_0" /> + <doc>(s1.9). Top or Left weight of pair.</doc> + <bitfield high="22" low="22" name="WEIGHT_PAIR"> + <value name="TOP_OR_LEFT" value="0"> + <doc>Top or Left</doc> + </value> + <value name="BOTTOM_OR_RIGHT" value="1"> + <doc>Bottom or Right</doc> + </value> + </bitfield> + <doc>Indicates which pair of weights within phase to + load.</doc> + <bitfield high="26" low="23" name="PHASE" /> + <doc>Indicates which of 9 phases to load</doc> + <bitfield high="27" low="27" name="DIRECTION"> + <value name="HORIZONTAL" value="0"> + <doc>Horizontal</doc> + </value> + <value name="VERTICAL" value="1"> + <doc>Vertical</doc> + </value> + </bitfield> + <doc>Indicates whether to load the horizontal or vertical + weights</doc> + </reg32> + <stripe length="16" offset="0x4480" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT0" offset="0x0"> + <doc>Texture Format State</doc> + <bitfield high="10" low="0" name="TXWIDTH" /> + <doc>Image width - 1. The largest image is 4096 texels. + When wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power of 2 + in memory. Can always be non-square, except for cube maps + which must be square.</doc> + <bitfield high="21" low="11" name="TXHEIGHT" /> + <doc>Image height - 1. The largest image is 4096 texels. + When wrapping or mirroring, must be a power of 2. When + mipmapping, must be a power of 2 or padded to a power of 2 + in memory. Can always be non-square, except for cube maps + which must be square.</doc> + <bitfield high="25" low="22" name="TXDEPTH" /> + <doc>LOG2(depth) of volume texture</doc> + <bitfield high="29" low="26" name="NUM_LEVELS" /> + <doc>Number of mipmap levels minus 1. Ranges from 0 to 12. + Equivalent to LOD index of smallest (coarsest) mipmap to + use.</doc> + <bitfield high="30" low="30" name="PROJECTED"> + <use-enum ref="ENUM143" /> + </bitfield> + <doc>Specifies whether texture coords are projected.</doc> + <bitfield high="31" low="31" name="TXPITCH_EN"> + <use-enum ref="ENUM144" /> + </bitfield> + <doc>Indicates when TXPITCH should be used instead of + TXWIDTH for image addressing</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x44C0" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT1" offset="0x0"> + <doc>Texture Format State</doc> + <bitfield high="4" low="0" name="TXFORMAT"> + <value name="TX_FMT_8_OR_TX_FMT_1" value="0"> + <doc>TX_FMT_8 or TX_FMT_1 (if TX_FORMAT2.TXFORMAT_MSB + is set)</doc> + </value> + <value name="TX_FMT_16_OR_TX_FMT_1_REVERSE" value="1"> + <doc>TX_FMT_16 or TX_FMT_1_REVERSE (if + TX_FORMAT2.TXFORMAT_MSB is set)</doc> + </value> + <value name="TX_FMT_4_4_OR_TX_FMT_10" value="2"> + <doc>TX_FMT_4_4 or TX_FMT_10 (if + TX_FORMAT2.TXFORMAT_MSB is set)</doc> + </value> + <value name="TX_FMT_8_8_OR_TX_FMT_10_10" value="3"> + <doc>TX_FMT_8_8 or TX_FMT_10_10 (if + TX_FORMAT2.TXFORMAT_MSB is set)</doc> + </value> + <value name="TX_FMT_16_16_OR_TX_FMT_10_10_10_10" + value="4"> + <doc>TX_FMT_16_16 or TX_FMT_10_10_10_10 (if + TX_FORMAT2.TXFORMAT_MSB is set)</doc> + </value> + <value name="TX_FMT_3_3_2_OR_TX_FMT_ATI1N" value="5"> + <doc>TX_FMT_3_3_2 or TX_FMT_ATI1N (if + TX_FORMAT2.TXFORMAT_MSB is set)</doc> + </value> + <value name="TX_FMT_5_6_5" value="6"> + <doc>TX_FMT_5_6_5</doc> + </value> + <value name="TX_FMT_6_5_5" value="7"> + <doc>TX_FMT_6_5_5</doc> + </value> + <value name="TX_FMT_11_11_10" value="8"> + <doc>TX_FMT_11_11_10</doc> + </value> + <value name="TX_FMT_10_11_11" value="9"> + <doc>TX_FMT_10_11_11</doc> + </value> + <value name="TX_FMT_4_4_4_4" value="10"> + <doc>TX_FMT_4_4_4_4</doc> + </value> + <value name="TX_FMT_1_5_5_5" value="11"> + <doc>TX_FMT_1_5_5_5</doc> + </value> + <value name="TX_FMT_8_8_8_8" value="12"> + <doc>TX_FMT_8_8_8_8</doc> + </value> + <value name="TX_FMT_2_10_10_10" value="13"> + <doc>TX_FMT_2_10_10_10</doc> + </value> + <value name="TX_FMT_16_16_16_16" value="14"> + <doc>TX_FMT_16_16_16_16</doc> + </value> + <value name="TX_FMT_Y8" value="18"> + <doc>TX_FMT_Y8</doc> + </value> + <value name="TX_FMT_AVYU444" value="19"> + <doc>TX_FMT_AVYU444</doc> + </value> + <value name="TX_FMT_VYUY422" value="20"> + <doc>TX_FMT_VYUY422</doc> + </value> + <value name="TX_FMT_YVYU422" value="21"> + <doc>TX_FMT_YVYU422</doc> + </value> + <value name="TX_FMT_16_MPEG" value="22"> + <doc>TX_FMT_16_MPEG</doc> + </value> + <value name="TX_FMT_16_16_MPEG" value="23"> + <doc>TX_FMT_16_16_MPEG</doc> + </value> + <value name="TX_FMT_16F" value="24"> + <doc>TX_FMT_16f</doc> + </value> + <value name="TX_FMT_16F_16F" value="25"> + <doc>TX_FMT_16f_16f</doc> + </value> + <value name="TX_FMT_16F_16F_16F_16F" value="26"> + <doc>TX_FMT_16f_16f_16f_16f</doc> + </value> + <value name="TX_FMT_32F" value="27"> + <doc>TX_FMT_32f</doc> + </value> + <value name="TX_FMT_32F_32F" value="28"> + <doc>TX_FMT_32f_32f</doc> + </value> + <value name="TX_FMT_32F_32F_32F_32F" value="29"> + <doc>TX_FMT_32f_32f_32f_32f</doc> + </value> + <value name="TX_FMT_W24_FP" value="30"> + <doc>TX_FMT_W24_FP</doc> + </value> + <value name="TX_FMT_ATI2N" value="31"> + <doc>TX_FMT_ATI2N</doc> + </value> + </bitfield> + <doc>Texture Format. Components are numbered right to left. + Parenthesis indicate typical uses of each format.</doc> + <bitfield high="5" low="5" name="SIGNED_COMP0"> + <use-enum ref="ENUM256" /> + </bitfield> + <doc>Component filter should interpret texel data as signed + or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="6" low="6" name="SIGNED_COMP1"> + <use-enum ref="ENUM256" /> + </bitfield> + <doc>Component filter should interpret texel data as signed + or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="7" low="7" name="SIGNED_COMP2"> + <use-enum ref="ENUM256" /> + </bitfield> + <doc>Component filter should interpret texel data as signed + or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="8" low="8" name="SIGNED_COMP3"> + <use-enum ref="ENUM256" /> + </bitfield> + <doc>Component filter should interpret texel data as signed + or unsigned. (Ignored for Y/YUV formats.)</doc> + <bitfield high="11" low="9" name="SEL_ALPHA"> + <use-enum ref="ENUM257" /> + </bitfield> + <doc>Specifies swizzling for each channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="14" low="12" name="SEL_RED"> + <use-enum ref="ENUM257" /> + </bitfield> + <doc>Specifies swizzling for each channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="17" low="15" name="SEL_GREEN"> + <use-enum ref="ENUM257" /> + </bitfield> + <doc>Specifies swizzling for each channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="20" low="18" name="SEL_BLUE"> + <use-enum ref="ENUM257" /> + </bitfield> + <doc>Specifies swizzling for each channel at the input of + the pixel shader. (Ignored for Y/YUV formats.)</doc> + <bitfield high="21" low="21" name="GAMMA"> + <use-enum ref="ENUM154" /> + </bitfield> + <doc>Optionally remove gamma from texture before passing to + shader. Only apply to 8bit or less components.</doc> + <bitfield high="23" low="22" name="YUV_TO_RGB"> + <use-enum ref="ENUM155" /> + </bitfield> + <doc>YUV to RGB conversion mode</doc> + <bitfield high="24" low="24" name="SWAP_YUV"> + <use-enum ref="ENUM156" /> + </bitfield> + <doc /> + <bitfield high="26" low="25" name="TEX_COORD_TYPE"> + <use-enum ref="ENUM157" /> + </bitfield> + <doc>Specifies coordinate type.</doc> + <bitfield high="31" low="27" name="CACHE"> + <use-enum ref="ENUM158" /> + </bitfield> + <doc>This field is ignored on R520 and RV510.</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4500" stride="0x0004"> + <reg32 access="rw" name="TX_FORMAT2" offset="0x0"> + <doc>Texture Format State</doc> + <bitfield high="13" low="0" name="TXPITCH" /> + <doc>Used instead of TXWIDTH for image addressing when + TXPITCH_EN is asserted. Pitch is given as number of texels + minus one. Maximum pitch is 16K texels.</doc> + <bitfield high="14" low="14" name="TXFORMAT_MSB" /> + <doc>Specifies the MSB of the texture format to extend the + number of formats to 64.</doc> + <bitfield high="15" low="15" name="TXWIDTH_11" /> + <doc>Specifies bit 11 of TXWIDTH to extend the largest + image to 4096 texels.</doc> + <bitfield high="16" low="16" name="TXHEIGHT_11" /> + <doc>Specifies bit 11 of TXHEIGHT to extend the largest + image to 4096 texels.</doc> + <bitfield high="17" low="17" name="POW2FIX2FLT"> + <value name="DIVIDE_BY_POW2" value="0"> + <doc>Divide by pow2-1 for fix2float (default)</doc> + </value> + <value name="DIVIDE_BY_POW2_FOR_FIX2FLOAT" value="1"> + <doc>Divide by pow2 for fix2float</doc> + </value> + </bitfield> + <doc>Optionally divide by 256 instead of 255 during + fix2float. Can only be asserted for 8-bit components.</doc> + <bitfield high="19" low="18" name="SEL_FILTER4"> + <value name="SELECT_TEXTURE_COMPONENT0" value="0"> + <doc>Select Texture Component0.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT1" value="1"> + <doc>Select Texture Component1.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT2" value="2"> + <doc>Select Texture Component2.</doc> + </value> + <value name="SELECT_TEXTURE_COMPONENT3" value="3"> + <doc>Select Texture Component3.</doc> + </value> + </bitfield> + <doc>If filter4 is enabled, specifies which texture + component to apply filter4 to.</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4540" stride="0x0004"> + <reg32 access="rw" name="TX_OFFSET" offset="0x0"> + <doc>Texture Offset State</doc> + <bitfield high="1" low="0" name="ENDIAN_SWAP"> + <use-enum ref="ENUM159" /> + </bitfield> + <doc>Endian Control</doc> + <bitfield high="2" low="2" name="MACRO_TILE"> + <use-enum ref="ENUM160" /> + </bitfield> + <doc>Macro Tile Control</doc> + <bitfield high="4" low="3" name="MICRO_TILE"> + <use-enum ref="ENUM161" /> + </bitfield> + <doc>Micro Tile Control</doc> + <bitfield high="31" low="5" name="TXOFFSET" /> + <doc>32-byte aligned pointer to base map</doc> + </reg32> + </stripe> + <stripe length="512" offset="0xA800" stride="0x0004"> + <reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0"> + <doc>ALU Alpha Instruction</doc> + <bitfield high="3" low="0" name="ALPHA_OP"> + <value name="OP_MAD" value="0"> + <doc>OP_MAD: Result = A*B + C</doc> + </value> + <value name="OP_DP" value="1"> + <doc>OP_DP: Result = dot product from RGB ALU</doc> + </value> + <value name="OP_MIN" value="2"> + <doc>OP_MIN: Result = min(A,B)</doc> + </value> + <value name="OP_MAX" value="3"> + <doc>OP_MAX: Result = max(A,B)</doc> + </value> + <value name="OP_CND" value="5"> + <doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> + </value> + <value name="OP_CMP" value="6"> + <doc>OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B</doc> + </value> + <value name="OP_FRC" value="7"> + <doc>OP_FRC: Result = A-floor(A)</doc> + </value> + <value name="OP_EX" value="8"> + <doc>OP_EX</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result = 2^^A</doc> + </value> + <value name="OP_LN" value="9"> + <doc>OP_LN</doc> + </value> + <value name="RESULT" value="2"> + <doc>Result = log2(A)</doc> + </value> + <value name="OP_RCP" value="10"> + <doc>OP_RCP: Result = 1/A</doc> + </value> + <value name="OP_RSQ" value="11"> + <doc>OP_RSQ: Result = 1/sqrt(A)</doc> + </value> + <value name="OP_SIN" value="12"> + <doc>OP_SIN: Result = sin(A*2pi)</doc> + </value> + <value name="OP_COS" value="13"> + <doc>OP_COS: Result = cos(A*2pi)</doc> + </value> + <value name="OP_MDH" value="14"> + <doc>OP_MDH: Result = A*B + C; A is always + topleft.src0, C is always topright.src0 (source select + and swizzles ignored). Input modifiers are respected + for all inputs.</doc> + </value> + <value name="OP_MDV" value="15"> + <doc>OP_MDV: Result = A*B + C; A is always + topleft.src0, C is always bottomleft.src0 (source + select and swizzles ignored). Input modifiers are + respected for all inputs.</doc> + </value> + </bitfield> + <doc>Specifies the opcode for this instruction.</doc> + <bitfield high="10" low="4" name="ALPHA_ADDRD" /> + <doc>Specifies the address of the pixel stack frame + register to which the Alpha result of this instruction is + to be written.</doc> + <bitfield high="11" low="11" name="ALPHA_ADDRD_REL"> + <use-enum ref="ENUM261" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of ALPHA_ADDRD before it is used. This implements + relative addressing.</doc> + <bitfield high="13" low="12" name="ALPHA_SEL_A"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for Alpha inputs A and B.</doc> + <bitfield high="16" low="14" name="ALPHA_SWIZ_A"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies the channel sources for Alpha inputs A and + B.</doc> + <bitfield high="18" low="17" name="ALPHA_MOD_A"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for Alpha inputs A and + B.</doc> + <bitfield high="20" low="19" name="ALPHA_SEL_B"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for Alpha inputs A and B.</doc> + <bitfield high="23" low="21" name="ALPHA_SWIZ_B"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies the channel sources for Alpha inputs A and + B.</doc> + <bitfield high="25" low="24" name="ALPHA_MOD_B"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for Alpha inputs A and + B.</doc> + <bitfield high="28" low="26" name="OMOD"> + <use-enum ref="ENUM264" /> + </bitfield> + <doc>Specifies the output modifier for this + instruction.</doc> + <bitfield high="30" low="29" name="TARGET"> + <use-enum ref="ENUM265" /> + </bitfield> + <doc>This specifies which (cached) frame buffer target to + write to. For non-output ALU instructions, this specifies + how to compare the results against zero when setting the + predicate bits.</doc> + <bitfield high="31" low="31" name="W_OMASK"> + <value name="NONE" value="0"> + <doc>NONE: Do not write output to w.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only to w.</doc> + </value> + </bitfield> + <doc>Specifies whether or not to write the Alpha component + of the result of this instuction to the depth output + fifo.</doc> + </reg32> + </stripe> + <stripe length="512" offset="0x9800" stride="0x0004"> + <reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0"> + <doc>This table specifies the Alpha source addresses and + pre-subtract operation for up to 512 ALU instruction. The + ALU expects 6 source operands - three for color (rgb0, + rgb1, rgb2) and three for alpha (a0, a1, a2). The + pre-subtract operation creates two more (rgbp and + ap).</doc> + <bitfield high="7" low="0" name="ADDR0" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. If the const field is set, this number ranges from 0 to + 255 and specifies a location within the constant register + bank. Otherwise: If the most significant bit is cleared, + this field specifies a location within the current pixel + stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating- point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including denormals + but excluding infinite/NaN.</doc> + <bitfield high="8" low="8" name="ADDR0_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="9" low="9" name="ADDR0_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="17" low="10" name="ADDR1" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. If the const field is set, this number ranges from 0 to + 255 and specifies a location within the constant register + bank. Otherwise: If the most significant bit is cleared, + this field specifies a location within the current pixel + stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating- point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including denormals + but excluding infinite/NaN.</doc> + <bitfield high="18" low="18" name="ADDR1_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="19" low="19" name="ADDR1_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="27" low="20" name="ADDR2" /> + <doc>Specifies the identity of source operands a0, a1, and + a2. If the const field is set, this number ranges from 0 to + 255 and specifies a location within the constant register + bank. Otherwise: If the most significant bit is cleared, + this field specifies a location within the current pixel + stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating- point constant with 4 bit + exponent (bias 7) and 3 bit mantissa, including denormals + but excluding infinite/NaN.</doc> + <bitfield high="28" low="28" name="ADDR2_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="29" low="29" name="ADDR2_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="31" low="30" name="SRCP_OP"> + <use-enum ref="ENUM168" /> + </bitfield> + <doc>Specifies how the pre-subtract value (SRCP) is + computed.</doc> + </reg32> + </stripe> + <stripe length="512" offset="0xB000" stride="0x0004"> + <reg32 access="rw" name="US_ALU_RGBA_INST" offset="0x0"> + <doc>ALU Shared RGBA Instruction</doc> + <bitfield high="3" low="0" name="RGB_OP"> + <value name="OP_MAD" value="0"> + <doc>OP_MAD: Result = A*B + C</doc> + </value> + <value name="OP_DP" value="1"> + <doc>OP_DP</doc> + </value> + <value name="RESULT" value="3"> + <doc>Result = A.r*B.r + A.g*B.g + A.b*B.b</doc> + </value> + <value name="OP_DP" value="2"> + <doc>OP_DP</doc> + </value> + <value name="RESULT" value="4"> + <doc>Result = A.r*B.r + A.g*B.g + A.b*B.b + + A.a*B.a</doc> + </value> + <value name="OP_D2A" value="3"> + <doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc> + </value> + <value name="OP_MIN" value="4"> + <doc>OP_MIN: Result = min(A,B)</doc> + </value> + <value name="OP_MAX" value="5"> + <doc>OP_MAX: Result = max(A,B)</doc> + </value> + <value name="OP_CND" value="7"> + <doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc> + </value> + <value name="OP_CMP" value="8"> + <doc>OP_CMP: Result = cmp(A,B,C) = + (C>=0.0)?A:B</doc> + </value> + <value name="OP_FRC" value="9"> + <doc>OP_FRC: Result = A-floor(A)</doc> + </value> + <value name="OP_SOP" value="10"> + <doc>OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from + Alpha ALU</doc> + </value> + <value name="OP_MDH" value="11"> + <doc>OP_MDH: Result = A*B + C; A is always + topleft.src0, C is always topright.src0 (source select + and swizzles ignored). Input modifiers are respected + for all inputs.</doc> + </value> + <value name="OP_MDV" value="12"> + <doc>OP_MDV: Result = A*B + C; A is always + topleft.src0, C is always bottomleft.src0 (source + select and swizzles ignored). Input modifiers are + respected for all inputs.</doc> + </value> + </bitfield> + <doc>Specifies the opcode for this instruction.</doc> + <bitfield high="10" low="4" name="RGB_ADDRD" /> + <doc>Specifies the address of the pixel stack frame + register to which the RGB result of this instruction is to + be written.</doc> + <bitfield high="11" low="11" name="RGB_ADDRD_REL"> + <use-enum ref="ENUM261" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of RGB_ADDRD before it is used. This implements + relative addressing.</doc> + <bitfield high="13" low="12" name="RGB_SEL_C"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for RGB and Alpha input + C.</doc> + <bitfield high="16" low="14" name="RED_SWIZ_C"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB and Alpha + input C.</doc> + <bitfield high="19" low="17" name="GREEN_SWIZ_C"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB and Alpha + input C.</doc> + <bitfield high="22" low="20" name="BLUE_SWIZ_C"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB and Alpha + input C.</doc> + <bitfield high="24" low="23" name="RGB_MOD_C"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for RGB and Alpha input + C.</doc> + <bitfield high="26" low="25" name="ALPHA_SEL_C"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for RGB and Alpha input + C.</doc> + <bitfield high="29" low="27" name="ALPHA_SWIZ_C"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB and Alpha + input C.</doc> + <bitfield high="31" low="30" name="ALPHA_MOD_C"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for RGB and Alpha input + C.</doc> + </reg32> + </stripe> + <stripe length="512" offset="0xA000" stride="0x0004"> + <reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0"> + <doc>ALU RGB Instruction</doc> + <bitfield high="1" low="0" name="RGB_SEL_A"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for RGB inputs A and B.</doc> + <bitfield high="4" low="2" name="RED_SWIZ_A"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="7" low="5" name="GREEN_SWIZ_A"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="10" low="8" name="BLUE_SWIZ_A"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="12" low="11" name="RGB_MOD_A"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for RGB inputs A and + B.</doc> + <bitfield high="14" low="13" name="RGB_SEL_B"> + <use-enum ref="ENUM262" /> + </bitfield> + <doc>Specifies the operands for RGB inputs A and B.</doc> + <bitfield high="17" low="15" name="RED_SWIZ_B"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="20" low="18" name="GREEN_SWIZ_B"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="23" low="21" name="BLUE_SWIZ_B"> + <use-enum ref="ENUM263" /> + </bitfield> + <doc>Specifies, per channel, the sources for RGB inputs A + and B.</doc> + <bitfield high="25" low="24" name="RGB_MOD_B"> + <use-enum ref="ENUM167" /> + </bitfield> + <doc>Specifies the input modifiers for RGB inputs A and + B.</doc> + <bitfield high="28" low="26" name="OMOD"> + <use-enum ref="ENUM264" /> + </bitfield> + <doc>Specifies the output modifier for this + instruction.</doc> + <bitfield high="30" low="29" name="TARGET"> + <use-enum ref="ENUM265" /> + </bitfield> + <doc>This specifies which (cached) frame buffer target to + write to. For non-output ALU instructions, this specifies + how to compare the results against zero when setting the + predicate bits.</doc> + <bitfield high="31" low="31" name="ALU_WMASK"> + <value name="DO_NOT_MODIFY_THE_CURRENT_ALU_RESULT" + value="0"> + <doc>Do not modify the current ALU result.</doc> + </value> + <value name="MODIFY_THE_CURRENT_ALU_RESULT_BASED_ON_THE_SETTINGS_OF_ALU_RESULT_SEL_AND_ALU_RESULT_OP" + value="1"> + <doc>Modify the current ALU result based on the + settings of ALU_RESULT_SEL and ALU_RESULT_OP.</doc> + </value> + </bitfield> + <doc>Specifies whether to update the current ALU + result.</doc> + </reg32> + </stripe> + <stripe length="512" offset="0x9000" stride="0x0004"> + <reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0"> + <doc>This table specifies the RGB source addresses and + pre-subtract operation for up to 512 ALU instructions. The + ALU expects 6 source operands - three for color (rgb0, + rgb1, rgb2) and three for alpha (a0, a1, a2). The + pre-subtract operation creates two more (rgbp and + ap).</doc> + <bitfield high="7" low="0" name="ADDR0" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. If the const field is set, this number ranges + from 0 to 255 and specifies a location within the constant + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit exponent + (bias 7) and 3 bit mantissa, including denormals but + excluding infinite/NaN.</doc> + <bitfield high="8" low="8" name="ADDR0_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="9" low="9" name="ADDR0_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="17" low="10" name="ADDR1" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. If the const field is set, this number ranges + from 0 to 255 and specifies a location within the constant + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit exponent + (bias 7) and 3 bit mantissa, including denormals but + excluding infinite/NaN.</doc> + <bitfield high="18" low="18" name="ADDR1_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="19" low="19" name="ADDR1_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="27" low="20" name="ADDR2" /> + <doc>Specifies the identity of source operands rgb0, rgb1, + and rgb2. If the const field is set, this number ranges + from 0 to 255 and specifies a location within the constant + register bank. Otherwise: If the most significant bit is + cleared, this field specifies a location within the current + pixel stack frame (ranging from 0 to 127). If the most + significant bit is set, then the lower 7 bits specify an + inline unsigned floating-point constant with 4 bit exponent + (bias 7) and 3 bit mantissa, including denormals but + excluding infinite/NaN.</doc> + <bitfield high="28" low="28" name="ADDR2_CONST"> + <use-enum ref="ENUM267" /> + </bitfield> + <doc>Specifies whether the associated address is a constant + register address or a temporary address / inline + constant.</doc> + <bitfield high="29" low="29" name="ADDR2_REL"> + <use-enum ref="ENUM268" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="31" low="30" name="SRCP_OP"> + <use-enum ref="ENUM174" /> + </bitfield> + <doc>Specifies how the pre-subtract value (SRCP) is + computed.</doc> + </reg32> + </stripe> + <stripe length="512" offset="0xB800" stride="0x0004"> + <reg32 access="rw" name="US_CMN_INST" offset="0x0"> + <doc>Shared instruction fields for all instruction + types</doc> + <bitfield high="1" low="0" name="TYPE"> + <value name="US_INST_TYPE_ALU" value="0"> + <doc>US_INST_TYPE_ALU: This instruction is an ALU + instruction.</doc> + </value> + <value name="US_INST_TYPE_OUT" value="1"> + <doc>US_INST_TYPE_OUT: This instruction is an output + instruction.</doc> + </value> + <value name="US_INST_TYPE_FC" value="2"> + <doc>US_INST_TYPE_FC: This instruction is a flow + control instruction.</doc> + </value> + <value name="US_INST_TYPE_TEX" value="3"> + <doc>US_INST_TYPE_TEX: This instruction is a texture + instruction.</doc> + </value> + </bitfield> + <doc>Specifies the type of instruction. Note that output + instructions write to render targets.</doc> + <bitfield high="2" low="2" name="TEX_SEM_WAIT"> + <value name="THIS_INSTRUCTION_MAY_ISSUE_IMMEDIATELY" + value="0"> + <doc>This instruction may issue immediately.</doc> + </value> + <value name="THIS_INSTRUCTION_WILL_NOT_ISSUE_UNTIL_THE_TEXTURE_SEMAPHORE_IS_AVAILABLE" + value="1"> + <doc>This instruction will not issue until the texture + semaphore is available.</doc> + </value> + </bitfield> + <doc>Specifies whether to wait for the texture + semaphore.</doc> + <bitfield high="5" low="3" name="RGB_PRED_SEL"> + <value name="US_PRED_SEL_NONE" value="0"> + <doc>US_PRED_SEL_NONE: No predication</doc> + </value> + <value name="US_PRED_SEL_RGBA" value="1"> + <doc>US_PRED_SEL_RGBA: Independent Channel + Predication</doc> + </value> + <value name="US_PRED_SEL_RRRR" value="2"> + <doc>US_PRED_SEL_RRRR: R-Replicate Predication</doc> + </value> + <value name="US_PRED_SEL_GGGG" value="3"> + <doc>US_PRED_SEL_GGGG: G-Replicate Predication</doc> + </value> + <value name="US_PRED_SEL_BBBB" value="4"> + <doc>US_PRED_SEL_BBBB: B-Replicate Predication</doc> + </value> + <value name="US_PRED_SEL_AAAA" value="5"> + <doc>US_PRED_SEL_AAAA: A-Replicate Predication</doc> + </value> + </bitfield> + <doc>Specifies whether the instruction uses predication. + For ALU/TEX/Output this specifies predication for the RGB + channels only. For FC this specifies the predicate for the + entire instruction.</doc> + <bitfield high="6" low="6" name="RGB_PRED_INV"> + <use-enum ref="ENUM274" /> + </bitfield> + <doc>Specifies whether the predicate should be inverted. + For ALU/TEX/Output this specifies predication for the RGB + channels only. For FC this specifies the predicate for the + entire instruction.</doc> + <bitfield high="7" low="7" name="WRITE_INACTIVE"> + <value name="ONLY_WRITE_TO_CHANNELS_OF_ACTIVE_PIXELS" + value="0"> + <doc>Only write to channels of active pixels</doc> + </value> + <value name="WRITE_TO_CHANNELS_OF_ALL_PIXELS" value="1"> + <doc>Write to channels of all pixels, including + inactive pixels</doc> + </value> + </bitfield> + <doc>Specifies which pixels to write to.</doc> + <bitfield high="8" low="8" name="LAST"> + <value name="DO_NOT_TERMINATE_THE_SHADER_AFTER_EXECUTING_THIS_INSTRUCTION" + value="0"> + <doc>Do not terminate the shader after executing this + instruction (unless this instruction is at + END_ADDR).</doc> + </value> + <value name="ALL_ACTIVE_PIXELS_ARE_WILLING_TO_TERMINATE_AFTER_EXECUTING_THIS_INSTRUCTION" + value="1"> + <doc>All active pixels are willing to terminate after + executing this instruction. There is no guarantee that + the shader will actually terminate here. This feature + is provided as a performance optimization for tests + where pixels can conditionally terminate early.</doc> + </value> + </bitfield> + <doc>Specifies whether this is the last instruction.</doc> + <bitfield high="9" low="9" name="NOP"> + <value name="DO_NOT_INSERT_NOP_INSTRUCTION_AFTER_THIS_ONE" + value="0"> + <doc>Do not insert NOP instruction after this + one.</doc> + </value> + <value name="INSERT_A_NOP_INSTRUCTION_AFTER_THIS_ONE" + value="1"> + <doc>Insert a NOP instruction after this one.</doc> + </value> + </bitfield> + <doc>Specifies whether to insert a NOP instruction after + this. This would get specified in order to meet dependency + requirements for the pre-subtract inputs, and dependency + requirements for src0 of an MDH/MDV instruction.</doc> + <bitfield high="10" low="10" name="ALU_WAIT"> + <value name="DO_NOT_WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION" + value="0"> + <doc>Do not wait for pending ALU instructions to + complete before issuing the current instruction.</doc> + </value> + <value name="WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION" + value="1"> + <doc>Wait for pending ALU instructions to complete + before issuing the current instruction.</doc> + </value> + </bitfield> + <doc>Specifies whether to wait for pending ALU instructions + to complete before issuing this instruction.</doc> + <bitfield high="13" low="11" name="RGB_WMASK"> + <use-enum ref="ENUM279" /> + </bitfield> + <doc>Specifies which components of the result of the RGB + instruction are written to the pixel stack frame.</doc> + <bitfield high="14" low="14" name="ALPHA_WMASK"> + <value name="NONE" value="0"> + <doc>NONE: Do not write register.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only.</doc> + </value> + </bitfield> + <doc>Specifies whether the result of the Alpha instruction + is written to the pixel stack frame.</doc> + <bitfield high="17" low="15" name="RGB_OMASK"> + <use-enum ref="ENUM279" /> + </bitfield> + <doc>Specifies which components of the result of the RGB + instruction are written to the output fifo if this is an + output instruction, and which predicate bits should be + modified if this is an ALU instruction.</doc> + <bitfield high="18" low="18" name="ALPHA_OMASK"> + <value name="NONE" value="0"> + <doc>NONE: Do not write output.</doc> + </value> + <value name="A" value="1"> + <doc>A: Write the alpha channel only.</doc> + </value> + </bitfield> + <doc>Specifies whether the result of the Alpha instruction + is written to the output fifo if this is an output + instruction, and whether the Alpha predicate bit should be + modified if this is an ALU instruction.</doc> + <bitfield high="19" low="19" name="RGB_CLAMP"> + <use-enum ref="ENUM171" /> + </bitfield> + <doc>Specifies RGB and Alpha clamp mode for this + instruction.</doc> + <bitfield high="20" low="20" name="ALPHA_CLAMP"> + <use-enum ref="ENUM171" /> + </bitfield> + <doc>Specifies RGB and Alpha clamp mode for this + instruction.</doc> + <bitfield high="21" low="21" name="ALU_RESULT_SEL"> + <value name="RED" value="0"> + <doc>RED: Use red as ALU result for FC.</doc> + </value> + <value name="ALPHA" value="1"> + <doc>ALPHA: Use alpha as ALU result for FC.</doc> + </value> + </bitfield> + <doc>Specifies which component of the result of this + instruction should be used as the `ALU result` by a + subsequent flow control instruction.</doc> + <bitfield high="22" low="22" name="ALPHA_PRED_INV"> + <use-enum ref="ENUM274" /> + </bitfield> + <doc>Specifies whether the predicate should be inverted. + For ALU/TEX/Output this specifies predication for the alpha + channel only. This field has no effect on FC + instructions.</doc> + <bitfield high="24" low="23" name="ALU_RESULT_OP"> + <value name="EQUAL_TO" value="0"> + <doc>Equal to</doc> + </value> + <value name="LESS_THAN" value="1"> + <doc>Less than</doc> + </value> + <value name="GREATER_THAN_OR_EQUAL_TO" value="2"> + <doc>Greater than or equal to</doc> + </value> + <value name="NOT_EQUAL" value="3"> + <doc>Not equal</doc> + </value> + </bitfield> + <doc>Specifies how to compare the ALU result against zero + for the `alu_result` bit in a subsequent flow control + instruction.</doc> + <bitfield high="27" low="25" name="ALPHA_PRED_SEL"> + <value name="US_PRED_SEL_NONE" value="0"> + <doc>US_PRED_SEL_NONE: No predication</doc> + </value> + <value name="US_PRED_SEL_RGBA" value="1"> + <doc>US_PRED_SEL_RGBA: A predication (identical to + US_PRED_SEL_AAAA)</doc> + </value> + <value name="US_PRED_SEL_RRRR" value="2"> + <doc>US_PRED_SEL_RRRR: R Predication</doc> + </value> + <value name="US_PRED_SEL_GGGG" value="3"> + <doc>US_PRED_SEL_GGGG: G Predication</doc> + </value> + <value name="US_PRED_SEL_BBBB" value="4"> + <doc>US_PRED_SEL_BBBB: B Predication</doc> + </value> + <value name="US_PRED_SEL_AAAA" value="5"> + <doc>US_PRED_SEL_AAAA: A Predication</doc> + </value> + </bitfield> + <doc>Specifies whether the instruction uses predication. + For ALU/TEX/Output this specifies predication for the alpha + channel only. This field has no effect on FC + instructions.</doc> + <bitfield high="31" low="28" name="STAT_WE" /> + <doc>Specifies which components (R,G,B,A) contribute to the + stat count</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_CODE_ADDR" offset="0x4630"> + <doc>Code start and end instruction addresses.</doc> + <bitfield high="8" low="0" name="START_ADDR" /> + <doc>Specifies the address of the first instruction to + execute in the shader program. This address is relative to + the shader program offset given in + US_CODE_OFFSET.OFFSET_ADDR.</doc> + <bitfield high="24" low="16" name="END_ADDR" /> + <doc>Specifies the address of the last instruction to execute + in the shader program. This address is relative to the shader + program offset given in US_CODE_OFFSET.OFFSET_ADDR. Shader + program execution will always terminate after the instruction + at this address is executed.</doc> + </reg32> + <reg32 access="rw" name="US_CODE_OFFSET" offset="0x4638"> + <doc>Offsets used for relative instruction addresses in the + shader program, including START_ADDR, END_ADDR, and any + non-global flow control jump addresses.</doc> + <bitfield high="8" low="0" name="OFFSET_ADDR" /> + <doc>Specifies the offset to add to relative instruction + addresses, including START_ADDR, END_ADDR, and some flow + control jump addresses.</doc> + </reg32> + <reg32 access="rw" name="US_CODE_RANGE" offset="0x4634"> + <doc>Range of instructions that contains the current shader + program.</doc> + <bitfield high="8" low="0" name="CODE_ADDR" /> + <doc>Specifies the start address of the current code window. + This address is an absolute address.</doc> + <bitfield high="24" low="16" name="CODE_SIZE" /> + <doc>Specifies the size of the current code window, minus + one. The last instruction in the code window is given by + CODE_ADDR + CODE_SIZE.</doc> + </reg32> + <reg32 access="rw" name="US_CONFIG" offset="0x4600"> + <doc>Shader Configuration</doc> + <bitfield high="0" low="0" name="Reserved" /> + <doc>Set to 0</doc> + <bitfield high="1" low="1" + name="ZERO_TIMES_ANYTHING_EQUALS_ZERO"> + <value name="DEFAULT_BEHAVIOUR" value="0"> + <doc>Default behaviour (0*inf=nan,0*nan=nan)</doc> + </value> + <value name="LEGACY_BEHAVIOUR_FOR_SHADER_MODEL_1" + value="1"> + <doc>Legacy behaviour for shader model 1 + (0*anything=0)</doc> + </value> + </bitfield> + <doc>Control how ALU multiplier behaves when one argument is + zero. This affects the multiplier used in MAD and dot product + calculations.</doc> + </reg32> + <stripe length="512" offset="0xA000" stride="0x0004"> + <reg32 access="rw" name="US_FC_ADDR" offset="0x0"> + <doc>Flow Control Instruction Address Fields</doc> + <bitfield high="4" low="0" name="BOOL_ADDR" /> + <doc>The address of the static boolean register to use in + the jump function.</doc> + <bitfield high="12" low="8" name="INT_ADDR" /> + <doc>The address of the static integer register to use for + loop/rep and endloop/endrep.</doc> + <bitfield high="24" low="16" name="JUMP_ADDR" /> + <doc>The address to jump to if the jump function evaluates + to true.</doc> + <bitfield high="31" low="31" name="JUMP_GLOBAL"> + <value name="ADD_THE_SHADER_PROGRAM_OFFSET_IN_US_CODE_OFFSET" + value="0"> + <doc>Add the shader program offset in + US_CODE_OFFSET.OFFSET_ADDR when calculating the + destination address of a jump</doc> + </value> + <value name="DON" value="1"> + <doc>Don`t use the shader program offset when + calculating the destination address jump</doc> + </value> + </bitfield> + <doc>Specifies whether to interpret JUMP_ADDR as a global + address.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_FC_BOOL_CONST" offset="0x4620"> + <doc>Static Boolean Constants for Flow Control Branching + Instructions. Quad-buffered.</doc> + </reg32> + <reg32 access="rw" name="US_FC_CTRL" offset="0x4624"> + <doc>Flow Control Options. Quad-buffered.</doc> + <bitfield high="30" low="30" name="TEST_EN"> + <value name="NORMAL_MODE" value="0"> + <doc>Normal mode</doc> + </value> + <value name="TEST_MODE" value="1"> + <doc>Test mode (currently unused)</doc> + </value> + </bitfield> + <doc>Specifies whether test mode is enabled. This flag + currently has no effect in hardware.</doc> + <bitfield high="31" low="31" name="FULL_FC_EN"> + <value name="USE_PARTIAL_FLOW" value="0"> + <doc>Use partial flow-control (enables twice the + contexts). Loops and subroutines are not available in + partial flow-control mode, and the nesting depth of + branch statements is limited.</doc> + </value> + <value name="USE_FULL_PIXEL_SHADER_3" value="1"> + <doc>Use full pixel shader 3.0 flow control, including + loops and subroutines.</doc> + </value> + </bitfield> + <doc>Specifies whether full flow control functionality is + enabled.</doc> + </reg32> + <stripe length="512" offset="0x9800" stride="0x0004"> + <reg32 access="rw" name="US_FC_INST" offset="0x0"> + <doc>Flow Control Instruction</doc> + <bitfield high="2" low="0" name="OP"> + <value name="US_FC_OP_JUMP" value="0"> + <doc>US_FC_OP_JUMP: (if, endif, call, etc)</doc> + </value> + <value name="US_FC_OP_LOOP" value="1"> + <doc>US_FC_OP_LOOP: same as jump except always take the + jump if the static counter is 0. If we don`t take the + jump, push initial loop counter and loop register (aL) + values onto the loop stack.</doc> + </value> + <value name="US_FC_OP_ENDLOOP" value="2"> + <doc>US_FC_OP_ENDLOOP: same as jump but decrement the + loop counter and increment the loop register (aL), and + don`t take the jump if the loop counter becomes + zero.</doc> + </value> + <value name="US_FC_OP_REP" value="3"> + <doc>US_FC_OP_REP: same as loop but don`t push the loop + register aL.</doc> + </value> + <value name="US_FC_OP_ENDREP" value="4"> + <doc>US_FC_OP_ENDREP: same as endloop but don`t + update/pop the loop register aL.</doc> + </value> + <value name="US_FC_OP_BREAKLOOP" value="5"> + <doc>US_FC_OP_BREAKLOOP: same as jump but pops the loop + stacks if a pixel stops being active.</doc> + </value> + <value name="US_FC_OP_BREAKREP" value="6"> + <doc>US_FC_OP_BREAKREP: same as breakloop but don`t pop + the loop register if it jumps.</doc> + </value> + <value name="US_FC_OP_CONTINUE" value="7"> + <doc>US_FC_OP_CONTINUE: used to disable pixels that are + ready to jump to the ENDLOOP/ENDREP instruction.</doc> + </value> + </bitfield> + <doc>Specifies the type of flow control instruction.</doc> + <bitfield high="4" low="4" name="B_ELSE"> + <value name="DON" value="0"> + <doc>Don`t alter the branch state before executing the + instruction.</doc> + </value> + <value name="PERFORM_AN_ELSE_OPERATION_ON_THE_BRANCH_STATE_BEFORE_EXECUTING_THE_INSTRUCTION" + value="1"> + <doc>Perform an else operation on the branch state + before executing the instruction; pixels in the active + state are moved to the branch inactive state with zero + counter, and vice versa.</doc> + </value> + </bitfield> + <doc>Specifies whether to perform an else operation on the + active and branch-inactive pixels before executing the + instruction.</doc> + <bitfield high="5" low="5" name="JUMP_ANY"> + <value name="JUMP_IF_ALL_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP" + value="0"> + <doc>Jump if ALL active pixels want to take the jump + (for if and else). If no pixels are active, jump.</doc> + </value> + <value name="JUMP_IF_ANY_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP" + value="1"> + <doc>Jump if ANY active pixels want to take the jump + (for call, loop/rep and endrep/endloop). If no pixels + are active, do not jump.</doc> + </value> + </bitfield> + <doc>If set, jump if any active pixels want to take the + jump (otherwise the instruction jumps only if all active + pixels want to).</doc> + <bitfield high="7" low="6" name="A_OP"> + <value name="US_FC_A_OP_NONE" value="0"> + <doc>US_FC_A_OP_NONE: Don`t change the address + stack</doc> + </value> + <value name="US_FC_A_OP_POP" value="1"> + <doc>US_FC_A_OP_POP: If we jump, pop the address stack + and use that value for the jump target</doc> + </value> + <value name="US_FC_A_OP_PUSH" value="2"> + <doc>US_FC_A_OP_PUSH: If we jump, push the current + address onto the address stack</doc> + </value> + </bitfield> + <doc>The address stack operation to perform if we take the + jump.</doc> + <bitfield high="15" low="8" name="JUMP_FUNC" /> + <doc>A 2x2x2 table of boolean values indicating whether to + take the jump. The table index is indexed by {ALU Compare + Result, Predication Result, Boolean Value (from the static + boolean address in US_FC_ADDR.BOOL)}. To determine whether + to jump, look at bit ((alu_result<<2) | + (predicate<<1) | bool).</doc> + <bitfield high="20" low="16" name="B_POP_CNT" /> + <doc>The amount to decrement the branch counter by if + US_FC_B_OP_DECR operation is performed.</doc> + <bitfield high="25" low="24" name="B_OP0"> + <value name="US_FC_B_OP_NONE" value="0"> + <doc>US_FC_B_OP_NONE: If we don`t jump, don`t alter the + branch counter for any pixel.</doc> + </value> + <value name="US_FC_B_OP_DECR" value="1"> + <doc>US_FC_B_OP_DECR: If we don`t jump, decrement + branch counter by B_POP_CNT for inactive pixels. + Activate pixels with negative counters.</doc> + </value> + <value name="US_FC_B_OP_INCR" value="2"> + <doc>US_FC_B_OP_INCR: If we don`t jump, increment + branch counter by 1 for inactive pixels. Deactivate + pixels that decided to jump and set their counter to + zero.</doc> + </value> + </bitfield> + <doc>The branch state operation to perform if we don`t take + the jump.</doc> + <bitfield high="27" low="26" name="B_OP1"> + <value name="US_FC_B_OP_NONE" value="0"> + <doc>US_FC_B_OP_NONE: If we do jump, don`t alter the + branch counter for any pixel.</doc> + </value> + <value name="US_FC_B_OP_DECR" value="1"> + <doc>US_FC_B_OP_DECR: If we do jump, decrement branch + counter by B_POP_CNT for inactive pixels. Activate + pixels with negative counters.</doc> + </value> + <value name="US_FC_B_OP_INCR" value="2"> + <doc>US_FC_B_OP_INCR: If we do jump, increment branch + counter by 1 for inactive pixels. Deactivate pixels + that decided not to jump and set their counter to + zero.</doc> + </value> + </bitfield> + <doc>The branch state operation to perform if we do take + the jump.</doc> + <bitfield high="28" low="28" name="IGNORE_UNCOVERED"> + <value name="INCLUDE_UNCOVERED_PIXELS_IN_JUMP_DECISIONS" + value="0"> + <doc>Include uncovered pixels in jump decisions</doc> + </value> + <value name="IGNORE_UNCOVERED_PIXELS_IN_MAKING_JUMP_DECISIONS" + value="1"> + <doc>Ignore uncovered pixels in making jump + decisions</doc> + </value> + </bitfield> + <doc>If set, uncovered pixels will not participate in flow + control decisions.</doc> + </reg32> + </stripe> + <stripe length="32" offset="0x4C00" stride="0x0004"> + <reg32 access="rw" name="US_FC_INT_CONST" offset="0x0"> + <doc>Integer Constants used by Flow Control Loop + Instructions. Single buffered.</doc> + <bitfield high="7" low="0" name="KR" /> + <doc>Specifies the number of iterations. Unsigned 8-bit + integer in [0, 255].</doc> + <bitfield high="15" low="8" name="KG" /> + <doc>Specifies the initial value of the loop register (aL). + Unsigned 8-bit integer in [0, 255].</doc> + <bitfield high="23" low="16" name="KB" /> + <doc>Specifies the increment used to change the loop + register (aL) on each iteration. Signed 7-bit integer in + [-128, 127].</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x4640" stride="0x0004"> + <reg32 access="rw" name="US_FORMAT0" offset="0x0"> + <bitfield high="25" low="22" name="TXDEPTH"> + <value name="WIDTH" value="13"> + <doc>width > 2048, height <= 2048</doc> + </value> + <value name="WIDTH" value="14"> + <doc>width <= 2048, height > 2048</doc> + </value> + <value name="WIDTH" value="15"> + <doc>width > 2048, height > 2048</doc> + </value> + </bitfield> + <doc /> + </reg32> + </stripe> + <stripe length="4" offset="0x46A4" stride="0x0004"> + <reg32 access="rw" name="US_OUT_FMT" offset="0x0"> + <bitfield high="4" low="0" name="OUT_FMT"> + <use-enum ref="ENUM179" /> + </bitfield> + <doc /> + <bitfield high="9" low="8" name="C0_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc /> + <bitfield high="11" low="10" name="C1_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc /> + <bitfield high="13" low="12" name="C2_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc /> + <bitfield high="15" low="14" name="C3_SEL"> + <use-enum ref="ENUM180" /> + </bitfield> + <doc /> + <bitfield high="20" low="20" name="ROUND_ADJ"> + <value name="NORMAL_ROUNDING" value="0"> + <doc>Normal rounding</doc> + </value> + <value name="MODIFIED_ROUNDING_OF_FIXED" value="1"> + <doc>Modified rounding of fixed-point data</doc> + </value> + </bitfield> + <doc /> + </reg32> + </stripe> + <reg32 access="rw" name="US_PIXSIZE" offset="0x4604"> + <doc>Shader pixel size. This register specifies the size and + partitioning of the current pixel stack frame</doc> + <bitfield high="6" low="0" name="PIX_SIZE" /> + <doc>Specifies the total size of the current pixel stack + frame (1:128)</doc> + </reg32> + <stripe length="512" offset="0x9800" stride="0x0004"> + <reg32 access="rw" name="US_TEX_ADDR" offset="0x0"> + <doc>Texture addresses and swizzles</doc> + <bitfield high="6" low="0" name="SRC_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the texture address for this instruction</doc> + <bitfield high="7" low="7" name="SRC_ADDR_REL"> + <use-enum ref="ENUM298" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="9" low="8" name="SRC_S_SWIZ"> + <use-enum ref="ENUM299" /> + </bitfield> + <doc>Specify which colour channel of src_addr to use for S + coordinate</doc> + <bitfield high="11" low="10" name="SRC_T_SWIZ"> + <use-enum ref="ENUM300" /> + </bitfield> + <doc>Specify which colour channel of src_addr to use for T + coordinate</doc> + <bitfield high="13" low="12" name="SRC_R_SWIZ"> + <use-enum ref="ENUM301" /> + </bitfield> + <doc>Specify which colour channel of src_addr to use for R + coordinate</doc> + <bitfield high="15" low="14" name="SRC_Q_SWIZ"> + <use-enum ref="ENUM302" /> + </bitfield> + <doc>Specify which colour channel of src_addr to use for Q + coordinate</doc> + <bitfield high="22" low="16" name="DST_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the returned texture data for this + instruction</doc> + <bitfield high="23" low="23" name="DST_ADDR_REL"> + <value name="NONE" value="0"> + <doc>NONE: Do not modify destination address</doc> + </value> + <value name="RELATIVE" value="1"> + <doc>RELATIVE: Add aL before lookup.</doc> + </value> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="25" low="24" name="DST_R_SWIZ"> + <value name="WRITE_R_CHANNEL_TO_R_CHANNEL" value="0"> + <doc>Write R channel to R channel</doc> + </value> + <value name="WRITE_G_CHANNEL_TO_R_CHANNEL" value="1"> + <doc>Write G channel to R channel</doc> + </value> + <value name="WRITE_B_CHANNEL_TO_R_CHANNEL" value="2"> + <doc>Write B channel to R channel</doc> + </value> + <value name="WRITE_A_CHANNEL_TO_R_CHANNEL" value="3"> + <doc>Write A channel to R channel</doc> + </value> + </bitfield> + <doc>Specify which colour channel of the returned texture + data to write to the red channel of dst_addr</doc> + <bitfield high="27" low="26" name="DST_G_SWIZ"> + <value name="WRITE_R_CHANNEL_TO_G_CHANNEL" value="0"> + <doc>Write R channel to G channel</doc> + </value> + <value name="WRITE_G_CHANNEL_TO_G_CHANNEL" value="1"> + <doc>Write G channel to G channel</doc> + </value> + <value name="WRITE_B_CHANNEL_TO_G_CHANNEL" value="2"> + <doc>Write B channel to G channel</doc> + </value> + <value name="WRITE_A_CHANNEL_TO_G_CHANNEL" value="3"> + <doc>Write A channel to G channel</doc> + </value> + </bitfield> + <doc>Specify which colour channel of the returned texture + data to write to the green channel of dst_addr</doc> + <bitfield high="29" low="28" name="DST_B_SWIZ"> + <value name="WRITE_R_CHANNEL_TO_B_CHANNEL" value="0"> + <doc>Write R channel to B channel</doc> + </value> + <value name="WRITE_G_CHANNEL_TO_B_CHANNEL" value="1"> + <doc>Write G channel to B channel</doc> + </value> + <value name="WRITE_B_CHANNEL_TO_B_CHANNEL" value="2"> + <doc>Write B channel to B channel</doc> + </value> + <value name="WRITE_A_CHANNEL_TO_B_CHANNEL" value="3"> + <doc>Write A channel to B channel</doc> + </value> + </bitfield> + <doc>Specify which colour channel of the returned texture + data to write to the blue channel of dst_addr</doc> + <bitfield high="31" low="30" name="DST_A_SWIZ"> + <value name="WRITE_R_CHANNEL_TO_A_CHANNEL" value="0"> + <doc>Write R channel to A channel</doc> + </value> + <value name="WRITE_G_CHANNEL_TO_A_CHANNEL" value="1"> + <doc>Write G channel to A channel</doc> + </value> + <value name="WRITE_B_CHANNEL_TO_A_CHANNEL" value="2"> + <doc>Write B channel to A channel</doc> + </value> + <value name="WRITE_A_CHANNEL_TO_A_CHANNEL" value="3"> + <doc>Write A channel to A channel</doc> + </value> + </bitfield> + <doc>Specify which colour channel of the returned texture + data to write to the alpha channel of dst_addr</doc> + </reg32> + </stripe> + <stripe length="512" offset="0xA000" stride="0x0004"> + <reg32 access="rw" name="US_TEX_ADDR_DXDY" offset="0x0"> + <doc>Additional texture addresses and swizzles for DX/DY + inputs</doc> + <bitfield high="6" low="0" name="DX_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the DX value for this instruction</doc> + <bitfield high="7" low="7" name="DX_ADDR_REL"> + <use-enum ref="ENUM298" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="9" low="8" name="DX_S_SWIZ"> + <use-enum ref="ENUM299" /> + </bitfield> + <doc>Specify which colour channel of dx_addr to use for S + coordinate</doc> + <bitfield high="11" low="10" name="DX_T_SWIZ"> + <use-enum ref="ENUM300" /> + </bitfield> + <doc>Specify which colour channel of dx_addr to use for T + coordinate</doc> + <bitfield high="13" low="12" name="DX_R_SWIZ"> + <use-enum ref="ENUM301" /> + </bitfield> + <doc>Specify which colour channel of dx_addr to use for R + coordinate</doc> + <bitfield high="15" low="14" name="DX_Q_SWIZ"> + <use-enum ref="ENUM302" /> + </bitfield> + <doc>Specify which colour channel of dx_addr to use for Q + coordinate</doc> + <bitfield high="22" low="16" name="DY_ADDR" /> + <doc>Specifies the location (within the shader pixel stack + frame) of the DY value for this instruction</doc> + <bitfield high="23" low="23" name="DY_ADDR_REL"> + <use-enum ref="ENUM298" /> + </bitfield> + <doc>Specifies whether the loop register is added to the + value of the associated address before it is used. This + implements relative addressing.</doc> + <bitfield high="25" low="24" name="DY_S_SWIZ"> + <use-enum ref="ENUM299" /> + </bitfield> + <doc>Specify which colour channel of dy_addr to use for S + coordinate</doc> + <bitfield high="27" low="26" name="DY_T_SWIZ"> + <use-enum ref="ENUM300" /> + </bitfield> + <doc>Specify which colour channel of dy_addr to use for T + coordinate</doc> + <bitfield high="29" low="28" name="DY_R_SWIZ"> + <use-enum ref="ENUM301" /> + </bitfield> + <doc>Specify which colour channel of dy_addr to use for R + coordinate</doc> + <bitfield high="31" low="30" name="DY_Q_SWIZ"> + <use-enum ref="ENUM302" /> + </bitfield> + <doc>Specify which colour channel of dy_addr to use for Q + coordinate</doc> + </reg32> + </stripe> + <stripe length="512" offset="0x9000" stride="0x0004"> + <reg32 access="rw" name="US_TEX_INST" offset="0x0"> + <doc>Texture Instruction</doc> + <bitfield high="19" low="16" name="TEX_ID" /> + <doc>Specifies the id of the texture map used for this + instruction</doc> + <bitfield high="24" low="22" name="INST"> + <value name="NOP" value="0"> + <doc>NOP: Do nothing</doc> + </value> + <value name="LD" value="1"> + <doc>LD: Do Texture Lookup (S,T,R)</doc> + </value> + <value name="TEXKILL" value="2"> + <doc>TEXKILL: Kill pixel if any component is < + 0</doc> + </value> + <value name="PROJ" value="3"> + <doc>PROJ: Do projected texture lookup + (S/Q,T/Q,R/Q)</doc> + </value> + <value name="LODBIAS" value="4"> + <doc>LODBIAS: Do texture lookup with lod bias</doc> + </value> + <value name="LOD" value="5"> + <doc>LOD: Do texture lookup with explicit lod</doc> + </value> + <value name="DXDY" value="6"> + <doc>DXDY: Do texture lookup with lod calculated from + DX and DY</doc> + </value> + </bitfield> + <doc>Specifies the operation taking place for this + instruction</doc> + <bitfield high="25" low="25" name="TEX_SEM_ACQUIRE"> + <value name="DON" value="0"> + <doc>Don`t hold the texture semaphore</doc> + </value> + <value name="HOLD_THE_TEXTURE_SEMAPHORE_UNTIL_THE_DATA_IS_WRITTEN_TO_THE_TEMPORARY_REGISTER" + value="1"> + <doc>Hold the texture semaphore until the data is + written to the temporary register.</doc> + </value> + </bitfield> + <doc>Whether to hold the texture semaphore until the data + is written to the temporary register.</doc> + <bitfield high="26" low="26" name="IGNORE_UNCOVERED"> + <value name="FETCH_TEXELS_FOR_UNCOVERED_PIXELS" + value="0"> + <doc>Fetch texels for uncovered pixels</doc> + </value> + <value name="DON" value="1"> + <doc>Don`t fetch texels for uncovered pixels</doc> + </value> + </bitfield> + <doc>If set, US will not request data for pixels which are + uncovered. Clear this bit for indirect texture + lookups.</doc> + <bitfield high="27" low="27" name="UNSCALED"> + <value name="SCALE_THE_S" value="0"> + <doc>Scale the S, T, R texture coordinates from + [0.0,1.0] to the dimensions of the target texture</doc> + </value> + <value name="USE_THE_UNSCALED_S" value="1"> + <doc>Use the unscaled S, T, R texture coordates.</doc> + </value> + </bitfield> + <doc>Whether to scale texture coordinates when sending them + to the texture unit.</doc> + </reg32> + </stripe> + <reg32 access="rw" name="US_W_FMT" offset="0x46B4"> + <doc>Specifies the source and format for the Depth (W) value + output by the shader</doc> + <bitfield high="1" low="0" name="W_FMT"> + <value name="W" value="0"> + <doc>W</doc> + </value> + <value name="W_IS_ALWAYS_ZERO" value="0"> + <doc>W is always zero</doc> + </value> + <value name="W" value="1"> + <doc>W</doc> + </value> + <value name="24" value="24"> + <doc>24-bit fixed point</doc> + </value> + <value name="W24_FP" value="2"> + <doc>W24_FP - 24-bit floating point. The floating point + values are a special format that preserve sorting order + when values are compared as integers, allowing higher + precision in W without additional logic in other + blocks.</doc> + </value> + </bitfield> + <doc>Format for W</doc> + <bitfield high="2" low="2" name="W_SRC"> + <use-enum ref="ENUM183" /> + </bitfield> + <doc>Source for W</doc> + </reg32> + <reg32 access="rw" name="VAP_ALT_NUM_VERTICES" offset="0x2088"> + <doc>Alternate Number of Vertices to allow > 16-bits of + Vertex count</doc> + <bitfield high="23" low="0" name="NUM_VERTICES" /> + <doc>24-bit vertex count for command packet. Used instead of + bits 31:16 of VAP_VF_CNTL if VAP_VF_CNTL.USE_ALT_NUM_VERTS is + set.</doc> + </reg32> + <reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C"> + <doc>Control Bits for User Clip Planes and Clipping</doc> + <bitfield high="0" low="0" name="UCP_ENA_0" /> + <doc>Enable User Clip Plane 0</doc> + <bitfield high="1" low="1" name="UCP_ENA_1" /> + <doc>Enable User Clip Plane 1</doc> + <bitfield high="2" low="2" name="UCP_ENA_2" /> + <doc>Enable User Clip Plane 2</doc> + <bitfield high="3" low="3" name="UCP_ENA_3" /> + <doc>Enable User Clip Plane 3</doc> + <bitfield high="4" low="4" name="UCP_ENA_4" /> + <doc>Enable User Clip Plane 4</doc> + <bitfield high="5" low="5" name="UCP_ENA_5" /> + <doc>Enable User Clip Plane 5</doc> + <bitfield high="15" low="14" name="PS_UCP_MODE" /> + <doc>0 = Cull using distance from center of point 1 = Cull + using radius-based distance from center of point 2 = Cull + using radius-based distance from center of point, Expand and + Clip on intersection 3 = Always expand and clip as + trifan</doc> + <bitfield high="16" low="16" name="CLIP_DISABLE" /> + <doc>Disables clip code generation and clipping process for + TCL</doc> + <bitfield high="17" low="17" name="UCP_CULL_ONLY_ENA" /> + <doc>Cull Primitives against UCPS, but don`t clip</doc> + <bitfield high="18" low="18" name="BOUNDARY_EDGE_FLAG_ENA" /> + <doc>If set, boundary edges are highlighted, else they are + not highlighted</doc> + <bitfield high="20" low="20" name="COLOR2_IS_TEXTURE" /> + <doc>If set, color2 is used as texture8 by GA (PS3.0 + requirement)</doc> + <bitfield high="21" low="21" name="COLOR3_IS_TEXTURE" /> + <doc>If set, color3 is used as texture9 by GA (PS3.0 + requirement)</doc> + </reg32> + <reg32 access="rw" name="VAP_CNTL" offset="0x2080"> + <doc>Vertex Assembler/Processor Control Register</doc> + <bitfield high="3" low="0" name="PVS_NUM_SLOTS" /> + <doc>Specifies the number of vertex slots to be used in the + VAP PVS process. A slot represents a single vertex storage + location1 across multiple engines (one vertex per engine). By + decreasing the number of slots, there is more memory for each + vertex, but less parallel processing. Similarly, by + increasing the number of slots, there is less memory per + vertex but more vertices being processed in parallel.</doc> + <bitfield high="7" low="4" name="PVS_NUM_CNTLRS" /> + <doc>Specifies the maximum number of controllers to be + processing in parallel. In general should be set to max value + of TBD. Can be changed for performance analysis.</doc> + <bitfield high="11" low="8" name="PVS_NUM_FPUS" /> + <doc>Specifies the number of Floating Point Units + (Vector/Math Engines) to use when processing vertices.</doc> + <bitfield high="17" low="17" name="VAP_NO_RENDER" /> + <doc>If set, VAP will not process any draw commands (i.e. + writes to VAP_VF_CNTL, the INDX and DATAPORT and Immediate + mode writes are ignored.</doc> + <bitfield high="21" low="18" name="VF_MAX_VTX_NUM" /> + <doc>This field controls the number of vertices that the + vertex fetcher manages for the TCL and Setup Vertex Storage + memories (and therefore the number of vertices that can be + re-used). This value should be set to 12 for most operation, + This number may be modified for performance evaluation. The + value is the maximum vertex number used which is one less + than the number of vertices (i.e. a 12 means 13 vertices will + be used)</doc> + <bitfield high="22" low="22" name="DX_CLIP_SPACE_DEF"> + <use-enum ref="ENUM184" /> + </bitfield> + <doc>Clip space is defined as:</doc> + <bitfield high="23" low="23" name="TCL_STATE_OPTIMIZATION" /> + <doc>If set, enables the TCL state optimization, and the new + state is used only if there is a change in TCL state, between + VF_CNTL (triggers)</doc> + </reg32> + <reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140"> + <doc>Vertex Assemblen/Processor Control Status</doc> + <bitfield high="1" low="0" name="VC_SWAP" /> + <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: + 0xAABBCCDD becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD + becomes 0xDDCCBBAA 3 = Half-dword swap: 0xAABBCCDD becomes + 0xCCDDAABB Default = 0</doc> + <bitfield high="8" low="8" name="PVS_BYPASS" /> + <doc>The TCL engine is logically or physically removed from + the circuit.</doc> + <bitfield high="11" low="11" name="PVS_BUSY" /> + <doc>Transform/Clip/Light (TCL) Engine is Busy. + Read-only.</doc> + <bitfield high="19" low="16" name="MAX_MPS" /> + <doc>Maximum number of MPs fused for this chip. Read- only. + For A11, fusemask is fixed to 1XXX. For A12, + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 000 => max_mps[3:0] = + 1XXX => 8 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 001 + => max_mps[3:0] = 0110 => 6 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 010 => max_mps[3:0] = + 0101 => 5 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 011 + => max_mps[3:0] = 0100 => 4 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 100 => max_mps[3:0] = + 0011 => 3 MPs CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 101 + => max_mps[3:0] = 0010 => 2 MPs + CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 110 => max_mps[3:0] = + 0001 => 1 MP CG.CC_COMBINEDSTRAPS.MAX_MPS[7:5] = 111 => + max_mps[3:0] = 0000 => 0 MP Note that max_mps[3:0] = 0111 + = 7 MPs is not available</doc> + <bitfield high="24" low="24" name="VS_BUSY" /> + <doc>Vertex Store is Busy. Read-only.</doc> + <bitfield high="25" low="25" name="RCP_BUSY" /> + <doc>Reciprocal Engine is Busy. Read-only.</doc> + <bitfield high="26" low="26" name="VTE_BUSY" /> + <doc>ViewPort Transform Engine is Busy. Read-only.</doc> + <bitfield high="27" low="27" name="MIU_BUSY" /> + <doc>Memory Interface Unit is Busy. Read-only.</doc> + <bitfield high="28" low="28" name="VC_BUSY" /> + <doc>Vertex Cache is Busy. Read-only.</doc> + <bitfield high="29" low="29" name="VF_BUSY" /> + <doc>Vertex Fetcher is Busy. Read-only.</doc> + <bitfield high="30" low="30" name="REGPIPE_BUSY" /> + <doc>Register Pipeline is Busy. Read-only.</doc> + <bitfield high="31" low="31" name="VAP_BUSY" /> + <doc>VAP Engine is Busy. Read-only.</doc> + </reg32> + <reg32 access="rw" name="VAP_INDEX_OFFSET" offset="0x208C"> + <doc>Offset Value added to index value in both Indexed and + Auto-indexed modes. Disabled by setting to 0</doc> + <bitfield high="24" low="0" name="INDEX_OFFSET" /> + <doc>25-bit signed 2`s comp offset value</doc> + </reg32> + <stripe length="8" offset="0x2150" stride="0x0004"> + <reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0"> + <doc>Programmable Stream Control Word 0</doc> + <bitfield high="3" low="0" name="DATA_TYPE_0" /> + <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE + Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE + Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 + 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = + [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except + has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y + = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD + with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], + Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per + dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 + [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT + * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y + = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 + DWORD with 2 11-bit and 1 10-bit fixed point values) (X = + [10:0], Y = [21:11], Z = [31:22], W = 1.0) 10 = FLOAT_8 (8 + IEEE Floats) Sames as 2 FLOAT_4 but must use consecutive + DST_VEC_LOC. Used to allow > 16 PSC for OGL path. 11 = + FLT16_2 (1 DWORD with 2 16-bit floating point values + (SE5M10 exp bias of 15, supports denormalized numbers)) (X + = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 12 = FLT16_4 (2 + DWORDS with 4(2 per dword) 16-bit floating point values + (SE5M10 exp bias of 15, supports denormalized numbers))) (X + = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 + [31:16]) * These data types use the SIGNED and NORMALIZE + flags described below.</doc> + <bitfield high="7" low="4" name="SKIP_DWORDS_0" /> + <doc>The number of DWORDS to skip (discard) after + processing the current element.</doc> + <bitfield high="12" low="8" name="DST_VEC_LOC_0" /> + <doc>The vector address in the input memory to write this + element</doc> + <bitfield high="13" low="13" name="LAST_VEC_0" /> + <doc>If set, indicates the last vector of the current + vertex stream</doc> + <bitfield high="14" low="14" name="SIGNED_0" /> + <doc>Determines whether fixed point data types are unsigned + (0) or 2`s complement signed (1) data types. See NORMALIZE + for complete description of affect</doc> + <bitfield high="15" low="15" name="NORMALIZE_0"> + <use-enum ref="ENUM185" /> + </bitfield> + <doc>Determines whether the fixed to floating point + conversion will normalize the value (i.e. fixed point value + is all fractional bits) or not (i.e. fixed point value is + all integer bits). This table describes the fixed to float + conversion results SIGNED NORMALIZE FLT RANGE 0 0 0.0 - + (2^n - 1) (i.e. 8-bit -> 0.0 - 255.0) 0 1 0.0 - 1.0 1 0 + -2^(n-1) - (2^(n-1) - 1) (i.e. 8-bit -> -128.0 - 127.0) + 1 1 -1.0 - 1.0 where n is the number of bits in the + associated fixed point value For signed, normalize + conversion, since the fixed point range is not evenly + distributed around 0, there are 3 different methods + supported by R300. See the VAP_PSC_SGN_NORM_CNTL + description for details.</doc> + <bitfield high="19" low="16" name="DATA_TYPE_1" /> + <doc>Similar to DATA_TYPE_0</doc> + <bitfield high="23" low="20" name="SKIP_DWORDS_1" /> + <doc>See SKIP_DWORDS_0</doc> + <bitfield high="28" low="24" name="DST_VEC_LOC_1" /> + <doc>See DST_VEC_LOC_0</doc> + <bitfield high="29" low="29" name="LAST_VEC_1" /> + <doc>See LAST_VEC_0</doc> + <bitfield high="30" low="30" name="SIGNED_1" /> + <doc>See SIGNED_0</doc> + <bitfield high="31" low="31" name="NORMALIZE_1" /> + <doc>See NORMALIZE_0</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x2500" stride="0x0008"> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_LW" + offset="0x0"> + <doc>For VS3.0 - To support more PVS instructions, increase + the address range - Programmable Vertex Shader Flow Control + Lower Word Addresses Register 0</doc> + <bitfield high="15" low="0" name="PVS_FC_ACT_ADRS_0"> + <use-enum ref="ENUM313" /> + </bitfield> + <doc>This field defines the last PVS instruction to execute + prior to the control flow redirection. JUMP - The last + instruction executed prior to the jump LOOP - The last + instruction executed prior to the loop (init loop + counter/inc) JSR - The last instruction executed prior to + the jump to the subroutine. + (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> + <bitfield high="31" low="16" + name="PVS_FC_LOOP_CNT_JMP_INST_0"> + <use-enum ref="ENUM314" /> + </bitfield> + <doc>This field has multiple definitions as follows: JUMP - + The instruction address to jump to. LOOP - The loop count. + *Note loop count of 0 must be replaced by a jump. JSR - The + instruction address to jump to (first inst of subroutine). + (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x2504" stride="0x0008"> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_UW" + offset="0x0"> + <doc>For VS3.0 - To support more PVS instructions, increase + the address range - Programmable Vertex Shader Flow Control + Upper Word Addresses Register 0</doc> + <bitfield high="15" low="0" name="PVS_FC_LAST_INST_0"> + <use-enum ref="ENUM313" /> + </bitfield> + <doc>This field has multiple definitions as follows: JUMP - + Not Applicable LOOP - The last instruction of the loop. JSR + - The last instruction of the subroutine. + (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> + <bitfield high="31" low="16" name="PVS_FC_RTN_INST_0"> + <use-enum ref="ENUM314" /> + </bitfield> + <doc>This field has multiple definitions as follows: JUMP - + Not Applicable LOOP - First Instruction of Loop (Typically + ACT_ADRS + 1) JSR - First Instruction After JSR (Typically + ACT_ADRS + 1). + (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> + </reg32> + </stripe> + <stripe length="16" offset="0x2290" stride="0x0004"> + <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" + offset="0x0"> + <doc>Programmable Vertex Shader Flow Control Loop Index + Register 0</doc> + <bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" /> + <doc>This field stores the automatic loop index register + init value. This is an 8-bit unsigned value 0-255. This + field is only used if the corresponding control flow + instruction is a loop.</doc> + <bitfield high="15" low="8" + name="PVS_FC_LOOP_STEP_VAL_0" /> + <doc>This field stores the automatic loop index register + step value. This is an 8-bit 2`s comp signed value + -128-127. This field is only used if the corresponding + control flow instruction is a loop.</doc> + <bitfield high="31" low="31" + name="PVS_FC_LOOP_REPEAT_NO_FLI_0" /> + <doc>When this field is set, the automatic loop index + register init value is not used at loop activation. The + intial loop index is inherited from outer loop. The loop + index register step value is used at the end of each loop + iteration ; after loop completion, the outer loop index + register is restored</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_TEX_TO_COLOR_CNTL" + offset="0x2218"> + <doc>For VS3.0 color2texture - flat shading on textures - + limitation: only first 8 vectors can have clipping with wrap + shortest or point sprite generated textures</doc> + </reg32> + <reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084"> + <doc>Vertex Fetcher Control</doc> + <bitfield high="3" low="0" name="PRIM_TYPE" /> + <doc>Primitive Type 0 : None (will not trigger Setup Engine + to run) 1 : Point List 2 : Line List 3 : Line Strip 4 : + Triangle List 5 : Triangle Fan 6 : Triangle Strip 7 : + Triangle with wFlags (aka, Rage128 `Type-2` triangles) * 8-11 + : Unused 12 : Line Loop 13 : Quad List 14 : Quad Strip 15 : + Polygon *Encoding 7 indicates whether a 16-bit word of wFlags + is present in the stream of indices arriving when the + VTX_AMODE is programmed as a `0`. The Setup Engine just steps + over the wFlags word; ignoring it. 0 = Stream contains just + indices, as: [ Index1, Index0] [ Index3, Index2] [ Index5, + Index4 ] etc... 1 = Stream contains indices and wFlags: [ + Index1, Index0] [ wFlags,Index 2 ] [ Index4, Index3] [ + wFlags, Index5 ] etc...</doc> + <bitfield high="5" low="4" name="PRIM_WALK" /> + <doc>Method of Passing Vertex Data. 0 : State-Based Vertex + Data. (Vertex data and tokens embedded in command stream.) 1 + = Indexes (Indices embedded in command stream; vertex data to + be fetched from memory.) 2 = Vertex List (Vertex data to be + fetched from memory.) 3 = Vertex Data (Vertex data embedded + in command stream.)</doc> + <bitfield high="10" low="6" name="RSVD_PREV_USED" /> + <doc>Reserved bits</doc> + <bitfield high="11" low="11" name="INDEX_SIZE" /> + <doc>When set, vertex indices are 32-bits/indx, otherwise, + 16- bits/indx.</doc> + <bitfield high="12" low="12" name="VTX_REUSE_DIS" /> + <doc>When set, vertex reuse is disabled. DO NOT SET unless + PRIM_WALK is Indexes.</doc> + <bitfield high="13" low="13" name="DUAL_INDEX_MODE" /> + <doc>When set, the incoming index is treated as two separate + indices. Bits 23-16 are used as the index for AOS 0 (These + are 0 for 16-bit indices) Bits 15-0 are used as the index for + AOS 1-15. This mode was added specifically for HOS + usage</doc> + <bitfield high="14" low="14" name="USE_ALT_NUM_VERTS" /> + <doc>When set, the number of vertices in the command packet + is taken from VAP_ALT_NUM_VERTICES register instead of bits + 31:16 of VAP_VF_CNTL</doc> + <bitfield high="31" low="16" name="NUM_VERTICES" /> + <doc>Number of vertices in the command packet.</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0"> + <doc>Vertex Array of Structures Control</doc> + <bitfield high="4" low="0" name="VTX_NUM_ARRAYS" /> + <doc>The number of arrays required to represent the current + vertex type. Each Array is described by the following three + fields: VTX_AOS_ADDR, VTX_AOS_COUNT, VTX_AOS_STRIDE.</doc> + <bitfield high="5" low="5" name="VC_FORCE_PREFETCH" /> + <doc>Force Vertex Data Pre-fetching. If this bit is set, then + a 256-bit word will always be fetched, regardless of which + dwords are needed. Typically useful when + VAP_VF_CNTL.PRIM_WALK is set to Vertex List (Auto-incremented + indices).</doc> + <bitfield high="6" low="6" name="VC_DIS_CACHE_INVLD" /> + <doc>If set, the vertex cache is not invalidated between draw + packets. This allows vertex cache hits to occur from packet + to packet. This must be set with caution with respect to + multiple contexts in the driver.</doc> + <bitfield high="16" low="16" name="AOS_0_FETCH_SIZE" /> + <doc>Granule Size to Fetch for AOS 0. 0 = 128-bit granule + size 1 = 256-bit granule size This allows the driver to + program the fetch size based on DWORDS/VTX/AOS combined with + AGP vs. LOC Memory. The general belief is that the granule + size should always be 256-bits for LOC memory and AGP8X data, + but should be 128-bit for AGP2X/4X data if the DWORDS/VTX/AOS + is less than TBD (128?) bits.</doc> + <bitfield high="17" low="17" name="AOS_1_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="18" low="18" name="AOS_2_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="19" low="19" name="AOS_3_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="20" low="20" name="AOS_4_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="21" low="21" name="AOS_5_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="22" low="22" name="AOS_6_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="23" low="23" name="AOS_7_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="24" low="24" name="AOS_8_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="25" low="25" name="AOS_9_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="26" low="26" name="AOS_10_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="27" low="27" name="AOS_11_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="28" low="28" name="AOS_12_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="29" low="29" name="AOS_13_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + <bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" /> + <doc>See AOS_0_FETCH_SIZE</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180"> + <doc>VAP Vertex State Control Register</doc> + <bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="3" low="2" name="COLOR_1_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 1 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="5" low="4" name="COLOR_2_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 2 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="7" low="6" name="COLOR_3_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 3 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="9" low="8" name="COLOR_4_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 4 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="11" low="10" name="COLOR_5_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 5 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="13" low="12" name="COLOR_6_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 6 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="15" low="14" name="COLOR_7_ASSEMBLY_CNTL" /> + <doc>0 : Select Color 7 1 : Select User Color 0 2 : Select + User Color 1 3 : Reserved</doc> + <bitfield high="16" low="16" + name="UPDATE_USER_COLOR_0_ENA" /> + <doc>0 : User Color 0 State is NOT updated when User Color 0 + is written. 1 : User Color 1 State IS updated when User Color + 0 is written.</doc> + <bitfield high="18" low="18" name="Reserved" /> + <doc>Set to 0</doc> + </reg32> + <stripe length="4" offset="0x2430" stride="0x0004"> + <reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x232C" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x2328" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x2324" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x2470" stride="0x0004"> + <reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x2320" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_EDGE_FLAGS" + offset="0x245C"> + <doc>Data register</doc> + <bitfield high="0" low="0" name="DATA_REGISTER" /> + <doc>EDGE_FLAGS</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" offset="0x24AC"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" offset="0x2498"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" offset="0x2310"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" offset="0x2314"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" offset="0x2318"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" offset="0x2450"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" offset="0x2454"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" offset="0x2458"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_PNT_SPRT_SZ" + offset="0x2420"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" offset="0x230C"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" offset="0x2490"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" offset="0x24A0"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" offset="0x2300"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" offset="0x2494"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" offset="0x24A4"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" offset="0x2304"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" offset="0x24A8"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" offset="0x2308"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" + offset="0x2428"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" + offset="0x242C"> + <doc>Data register</doc> + </reg32> + <stripe length="8" offset="0x23AC" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x23A8" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x23A0" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <stripe length="8" offset="0x23A4" stride="0x0010"> + <reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0"> + <doc>Data register</doc> + </reg32> + </stripe> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" offset="0x2468"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464"> + <doc>Data register</doc> + </reg32> + <reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" + offset="0x249C"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460"> + <doc>Data register</doc> + </reg32> + <reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C"> + <doc>Z Buffer Band-Width Control Defa</doc> + <bitfield high="0" low="0" name="HIZ_ENABLE"> + <use-enum ref="ENUM187" /> + </bitfield> + <doc>Enables hierarchical Z.</doc> + <bitfield high="1" low="1" name="HIZ_MIN"> + <use-enum ref="ENUM188" /> + </bitfield> + <doc /> + <bitfield high="2" low="2" name="FAST_FILL"> + <use-enum ref="ENUM189" /> + </bitfield> + <doc /> + <bitfield high="3" low="3" name="RD_COMP_ENABLE"> + <use-enum ref="ENUM190" /> + </bitfield> + <doc>Enables reading of compressed Z data from memory to the + cache.</doc> + <bitfield high="4" low="4" name="WR_COMP_ENABLE"> + <use-enum ref="ENUM191" /> + </bitfield> + <doc>Enables writing of compressed Z data from cache to + memory,</doc> + <bitfield high="5" low="5" name="ZB_CB_CLEAR"> + <use-enum ref="ENUM192" /> + </bitfield> + <doc>This bit is set when the Z buffer is used to help the CB + in clearing a region. Part of the region is cleared by the + color buffer and part will be cleared by the Z buffer. Since + the Z buffer does not have any write masks in the cache, full + micro- tiles need to be written. If a partial micro-tile is + touched, then the un-touched part will be unknowns. The cache + will operate in write-allocate mode and quads will be + accumulated in the cache and then evicted to main memory. The + color value is supplied through the ZB_DEPTHCLEARVALUE + register.</doc> + <bitfield high="6" low="6" + name="FORCE_COMPRESSED_STENCIL_V" /> + <doc>Enabling this bit will force all the compressed stencil + values</doc> + <bitfield high="7" low="7" name="ZEQUAL_OPTIMIZE_DISABLE"> + <value name="ENABLE_NOT_UPDATING_THE_Z_BUFFER_IF_NEWZ" + value="0"> + <doc>Enable not updating the Z buffer if NewZ=OldZ</doc> + </value> + <value name="DISABLE_ABOVE_FEATURE" value="1"> + <doc>Disable above feature (in case there is a bug)</doc> + </value> + </bitfield> + <doc>By default this is 0 (enabled). When NEWZ=OLDZ, then + writes do not occur to save BW.</doc> + <bitfield high="8" low="8" name="SEQUAL_OPTIMIZE_DISABLE"> + <value name="ENABLE_NOT_UPDATING_THE_STENCIL_BUFFER_IF_NEWS" + value="0"> + <doc>Enable not updating the Stencil buffer if + NewS=OldS</doc> + </value> + <value name="DISABLE_ABOVE_FEATURE" value="1"> + <doc>Disable above feature (in case there is a bug)</doc> + </value> + </bitfield> + <doc>By default this is 0 (enabled). When + NEW_STENCIL=OLD_STENCIL, then writes do not occur to save + BW.</doc> + <bitfield high="10" low="10" name="BMASK_DISABLE"> + <value name="ENABLE_BYTEMASKING" value="0"> + <doc>Enable bytemasking</doc> + </value> + <value name="DISABLE_BYTEMASKING" value="1"> + <doc>Disable bytemasking</doc> + </value> + </bitfield> + <doc>Controls whether bytemasking is used or not.</doc> + <bitfield high="11" low="11" name="HIZ_EQUAL_REJECT_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables hiz rejects when the z function is equals.</doc> + <bitfield high="15" low="15" name="HIZ_FP_INVERT"> + <value name="COUNT_LEADING_1S" value="0"> + <doc>Count leading 1s</doc> + </value> + <value name="COUNT_LEADING_0S" value="1"> + <doc>Count leading 0s</doc> + </value> + </bitfield> + <doc>Determines whether leading zeros or ones are + eliminated.</doc> + <bitfield high="16" low="16" + name="TILE_OVERWRITE_RECOMPRESSI" /> + <doc>The zb tries to detect single plane equations that + completely</doc> + <bitfield high="17" low="17" + name="CONTIGUOUS_6XAA_SAMPLES_DI" /> + <doc>This disables storing samples contiguously in + 6xaa.</doc> + <bitfield high="18" low="18" name="PEQ_PACKING_ENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables packing of the plane equations to eliminate + wasted peq slots.</doc> + <bitfield high="19" low="19" + name="COVERED_PTR_MASKING_ENABL" /> + <doc>Enables discarding of pointers from pixels that are + going to be</doc> + </reg32> + <reg32 access="rw" name="ZB_CNTL" offset="0x4F00"> + <doc>Z Buffer Control</doc> + <bitfield high="0" low="0" name="STENCIL_ENABLE"> + <use-enum ref="ENUM178" /> + </bitfield> + <doc>Enables stenciling.</doc> + <bitfield high="1" low="1" name="Z_ENABLE"> + <use-enum ref="ENUM178" /> + </bitfield> + <doc>Enables Z functions.</doc> + <bitfield high="2" low="2" name="ZWRITEENABLE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enables writing of the Z buffer.</doc> + <bitfield high="3" low="3" name="ZSIGNED_COMPARE"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Enable signed Z buffer comparison , for + W-buffering.</doc> + <bitfield high="4" low="4" name="STENCIL_FRONT_BACK"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>When STENCIL_ENABLE is set, setting STENCIL_FRONT_BACK + bit to one specifies that + stencilfunc/stencilfail/stencilzpass/stencilzfail registers + are used if the quad is generated from front faced primitive + and + stencilfunc_bf/stencilfail_bf/stencilzpass_bf/stencilzfail_bf + are used if the quad is generated from a back faced + primitive. If the STENCIL_FRONT_BACK is not set, then + stencilfunc/stencilfail/stencilzpass/stencilzfail registers + determine the operation independent of the front/back face + state of the quad.</doc> + <bitfield high="5" low="5" name="ZSIGNED_MAGNITUDE"> + <value name="TWOS_COMPLEMENT" value="0"> + <doc>Twos complement</doc> + </value> + <value name="SIGNED_MAGNITUDE" value="1"> + <doc>Signed magnitude</doc> + </value> + </bitfield> + <doc>Specifies the signed number type to use for the Z buffer + comparison. This only has an effect when ZSIGNED_COMPARE is + enabled.</doc> + <bitfield high="6" low="6" name="STENCIL_REFMASK_FRONT_BACK"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc /> + </reg32> + <reg32 access="rw" name="ZB_FIFO_SIZE" offset="0x4FD0"> + <doc>Sets the fifo sizes</doc> + <bitfield high="1" low="0" name="OP_FIFO_SIZE"> + <use-enum ref="ENUM216" /> + </bitfield> + <doc>Determines the size of the op fifo</doc> + </reg32> + <reg32 access="rw" name="ZB_FORMAT" offset="0x4F10"> + <doc>Format of the Data in the Z buffer</doc> + <bitfield high="3" low="0" name="DEPTHFORMAT"> + <use-enum ref="ENUM196" /> + </bitfield> + <doc>Specifies the format of the Z buffer.</doc> + <bitfield high="4" low="4" name="INVERT"> + <value name="IN_13E3_FORMAT" value="0"> + <doc>in 13E3 format , count leading 1`s</doc> + </value> + <value name="IN_13E3_FORMAT" value="1"> + <doc>in 13E3 format , count leading 0`s.</doc> + </value> + </bitfield> + <doc /> + <bitfield high="5" low="5" name="PEQ8" /> + <doc>This bit is unused</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44"> + <doc>Hierarchical Z Memory Offset</doc> + <bitfield high="17" low="2" name="HIZ_OFFSET" /> + <doc>DWORD offset into HiZ RAM.</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50"> + <doc>Hierarchical Z Read Index</doc> + <bitfield high="17" low="2" name="HIZ_RDINDEX" /> + <doc>Read index into HiZ RAM.</doc> + </reg32> + <reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48"> + <doc>Hierarchical Z Write Index</doc> + <bitfield high="17" low="2" name="HIZ_WRINDEX" /> + <doc>Self-incrementing write index into the HiZ RAM. Starting + write index must start on a DWORD boundary. Each time + ZB_HIZ_DWORD is written, this index will autoincrement. + HIZ_OFFSET and HIZ_PITCH are not used to compute read/write + address to HIZ ram, when it is accessed through WRINDEX and + DWORD</doc> + </reg32> + <reg32 access="rw" name="ZB_STENCILREFMASK_BF" offset="0x4FD4"> + <doc>Stencil Reference Value and Mask for backfacing + quads</doc> + <bitfield high="7" low="0" name="STENCILREF" /> + <doc>Specifies the reference stencil value.</doc> + <bitfield high="15" low="8" name="STENCILMASK" /> + <doc>This value is ANDed with both the reference and the + current stencil value prior to the stencil test.</doc> + <bitfield high="23" low="16" name="STENCILWRITEMASK" /> + <doc>Specifies the write mask for the stencil planes.</doc> + </reg32> + <reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04"> + <doc>Z and Stencil Function Control</doc> + <bitfield high="2" low="0" name="ZFUNC"> + <use-enum ref="ENUM202" /> + </bitfield> + <doc>Specifies the Z function.</doc> + <bitfield high="5" low="3" name="STENCILFUNC"> + <use-enum ref="ENUM203" /> + </bitfield> + <doc>Specifies the stencil function.</doc> + <bitfield high="8" low="6" name="STENCILFAIL"> + <use-enum ref="ENUM204" /> + </bitfield> + <doc>Specifies the stencil value to be written if the stencil + test fails.</doc> + <bitfield high="11" low="9" name="STENCILZPASS" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled).</doc> + <bitfield high="14" low="12" name="STENCILZFAIL" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails.</doc> + <bitfield high="17" low="15" name="STENCILFUNC_BF" /> + <doc>Same encoding as STENCILFUNC. Specifies the stencil + function for back faced quads , if STENCIL_FRONT_BACK = + 1.</doc> + <bitfield high="20" low="18" name="STENCILFAIL_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test fails for back faced + quads, if STENCIL_FRONT_BACK = 1</doc> + <bitfield high="23" low="21" name="STENCILZPASS_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + passes (or is not enabled) for back faced quads, if + STENCIL_FRONT_BACK = 1</doc> + <bitfield high="26" low="24" name="STENCILZFAIL_BF" /> + <doc>Same encoding as STENCILFAIL. Specifies the stencil + value to be written if the stencil test passes and the Z test + fails for back faced quads, if STENCIL_FRONT_BACK =1</doc> + <bitfield high="27" low="27" name="ZERO_OUTPUT_MASK"> + <use-enum ref="ENUM5" /> + </bitfield> + <doc>Zeroes the zb coverage mask output. This does not affect + the updating of the depth or stencil values.</doc> + </reg32> + </group> + <variant id="r300"> + <use-group ref="rX00_regs" /> + <use-group ref="r300_regs" /> + </variant> + <variant id="r500"> + <use-group ref="rX00_regs" /> + <use-group ref="r500_regs" /> + </variant> </database> diff --git a/radeonreg.py b/radeonreg.py index ae875fc..ca7e87d 100755 --- a/radeonreg.py +++ b/radeonreg.py @@ -215,7 +215,7 @@ def CreateXML(handle, regs, variants): """ This file was automatically generated from radeonreg.py. -I strongly suggest running "tidy -m -xml 'name_of_file.xml'" on this file +I strongly suggest running "tidy -i -m -xml 'name_of_file.xml'" on this file before attempting to read it. ~ C. |