Fix up more schema problems.

2 files changed, 1367 insertions, 999 deletions

diff --git a/r300reg.xml b/r300reg.xml
index 65be720..75beac2 100644
--- a/r300reg.xml
+++ b/r300reg.xml
@@ -2087,18 +2087,22 @@ value.</doc>
 </enum>
 <group name="rX00_regs" prepend="R300_">
 <reg32 access="rw" name="RB3D_AARESOLVE_OFFSET" offset="0x4E80">
-Resolve buffer destination address. The cache must be empty before
-changing this register if the cb is in resolve mode. Unpipelined
+<doc>Resolve buffer destination address. The cache must be empty
+before changing this register if the cb is in resolve mode.
+Unpipelined</doc>
 <bitfield high="31" low="5" name="AARESOLVE_OFFSET" />
-<doc>256-bit aligned 3D resolve destination offset.</doc></reg32>
+<doc>256-bit aligned 3D resolve destination offset.</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_AARESOLVE_PITCH" offset="0x4E84">
-Resolve Buffer Pitch and Tiling Control. The cache must be empty
-before changing this register if the cb is in resolve mode.
-Unpipelined
+<doc>Resolve Buffer Pitch and Tiling Control. The cache must be
+empty before changing this register if the cb is in resolve mode.
+Unpipelined</doc>
 <bitfield high="13" low="1" name="AARESOLVE_PITCH" />
-<doc>3D destination pitch in multiples of 2-pixels.</doc></reg32>
-<reg32 access="rw" name="RB3D_ABLENDCNTL" offset="0x4E08">Alpha
-Blend Control for Alpha Channel. Pipelined through the blender.
+<doc>3D destination pitch in multiples of 2-pixels.</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_ABLENDCNTL" offset="0x4E08">
+<doc>Alpha Blend Control for Alpha Channel. Pipelined through the
+blender.</doc>
 <bitfield high="14" low="12" name="COMB_FCN">
 <use-enum ref="ENUM2" />
 </bitfield>
@@ -2112,22 +2116,32 @@ DESTBLEND are combined.</doc>
 <use-enum ref="ENUM4" />
 </bitfield>
 <doc>Destination Blend Function , Alpha blending function
-(DST).</doc></reg32>
-<reg32 access="rw" name="RB3D_CLRCMP_CLR" offset="0x4E20">Color
-Compare Color. Stalls the 2d/3d datapath until it is idle.</reg32>
-<reg32 access="rw" name="RB3D_CLRCMP_FLIPE" offset="0x4E1C">Color
-Compare Flip. Stalls the 2d/3d datapath until it is idle.</reg32>
-<reg32 access="rw" name="RB3D_CLRCMP_MSK" offset="0x4E24">Color
-Compare Mask. Stalls the 2d/3d datapath until it is idle.</reg32>
-<stripe addr="0x4E28" length="4" stride="0x0004">
-<reg32 access="rw" name="RB3D_COLOROFFSET" offset="0x0">Color
-Buffer Address Offset of multibuffer 0. Unpipelined.
+(DST).</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_CLRCMP_CLR" offset="0x4E20">
+<doc>Color Compare Color. Stalls the 2d/3d datapath until it is
+idle.</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_CLRCMP_FLIPE" offset="0x4E1C">
+<doc>Color Compare Flip. Stalls the 2d/3d datapath until it is
+idle.</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_CLRCMP_MSK" offset="0x4E24">
+<doc>Color Compare Mask. Stalls the 2d/3d datapath until it is
+idle.</doc>
+</reg32>
+<stripe length="4" offset="0x4E28" stride="0x0004">
+<reg32 access="rw" name="RB3D_COLOROFFSET" offset="0x0">
+<doc>Color Buffer Address Offset of multibuffer 0.
+Unpipelined.</doc>
 <bitfield high="31" low="5" name="COLOROFFSET" />
 <doc>256-bit aligned 3D destination offset address. The cache must
-be empty before this is changed.</doc></reg32>
+be empty before this is changed.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="RB3D_DITHER_CTL" offset="0x4E50">Dithering
-control register. Pipelined through the blender.
+<reg32 access="rw" name="RB3D_DITHER_CTL" offset="0x4E50">
+<doc>Dithering control register. Pipelined through the
+blender.</doc>
 <bitfield high="1" low="0" name="DITHER_MODE">
 <use-enum ref="ENUM17" />
 </bitfield>
@@ -2135,15 +2149,17 @@ control register. Pipelined through the blender.
 <bitfield high="3" low="2" name="ALPHA_DITHER_MODE">
 <use-enum ref="ENUM17" />
 </bitfield>
-<doc /></reg32>
+<doc />
+</reg32>
 <reg32 access="rw" name="RB3D_DSTCACHE_CTLSTAT" offset="0x4E4C">
-Destination Color Buffer Cache Control/Status. If the cb is in e2
-mode, then a flush or free will not occur upon a write to this
+<doc>Destination Color Buffer Cache Control/Status. If the cb is in
+e2 mode, then a flush or free will not occur upon a write to this
 register, but a sync will be immediately sent if one is requested.
 If both DC_FLUSH and DC_FREE are zero but DC_FINISH is one, then a
 sync will be sent immediately -- the cb will not wait for all the
 previous operations to complete before sending the sync.
-Unpipelined except when DC_FINISH and DC_FREE are both set to zero.
+Unpipelined except when DC_FINISH and DC_FREE are both set to
+zero.</doc>
 <bitfield high="1" low="0" name="DC_FLUSH">
 <value name="NO_EFFECT" value="0">
 <doc>No effect</doc>
@@ -2190,9 +2206,11 @@ value="1">
 operation</doc>
 </value>
 </bitfield>
-<doc /></reg32>
-<reg32 access="rw" name="RB3D_ROPCNTL" offset="0x4E18">3D ROP
-Control. Stalls the 2d/3d datapath until it is idle.
+<doc />
+</reg32>
+<reg32 access="rw" name="RB3D_ROPCNTL" offset="0x4E18">
+<doc>3D ROP Control. Stalls the 2d/3d datapath until it is
+idle.</doc>
 <bitfield high="2" low="2" name="ROP_ENABLE">
 <value name="DISABLE_ROP" value="0">
 <doc>Disable ROP. (Forces ROP2 to be 0xC).</doc>
@@ -2205,9 +2223,10 @@ Control. Stalls the 2d/3d datapath until it is idle.
 <bitfield high="11" low="8" name="ROP" />
 <doc>ROP2 code for 3D fragments. This value is replicated into 2
 nibbles to form the equivalent ROP3 code to control the ROP3 logic.
-These are the GDI ROP2 codes.</doc></reg32>
-<reg32 access="rw" name="FG_DEPTH_SRC" offset="0x4BD8">Where does
-depth come from?
+These are the GDI ROP2 codes.</doc>
+</reg32>
+<reg32 access="rw" name="FG_DEPTH_SRC" offset="0x4BD8">
+<doc>Where does depth come from?</doc>
 <bitfield high="0" low="0" name="DEPTH_SRC">
 <value name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE_EQUATION"
 value="0">
@@ -2218,9 +2237,10 @@ value="1">
 <doc>Depth comes from shader as four discrete values.</doc>
 </value>
 </bitfield>
-<doc /></reg32>
-<reg32 access="rw" name="FG_FOG_BLEND" offset="0x4BC0">Fog Blending
-Enable
+<doc />
+</reg32>
+<reg32 access="rw" name="FG_FOG_BLEND" offset="0x4BC0">
+<doc>Fog Blending Enable</doc>
 <bitfield high="0" low="0" name="ENABLE">
 <value name="DISABLES_FOG" value="0">
 <doc>Disables fog (output matches input color).</doc>
@@ -2244,9 +2264,10 @@ Enable
 <doc>Fog is derived from constant fog factor</doc>
 </value>
 </bitfield>
-<doc>Fog generation function</doc></reg32>
+<doc>Fog generation function</doc>
+</reg32>
 <reg32 access="rw" name="GA_COLOR_CONTROL" offset="0x4278">
-Specifies per RGB or Alpha shading method.
+<doc>Specifies per RGB or Alpha shading method.</doc>
 <bitfield high="1" low="0" name="RGB0_SHADING">
 <use-enum ref="ENUM30" />
 </bitfield>
@@ -2294,19 +2315,24 @@ Specifies per RGB or Alpha shading method.
 </value>
 </bitfield>
 <doc>Specifies, for flat shaded polygons, which vertex holds the
-polygon color.</doc></reg32>
-<reg32 access="rw" name="GA_FOG_OFFSET" offset="0x4298">Specifies
-the offset to apply to fog.</reg32>
-<reg32 access="rw" name="GA_FOG_SCALE" offset="0x4294">Specifies
-the scale to apply to fog.</reg32>
-<reg32 access="rw" name="GA_LINE_S0" offset="0x4264">S Texture
-Coordinate Value for Vertex 0 of Line (stuff textures -- i.e.
-AA)</reg32>
-<reg32 access="rw" name="GA_LINE_S1" offset="0x4268">S Texture
-Coordinate Value for Vertex 1 of Lines (V2 of parallelogram --
-stuff textures -- i.e. AA)</reg32>
+polygon color.</doc>
+</reg32>
+<reg32 access="rw" name="GA_FOG_OFFSET" offset="0x4298">
+<doc>Specifies the offset to apply to fog.</doc>
+</reg32>
+<reg32 access="rw" name="GA_FOG_SCALE" offset="0x4294">
+<doc>Specifies the scale to apply to fog.</doc>
+</reg32>
+<reg32 access="rw" name="GA_LINE_S0" offset="0x4264">
+<doc>S Texture Coordinate Value for Vertex 0 of Line (stuff
+textures -- i.e. AA)</doc>
+</reg32>
+<reg32 access="rw" name="GA_LINE_S1" offset="0x4268">
+<doc>S Texture Coordinate Value for Vertex 1 of Lines (V2 of
+parallelogram -- stuff textures -- i.e. AA)</doc>
+</reg32>
 <reg32 access="rw" name="GA_LINE_STIPPLE_CONFIG" offset="0x4238">
-Line Stipple configuration information.
+<doc>Line Stipple configuration information.</doc>
 <bitfield high="1" low="0" name="LINE_RESET">
 <value name="NO_RESETING" value="0">
 <doc>No reseting</doc>
@@ -2321,27 +2347,39 @@ Line Stipple configuration information.
 <doc>Specify type of reset to use for stipple accumulation.</doc>
 <bitfield high="31" low="2" name="STIPPLE_SCALE" />
 <doc>Specifies, in truncated (30b) floating point, scale to apply
-to generated texture coordinates.</doc></reg32>
+to generated texture coordinates.</doc>
+</reg32>
 <reg32 access="rw" name="GA_LINE_STIPPLE_VALUE" offset="0x4260">
-Current value of stipple accumulator.</reg32>
-<reg32 access="rw" name="GA_POINT_MINMAX" offset="0x4230">Specifies
-maximum and minimum point &amp; sprite sizes for per vertex size
-specification.
+<doc>Current value of stipple accumulator.</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_MINMAX" offset="0x4230">
+<doc>Specifies maximum and minimum point &amp; sprite sizes for per
+vertex size specification.</doc>
 <bitfield high="15" low="0" name="MIN_SIZE" />
 <doc>Minimum point &amp; sprite radius (in subsamples) size to
 allow.</doc>
 <bitfield high="31" low="16" name="MAX_SIZE" />
 <doc>Maximum point &amp; sprite radius (in subsamples) size to
-allow.</doc></reg32>
-<reg32 access="rw" name="GA_POINT_S0" offset="0x4200">S Texture
-Coordinate of Vertex 0 for Point texture stuffing (LLC)</reg32>
-<reg32 access="rw" name="GA_POINT_S1" offset="0x4208">S Texture
-Coordinate of Vertex 2 for Point texture stuffing (URC)</reg32>
-<reg32 access="rw" name="GA_POINT_T0" offset="0x4204">T Texture
-Coordinate of Vertex 0 for Point texture stuffing (LLC)</reg32>
-<reg32 access="rw" name="GA_POINT_T1" offset="0x420C">T Texture
-Coordinate of Vertex 2 for Point texture stuffing (URC)</reg32>
-<reg32 access="rw" name="GA_POLY_MODE" offset="0x4288">Polygon Mode
+allow.</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_S0" offset="0x4200">
+<doc>S Texture Coordinate of Vertex 0 for Point texture stuffing
+(LLC)</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_S1" offset="0x4208">
+<doc>S Texture Coordinate of Vertex 2 for Point texture stuffing
+(URC)</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_T0" offset="0x4204">
+<doc>T Texture Coordinate of Vertex 0 for Point texture stuffing
+(LLC)</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_T1" offset="0x420C">
+<doc>T Texture Coordinate of Vertex 2 for Point texture stuffing
+(URC)</doc>
+</reg32>
+<reg32 access="rw" name="GA_POLY_MODE" offset="0x4288">
+<doc>Polygon Mode</doc>
 <bitfield high="1" low="0" name="POLY_MODE">
 <value name="DISABLE_POLY_MODE" value="0">
 <doc>Disable poly mode (render triangles).</doc>
@@ -2359,17 +2397,19 @@ type).</doc>
 <bitfield high="9" low="7" name="BACK_PTYPE">
 <use-enum ref="ENUM37" />
 </bitfield>
-<doc>Specifies how to render back-facing polygons.</doc></reg32>
+<doc>Specifies how to render back-facing polygons.</doc>
+</reg32>
 <reg32 access="rw" name="GA_TRIANGLE_STIPPLE" offset="0x4214">
-Specifies amount to shift integer position of vertex (screen space)
-before converting to float for triangle stipple.
+<doc>Specifies amount to shift integer position of vertex (screen
+space) before converting to float for triangle stipple.</doc>
 <bitfield high="3" low="0" name="X_SHIFT" />
 <doc>Amount to shift x position before conversion to SPFP.</doc>
 <bitfield high="19" low="16" name="Y_SHIFT" />
-<doc>Amount to shift y position before conversion to
-SPFP.</doc></reg32>
-<reg32 access="rw" name="GB_AA_CONFIG" offset="0x4020">Specifies
-the graphics pipeline configuration for antialiasing.
+<doc>Amount to shift y position before conversion to SPFP.</doc>
+</reg32>
+<reg32 access="rw" name="GB_AA_CONFIG" offset="0x4020">
+<doc>Specifies the graphics pipeline configuration for
+antialiasing.</doc>
 <bitfield high="0" low="0" name="AA_ENABLE">
 <value name="ANTIALIASING_DISABLED" value="0">
 <doc>Antialiasing disabled(def)</doc>
@@ -2394,34 +2434,38 @@ the graphics pipeline configuration for antialiasing.
 </value>
 </bitfield>
 <doc>Specifies the number of subsamples to use while
-antialiasing.</doc></reg32>
-<reg32 access="rw" name="SC_CLIP_0_A" offset="0x43B0">OpenGL Clip
-rectangles
+antialiasing.</doc>
+</reg32>
+<reg32 access="rw" name="SC_CLIP_0_A" offset="0x43B0">
+<doc>OpenGL Clip rectangles</doc>
 <bitfield high="12" low="0" name="XS0" />
 <doc>Left hand edge of clip rectangle</doc>
 <bitfield high="25" low="13" name="YS0" />
-<doc>Upper edge of clip rectangle</doc></reg32>
-<reg32 access="rw" name="SC_CLIP_0_B" offset="0x43B4">OpenGL Clip
-rectangles
+<doc>Upper edge of clip rectangle</doc>
+</reg32>
+<reg32 access="rw" name="SC_CLIP_0_B" offset="0x43B4">
+<doc>OpenGL Clip rectangles</doc>
 <bitfield high="12" low="0" name="XS1" />
 <doc>Right hand edge of clip rectangle</doc>
 <bitfield high="25" low="13" name="YS1" />
-<doc>Lower edge of clip rectangle</doc></reg32>
+<doc>Lower edge of clip rectangle</doc>
+</reg32>
 <reg32 access="rw" name="SC_CLIP_1_A" offset="0x43B8" />
 <reg32 access="rw" name="SC_CLIP_1_B" offset="0x43BC" />
 <reg32 access="rw" name="SC_CLIP_2_A" offset="0x43C0" />
 <reg32 access="rw" name="SC_CLIP_2_B" offset="0x43C4" />
 <reg32 access="rw" name="SC_CLIP_3_A" offset="0x43C8" />
 <reg32 access="rw" name="SC_CLIP_3_B" offset="0x43CC" />
-<reg32 access="rw" name="SC_CLIP_RULE" offset="0x43D0">OpenGL Clip
-boolean function
+<reg32 access="rw" name="SC_CLIP_RULE" offset="0x43D0">
+<doc>OpenGL Clip boolean function</doc>
 <bitfield high="15" low="0" name="CLIP_RULE" />
 <doc>OpenGL Clip boolean function. The `inside` flags for each of
 the four clip rectangles form a 4-bit binary number. The
 corresponding bit in this 16-bit number specifies whether the pixel
-is visible.</doc></reg32>
-<reg32 access="rw" name="SC_HYPERZ_EN" offset="0x43A4">Hierarchical
-Z Enable
+is visible.</doc>
+</reg32>
+<reg32 access="rw" name="SC_HYPERZ_EN" offset="0x43A4">
+<doc>Hierarchical Z Enable</doc>
 <bitfield high="0" low="0" name="HZ_EN">
 <value name="DISABLES_HYPER" value="0">
 <doc>Disables Hyper-Z.</doc>
@@ -2485,27 +2529,30 @@ z value</doc>
 <doc>Vertex 0 does contain maximum z value</doc>
 </value>
 </bitfield>
-<doc>Specifies whether vertex 0 z contains maximum z
-value</doc></reg32>
-<reg32 access="rw" name="SC_SCISSOR0" offset="0x43E0">Scissor
-rectangle specification
+<doc>Specifies whether vertex 0 z contains maximum z value</doc>
+</reg32>
+<reg32 access="rw" name="SC_SCISSOR0" offset="0x43E0">
+<doc>Scissor rectangle specification</doc>
 <bitfield high="12" low="0" name="XS0" />
 <doc>Left hand edge of scissor rectangle</doc>
 <bitfield high="25" low="13" name="YS0" />
-<doc>Upper edge of scissor rectangle</doc></reg32>
-<reg32 access="rw" name="SC_SCISSOR1" offset="0x43E4">Scissor
-rectangle specification
+<doc>Upper edge of scissor rectangle</doc>
+</reg32>
+<reg32 access="rw" name="SC_SCISSOR1" offset="0x43E4">
+<doc>Scissor rectangle specification</doc>
 <bitfield high="12" low="0" name="XS1" />
 <doc>Right hand edge of scissor rectangle</doc>
 <bitfield high="25" low="13" name="YS1" />
-<doc>Lower edge of scissor rectangle</doc></reg32>
-<reg32 access="rw" name="SC_SCREENDOOR" offset="0x43E8">Screen door
-sample mask
+<doc>Lower edge of scissor rectangle</doc>
+</reg32>
+<reg32 access="rw" name="SC_SCREENDOOR" offset="0x43E8">
+<doc>Screen door sample mask</doc>
 <bitfield high="23" low="0" name="SCREENDOOR" />
 <doc>Screen door sample mask - 1 means sample may be covered, 0
-means sample is not covered</doc></reg32>
-<reg32 access="rw" name="SU_CULL_MODE" offset="0x42B8">Culling
-Enables
+means sample is not covered</doc>
+</reg32>
+<reg32 access="rw" name="SU_CULL_MODE" offset="0x42B8">
+<doc>Culling Enables</doc>
 <bitfield high="0" low="0" name="CULL_FRONT">
 <value name="DO_NOT_CULL_FRONT" value="0">
 <doc>Do not cull front-facing triangles.</doc>
@@ -2533,17 +2580,24 @@ Enables
 </value>
 </bitfield>
 <doc>X-Ored with cross product sign to determine positive
-facing</doc></reg32>
-<reg32 access="rw" name="SU_DEPTH_OFFSET" offset="0x42C4">SU Depth
-Offset value</reg32>
-<reg32 access="rw" name="SU_DEPTH_SCALE" offset="0x42C0">SU Depth
-Scale value</reg32>
+facing</doc>
+</reg32>
+<reg32 access="rw" name="SU_DEPTH_OFFSET" offset="0x42C4">
+<doc>SU Depth Offset value</doc>
+</reg32>
+<reg32 access="rw" name="SU_DEPTH_SCALE" offset="0x42C0">
+<doc>SU Depth Scale value</doc>
+</reg32>
 <reg32 access="rw" name="SU_POLY_OFFSET_BACK_OFFSET"
-offset="0x42B0">Back-Facing Polygon Offset Offset</reg32>
+offset="0x42B0">
+<doc>Back-Facing Polygon Offset Offset</doc>
+</reg32>
 <reg32 access="rw" name="SU_POLY_OFFSET_BACK_SCALE"
-offset="0x42AC">Back-Facing Polygon Offset Scale</reg32>
+offset="0x42AC">
+<doc>Back-Facing Polygon Offset Scale</doc>
+</reg32>
 <reg32 access="rw" name="SU_POLY_OFFSET_ENABLE" offset="0x42B4">
-Enables for polygon offset
+<doc>Enables for polygon offset</doc>
 <bitfield high="0" low="0" name="FRONT_ENABLE">
 <value name="DISABLE_FRONT_OFFSET" value="0">
 <doc>Disable front offset.</doc>
@@ -2572,23 +2626,33 @@ Enables for polygon offset
 </bitfield>
 <doc>Forces all parallelograms to have FRONT_FACING for poly offset
 -- Need to have FRONT_ENABLE also set to have Z offset for
-parallelograms.</doc></reg32>
+parallelograms.</doc>
+</reg32>
 <reg32 access="rw" name="SU_POLY_OFFSET_FRONT_OFFSET"
-offset="0x42A8">Front-Facing Polygon Offset Offset</reg32>
+offset="0x42A8">
+<doc>Front-Facing Polygon Offset Offset</doc>
+</reg32>
 <reg32 access="rw" name="SU_POLY_OFFSET_FRONT_SCALE"
-offset="0x42A4">Front-Facing Polygon Offset Scale</reg32>
-<reg32 access="rw" name="TX_INVALTAGS" offset="0x4100">Invalidate
-texture cache tags</reg32>
+offset="0x42A4">
+<doc>Front-Facing Polygon Offset Scale</doc>
+</reg32>
+<reg32 access="rw" name="TX_INVALTAGS" offset="0x4100">
+<doc>Invalidate texture cache tags</doc>
+</reg32>
 <reg32 access="rw" name="VAP_GB_HORZ_CLIP_ADJ" offset="0x2228">
-Horizontal Guard Band Clip Adjust Register</reg32>
+<doc>Horizontal Guard Band Clip Adjust Register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_GB_HORZ_DISC_ADJ" offset="0x222C">
-Horizontal Guard Band Discard Adjust Register</reg32>
+<doc>Horizontal Guard Band Discard Adjust Register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_GB_VERT_CLIP_ADJ" offset="0x2220">
-Vertical Guard Band Clip Adjust Register</reg32>
+<doc>Vertical Guard Band Clip Adjust Register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_GB_VERT_DISC_ADJ" offset="0x2224">
-Vertical Guard Band Discard Adjust Register</reg32>
-<reg32 access="rw" name="VAP_OUT_VTX_FMT_0" offset="0x2090">VAP
-Out/GA Vertex Format Register 0
+<doc>Vertical Guard Band Discard Adjust Register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_OUT_VTX_FMT_0" offset="0x2090">
+<doc>VAP Out/GA Vertex Format Register 0</doc>
 <bitfield high="0" low="0" name="VTX_POS_PRESENT" />
 <doc>Output the Position Vector</doc>
 <bitfield high="1" low="1" name="VTX_COLOR_0_PRESENT" />
@@ -2600,9 +2664,10 @@ Out/GA Vertex Format Register 0
 <bitfield high="4" low="4" name="VTX_COLOR_3_PRESENT" />
 <doc>Output Color 3 Vector</doc>
 <bitfield high="16" low="16" name="VTX_PT_SIZE_PRESENT" />
-<doc>Output Point Size Vector</doc></reg32>
-<reg32 access="rw" name="VAP_OUT_VTX_FMT_1" offset="0x2094">VAP
-Out/GA Vertex Format Register 1
+<doc>Output Point Size Vector</doc>
+</reg32>
+<reg32 access="rw" name="VAP_OUT_VTX_FMT_1" offset="0x2094">
+<doc>VAP Out/GA Vertex Format Register 1</doc>
 <bitfield high="2" low="0" name="TEX_0_COMP_CNT" />
 <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 =
 2 components 3 = 3 components 4 = 4 components</doc>
@@ -2626,20 +2691,24 @@ Out/GA Vertex Format Register 1
 2 components 3 = 3 components 4 = 4 components</doc>
 <bitfield high="23" low="21" name="TEX_7_COMP_CNT" />
 <doc>Number of words in texture 0 = Not Present 1 = 1 component 2 =
-2 components 3 = 3 components 4 = 4 components</doc></reg32>
-<stripe addr="0x2000" length="16" stride="0x0004">
-<reg32 access="w" name="VAP_PORT_DATA" offset="0x0">Setup Engine
-Data Port 0 through 15.</reg32>
+2 components 3 = 3 components 4 = 4 components</doc>
+</reg32>
+<stripe length="16" offset="0x2000" stride="0x0004">
+<reg32 access="w" name="VAP_PORT_DATA" offset="0x0">
+<doc>Setup Engine Data Port 0 through 15.</doc>
+</reg32>
 </stripe>
 <reg32 access="w" name="VAP_PORT_DATA_IDX_128" offset="0x20B8">
-128-bit Data Port for Indexed Primitives.</reg32>
-<stripe addr="0x2040" length="16" stride="0x0004">
-<reg32 access="w" name="VAP_PORT_IDX" offset="0x0">Setup Engine
-Index Port 0 through 15.</reg32>
+<doc>128-bit Data Port for Indexed Primitives.</doc>
+</reg32>
+<stripe length="16" offset="0x2040" stride="0x0004">
+<reg32 access="w" name="VAP_PORT_IDX" offset="0x0">
+<doc>Setup Engine Index Port 0 through 15.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x21E0" length="8" stride="0x0004">
+<stripe length="8" offset="0x21E0" stride="0x0004">
 <reg32 access="rw" name="VAP_PROG_STREAM_CNTL_EXT" offset="0x0">
-Programmable Stream Control Extension Word 0
+<doc>Programmable Stream Control Extension Word 0</doc>
 <bitfield high="2" low="0" name="SWIZZLE_SELECT_X_0" />
 <doc>X-Component Swizzle Select 0 = SELECT_X 1 = SELECT_Y 2 =
 SELECT_Z 3 = SELECT_W 4 = SELECT_FP_ZERO (Floating Point 0.0) 5 =
@@ -2662,10 +2731,11 @@ to Z Bit 3 maps to W</doc>
 <bitfield high="27" low="25" name="SWIZZLE_SELECT_W_1" />
 <doc>See SWIZZLE_SELECT_W_0</doc>
 <bitfield high="31" low="28" name="WRITE_ENA_1" />
-<doc>See WRITE_ENA_0</doc></reg32>
+<doc>See WRITE_ENA_0</doc>
+</reg32>
 </stripe>
 <reg32 access="rw" name="VAP_PSC_SGN_NORM_CNTL" offset="0x21DC">
-Programmable Stream Control Signed Normalize Control
+<doc>Programmable Stream Control Signed Normalize Control</doc>
 <bitfield high="1" low="0" name="SGN_NORM_METHOD_0">
 <value name="SGN_NORM_ZERO" value="0">
 <doc>SGN_NORM_ZERO : value / (2^(n-1)-1), so - 128/127 will be less
@@ -2712,9 +2782,10 @@ that -1.0, -127/127 will yeild -1.0, 0/127 will yield 0, and
 <bitfield high="29" low="28" name="SGN_NORM_METHOD_14" />
 <doc>See SGN_NORM_METHOD_0</doc>
 <bitfield high="31" low="30" name="SGN_NORM_METHOD_15" />
-<doc>See SGN_NORM_METHOD_0</doc></reg32>
+<doc>See SGN_NORM_METHOD_0</doc>
+</reg32>
 <reg32 access="rw" name="VAP_PVS_CODE_CNTL_0" offset="0x22D0">
-Programmable Vertex Shader Code Control Register 0
+<doc>Programmable Vertex Shader Code Control Register 0</doc>
 <bitfield high="9" low="0" name="PVS_FIRST_INST" />
 <doc>First Instruction to Execute in PVS.</doc>
 <bitfield high="19" low="10" name="PVS_XYZW_VALID_INST" />
@@ -2723,16 +2794,17 @@ for the last time. This value is used to lower the processing
 priority while trivial clip and back-face culling decisions are
 made. This field must be set to valid instruction.</doc>
 <bitfield high="29" low="20" name="PVS_LAST_INST" />
-<doc>Last Instruction (Inclusive) for the PVS to
-execute.</doc></reg32>
+<doc>Last Instruction (Inclusive) for the PVS to execute.</doc>
+</reg32>
 <reg32 access="rw" name="VAP_PVS_CODE_CNTL_1" offset="0x22D8">
-Programmable Vertex Shader Code Control Register 1
+<doc>Programmable Vertex Shader Code Control Register 1</doc>
 <bitfield high="9" low="0" name="PVS_LAST_VTX_SRC_INST" />
 <doc>The PVS Instruction which uses the Input Vertex Memory for the
 last time. This value is used to free up the Input Vertex Slots
-ASAP. This field must be set to a valid instruction.</doc></reg32>
+ASAP. This field must be set to a valid instruction.</doc>
+</reg32>
 <reg32 access="rw" name="VAP_PVS_CONST_CNTL" offset="0x22D4">
-Programmable Vertex Shader Constant Control Register
+<doc>Programmable Vertex Shader Constant Control Register</doc>
 <bitfield high="7" low="0" name="PVS_CONST_BASE_OFFSET" />
 <doc>Vector Offset into PVS constant memory to the start of the
 constants for the current shader</doc>
@@ -2741,10 +2813,12 @@ constants for the current shader</doc>
 shader (Inst Const Addr + Addr Register). If the address which is
 generated by the shader is outside the range of 0 to
 PVS_MAX_CONST_ADDR, then (0,0,0,0) is returned as the source
-operand data.</doc></reg32>
-<stripe addr="0x2230" length="16" stride="0x0004">
+operand data.</doc>
+</reg32>
+<stripe length="16" offset="0x2230" stride="0x0004">
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS" offset="0x0">
-Programmable Vertex Shader Flow Control Addresses Register 0
+<doc>Programmable Vertex Shader Flow Control Addresses Register
+0</doc>
 <bitfield high="7" low="0" name="PVS_FC_ACT_ADRS_0" />
 <doc>This field defines the last PVS instruction to execute prior
 to the control flow redirection. JUMP - The last instruction
@@ -2763,11 +2837,11 @@ instruction of the subroutine.</doc>
 <bitfield high="31" low="24" name="PVS_FC_RTN_INST_0" />
 <doc>This field has multiple definitions as follows: JUMP - Not
 Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS +
-1) JSR - First Instruction After JSR (Typically ACT_ADRS +
-1)</doc></reg32>
+1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1)</doc>
+</reg32>
 </stripe>
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_OPC" offset="0x22DC">
-Programmable Vertex Shader Flow Control Opcode Register
+<doc>Programmable Vertex Shader Flow Control Opcode Register</doc>
 <bitfield high="1" low="0" name="PVS_FC_OPC_0" />
 <doc>This opcode field determines what type of control flow
 instruction to execute. 0 = NO_OP 1 = JUMP 2 = LOOP 3 = JSR (Jump
@@ -2801,7 +2875,8 @@ to Subroutine)</doc>
 <bitfield high="29" low="28" name="PVS_FC_OPC_14" />
 <doc>See PVS_FC_OPC_0.</doc>
 <bitfield high="31" low="30" name="PVS_FC_OPC_15" />
-<doc>See PVS_FC_OPC_0.</doc></reg32>
+<doc>See PVS_FC_OPC_0.</doc>
+</reg32>
 <reg32 access="rw" name="VAP_PVS_STATE_FLUSH_REG"
 offset="0x2284" />
 <reg32 access="rw" name="VAP_PVS_VECTOR_DATA_REG"
@@ -2815,29 +2890,37 @@ offset="0x2208" />
 <reg32 access="rw" name="VAP_PVS_VTX_TIMEOUT_REG"
 offset="0x2288" />
 <reg32 access="rw" name="VAP_VF_MAX_VTX_INDX" offset="0x2134">
-Maximum Vertex Indx Clamp
+<doc>Maximum Vertex Indx Clamp</doc>
 <bitfield high="23" low="0" name="MAX_INDX" />
 <doc>If index to be fetched is larger than this value, the fetch
-indx is set to MAX_INDX</doc></reg32>
+indx is set to MAX_INDX</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VF_MIN_VTX_INDX" offset="0x2138">
-Minimum Vertex Indx Clamp
+<doc>Minimum Vertex Indx Clamp</doc>
 <bitfield high="23" low="0" name="MIN_INDX" />
 <doc>If index to be fetched is smaller than this value, the fetch
-indx is set to MIN_INDX</doc></reg32>
+indx is set to MIN_INDX</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VPORT_XOFFSET" offset="0x209C">
-Viewport Transform X Offset</reg32>
-<reg32 access="rw" name="VAP_VPORT_XSCALE" offset="0x2098">Viewport
-Transform X Scale Factor</reg32>
+<doc>Viewport Transform X Offset</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VPORT_XSCALE" offset="0x2098">
+<doc>Viewport Transform X Scale Factor</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VPORT_YOFFSET" offset="0x20A4">
-Viewport Transform Y Offset</reg32>
-<reg32 access="rw" name="VAP_VPORT_YSCALE" offset="0x20A0">Viewport
-Transform Y Scale Factor</reg32>
+<doc>Viewport Transform Y Offset</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VPORT_YSCALE" offset="0x20A0">
+<doc>Viewport Transform Y Scale Factor</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VPORT_ZOFFSET" offset="0x20AC">
-Viewport Transform Z Offset</reg32>
-<reg32 access="rw" name="VAP_VPORT_ZSCALE" offset="0x20A8">Viewport
-Transform Z Scale Factor</reg32>
-<reg32 access="rw" name="VAP_VTE_CNTL" offset="0x20B0">Viewport
-Transform Engine Control
+<doc>Viewport Transform Z Offset</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VPORT_ZSCALE" offset="0x20A8">
+<doc>Viewport Transform Z Scale Factor</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTE_CNTL" offset="0x20B0">
+<doc>Viewport Transform Engine Control</doc>
 <bitfield high="0" low="0" name="VPORT_X_SCALE_ENA" />
 <doc>Viewport Transform Scale Enable for X component</doc>
 <bitfield high="1" low="1" name="VPORT_X_OFFSET_ENA" />
@@ -2864,16 +2947,18 @@ Engine will perform the reciprocal to get 1/W0.</doc>
 <bitfield high="11" low="11" name="SERIAL_PROC_ENA" />
 <doc>If set, x,y,z viewport transform are performed serially
 through a single pipeline instead of in parallel. Used to mimic
-RL300 design.</doc></reg32>
-<stripe addr="0x20C8" length="16" stride="0x0005">
+RL300 design.</doc>
+</reg32>
+<stripe length="16" offset="0x20C8" stride="0x0005">
 <reg32 access="rw" name="VAP_VTX_AOS_ADDR" offset="0x0">
-Array-of-Structures Address 0
+<doc>Array-of-Structures Address 0</doc>
 <bitfield high="31" low="2" name="VTX_AOS_ADDR0" />
-<doc>Base Address of the Array of Structures.</doc></reg32>
+<doc>Base Address of the Array of Structures.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x20C4" length="1415" stride="0x0000">
+<stripe length="1415" offset="0x20C4" stride="0x0000">
 <reg32 access="rw" name="VAP_VTX_AOS_ATTR" offset="0x0">
-Array-of-Structures Attributes 0 &amp; 1
+<doc>Array-of-Structures Attributes 0 &amp; 1</doc>
 <bitfield high="6" low="0" name="VTX_AOS_COUNT0" />
 <doc>Number of dwords in this structure.</doc>
 <bitfield high="14" low="8" name="VTX_AOS_STRIDE0" />
@@ -2881,27 +2966,28 @@ Array-of-Structures Attributes 0 &amp; 1
 <bitfield high="22" low="16" name="VTX_AOS_COUNT1" />
 <doc>Number of dwords in this structure.</doc>
 <bitfield high="30" low="24" name="VTX_AOS_STRIDE1" />
-<doc>Number of dwords from one array element to the
-next.</doc></reg32>
+<doc>Number of dwords from one array element to the next.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_VTX_SIZE" offset="0x20B4">Vertex Size
-Specification Register
+<reg32 access="rw" name="VAP_VTX_SIZE" offset="0x20B4">
+<doc>Vertex Size Specification Register</doc>
 <bitfield high="6" low="0" name="DWORDS_PER_VTX" />
 <doc>This field specifies the number of DWORDS per vertex to expect
 when VAP_VF_CNTL.PRIM_WALK is set to Vertex Data (vertex data
 embedded in command stream). This field is not used for any other
 PRIM_WALK settings. This field replaces the usage of the
-VAP_VTX_FMT_0/1 for this purpose in prior
-implementations.</doc></reg32>
-<reg32 access="rw" name="ZB_DEPTHCLEARVALUE" offset="0x4F28">Z
-Buffer Clear Value</reg32>
-<reg32 access="rw" name="ZB_DEPTHOFFSET" offset="0x4F20">Z Buffer
-Address Offset
+VAP_VTX_FMT_0/1 for this purpose in prior implementations.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_DEPTHCLEARVALUE" offset="0x4F28">
+<doc>Z Buffer Clear Value</doc>
+</reg32>
+<reg32 access="rw" name="ZB_DEPTHOFFSET" offset="0x4F20">
+<doc>Z Buffer Address Offset</doc>
 <bitfield high="31" low="5" name="DEPTHOFFSET" />
-<doc>2K aligned Z buffer address offset for macro
-tiles.</doc></reg32>
-<reg32 access="rw" name="ZB_DEPTHPITCH" offset="0x4F24">Z Buffer
-Pitch and Endian Control
+<doc>2K aligned Z buffer address offset for macro tiles.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_DEPTHPITCH" offset="0x4F24">
+<doc>Z Buffer Pitch and Endian Control</doc>
 <bitfield high="13" low="2" name="DEPTHPITCH" />
 <doc>Z buffer pitch in multiples of 4 pixels.</doc>
 <bitfield high="16" low="16" name="DEPTHMACROTILE">
@@ -2942,32 +3028,37 @@ bytes</doc>
 <doc>Half Dword swap</doc>
 </value>
 </bitfield>
-<doc>Specifies endian control for the Z buffer.</doc></reg32>
-<reg32 access="rw" name="ZB_DEPTHXY_OFFSET" offset="0x4F60">Depth
-buffer X and Y coordinate offset
+<doc>Specifies endian control for the Z buffer.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_DEPTHXY_OFFSET" offset="0x4F60">
+<doc>Depth buffer X and Y coordinate offset</doc>
 <bitfield high="11" low="1" name="DEPTHX_OFFSET" />
 <doc>X coordinate offset. multiple of 32 . Bits 4:0 have to be
 zero</doc>
 <bitfield high="27" low="17" name="DEPTHY_OFFSET" />
 <doc>Y coordinate offset. multiple of 32 . Bits 4:0 have to be
-zero</doc></reg32>
-<reg32 access="rw" name="ZB_HIZ_DWORD" offset="0x4F4C">Hierarchical
-Z Data</reg32>
-<reg32 access="rw" name="ZB_HIZ_PITCH" offset="0x4F54">Hierarchical
-Z Pitch
+zero</doc>
+</reg32>
+<reg32 access="rw" name="ZB_HIZ_DWORD" offset="0x4F4C">
+<doc>Hierarchical Z Data</doc>
+</reg32>
+<reg32 access="rw" name="ZB_HIZ_PITCH" offset="0x4F54">
+<doc>Hierarchical Z Pitch</doc>
 <bitfield high="13" low="4" name="HIZ_PITCH" />
-<doc>Pitch used in HiZ address computation.</doc></reg32>
-<reg32 access="rw" name="ZB_STENCILREFMASK" offset="0x4F08">Stencil
-Reference Value and Mask
+<doc>Pitch used in HiZ address computation.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_STENCILREFMASK" offset="0x4F08">
+<doc>Stencil Reference Value and Mask</doc>
 <bitfield high="7" low="0" name="STENCILREF" />
 <doc>Specifies the reference stencil value.</doc>
 <bitfield high="15" low="8" name="STENCILMASK" />
 <doc>This value is ANDed with both the reference and the current
 stencil value prior to the stencil test.</doc>
 <bitfield high="23" low="16" name="STENCILWRITEMASK" />
-<doc>Specifies the write mask for the stencil planes.</doc></reg32>
-<reg32 access="rw" name="ZB_ZCACHE_CTLSTAT" offset="0x4F18">Z
-Buffer Cache Control/Status
+<doc>Specifies the write mask for the stencil planes.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_ZCACHE_CTLSTAT" offset="0x4F18">
+<doc>Z Buffer Cache Control/Status</doc>
 <bitfield high="0" low="0" name="ZC_FLUSH">
 <value name="NO_EFFECT" value="0">
 <doc>No effect</doc>
@@ -3000,9 +3091,10 @@ bit that clears itself at the end of the operation.</doc>
 <doc>Busy</doc>
 </value>
 </bitfield>
-<doc>This bit is unused ...</doc></reg32>
-<reg32 access="rw" name="ZB_ZPASS_ADDR" offset="0x4F5C">Z Buffer Z
-Pass Counter Address
+<doc>This bit is unused ...</doc>
+</reg32>
+<reg32 access="rw" name="ZB_ZPASS_ADDR" offset="0x4F5C">
+<doc>Z Buffer Z Pass Counter Address</doc>
 <bitfield high="31" low="2" name="ZPASS_ADDR" />
 <doc>Writing this location with a DWORD address causes the value in
 ZB_ZPASS_DATA to be written to main memory at the location pointed
@@ -3012,9 +3104,11 @@ address. There is no guarantee which pipe will write last. So when
 writing to this register, the GA needs to be programmed to send the
 write command to pipe 0. Then a different address needs to be
 written to pipe 1. Then both pipes should be enabled for further
-register writes.</doc></reg32>
-<reg32 access="rw" name="ZB_ZPASS_DATA" offset="0x4F58">Z Buffer Z
-Pass Counter Data</reg32>
+register writes.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_ZPASS_DATA" offset="0x4F58">
+<doc>Z Buffer Z Pass Counter Data</doc>
+</reg32>
 <reg32 access="rw" name="ZB_ZTOP" offset="0x4F14">
 <bitfield high="0" low="0" name="ZTOP">
 <value name="Z_IS_AT_THE_BOTTOM_OF_THE_PIPE" value="0">
@@ -3029,7 +3123,7 @@ Pass Counter Data</reg32>
 </group>
 <group name="r300_regs" prepend="R300_">
 <reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88">
-Resolve Buffer Control. Unpipelined
+<doc>Resolve Buffer Control. Unpipelined</doc>
 <bitfield high="0" low="0" name="AARESOLVE_MODE" />
 <doc>Specifies if the color buffer is in resolve mode. The cache
 must be empty before changing this register.</doc>
@@ -3037,9 +3131,11 @@ must be empty before changing this register.</doc>
 <use-enum ref="ENUM1" />
 </bitfield>
 <doc>Specifies the gamma and degamma to be applied to the samples
-before and after filtering, respectively.</doc></reg32>
-<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04">Alpha
-Blend Control for Color Channels. Pipelined through the blender.
+before and after filtering, respectively.</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04">
+<doc>Alpha Blend Control for Color Channels. Pipelined through the
+blender.</doc>
 <bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE">
 <use-enum ref="ENUM5" />
 </bitfield>
@@ -3094,8 +3190,10 @@ DESTBLEND are combined.</doc>
 <use-enum ref="ENUM4" />
 </bitfield>
 <doc>Destination Blend Function , Alpha blending function
-(DST).</doc></reg32>
-<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00">Unpipelined.
+(DST).</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00">
+<doc>Unpipelined.</doc>
 <bitfield high="6" low="5" name="NUM_MULTIWRITES">
 <use-enum ref="ENUM9" />
 </bitfield>
@@ -3112,12 +3210,13 @@ logic in the backend.</doc>
 <doc>Enables AA color compression. The cache must be empty before
 this is changed.</doc>
 <bitfield high="10" low="10" name="Reserved" />
-<doc>Set to 0</doc></reg32>
-<stripe addr="0x4E38" length="4" stride="0x0004">
-<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0">Color buffer
-format and tiling control for all the multibuffers and the pitch of
-multibuffer 0. Unpipelined. The cache must be empty before any of
-the registers are changed.
+<doc>Set to 0</doc>
+</reg32>
+<stripe length="4" offset="0x4E38" stride="0x0004">
+<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0">
+<doc>Color buffer format and tiling control for all the
+multibuffers and the pitch of multibuffer 0. Unpipelined. The cache
+must be empty before any of the registers are changed.</doc>
 <bitfield high="13" low="1" name="COLORPITCH" />
 <doc>3D destination pitch in multiples of 2-pixels.</doc>
 <bitfield high="16" low="16" name="COLORTILE">
@@ -3166,12 +3265,13 @@ format.</doc>
 <doc>ARGB4444</doc>
 </value>
 </bitfield>
-<doc>3D destination color format.</doc></reg32>
+<doc>3D destination color format.</doc>
+</reg32>
 </stripe>
 <reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" offset="0x4E0C">
-3D Color Channel Mask. If all the channels used in the current
+<doc>3D Color Channel Mask. If all the channels used in the current
 color format are disabled, then the cb will discard all the
-incoming quads. Pipelined through the blender.
+incoming quads. Pipelined through the blender.</doc>
 <bitfield high="0" low="0" name="BLUE_MASK">
 <use-enum ref="ENUM16" />
 </bitfield>
@@ -3187,12 +3287,15 @@ incoming quads. Pipelined through the blender.
 <bitfield high="3" low="3" name="ALPHA_MASK">
 <use-enum ref="ENUM16" />
 </bitfield>
-<doc>mask bit for alpha channel</doc></reg32>
+<doc>mask bit for alpha channel</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" offset="0x4E14">
-Clear color that is used when the color mask is set to 00.
-Unpipelined.</reg32>
+<doc>Clear color that is used when the color mask is set to 00.
+Unpipelined.</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10">
-Constant color used by the blender. Pipelined through the blender.
+<doc>Constant color used by the blender. Pipelined through the
+blender.</doc>
 <bitfield high="7" low="0" name="BLUE" />
 <doc>blue constant color</doc>
 <bitfield high="15" low="8" name="GREEN" />
@@ -3200,9 +3303,10 @@ Constant color used by the blender. Pipelined through the blender.
 <bitfield high="23" low="16" name="RED" />
 <doc>red constant color</doc>
 <bitfield high="31" low="24" name="ALPHA" />
-<doc>alpha constant color</doc></reg32>
-<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4">Alpha
-Function
+<doc>alpha constant color</doc>
+</reg32>
+<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4">
+<doc>Alpha Function</doc>
 <bitfield high="7" low="0" name="AF_VAL" />
 <doc>Specifies the alpha compare value.</doc>
 <bitfield high="10" low="8" name="AF_FUNC">
@@ -3225,26 +3329,30 @@ function.</doc>
 <bitfield high="20" low="20" name="DITH_EN">
 <use-enum ref="ENUM26" />
 </bitfield>
-<doc>Enables/Disables RGB Dithering.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0">Blue
-Component of Fog Color
+<doc>Enables/Disables RGB Dithering.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0">
+<doc>Blue Component of Fog Color</doc>
 <bitfield high="9" low="0" name="BLUE" />
-<doc>Blue component of fog color; (0.9) fixed format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC">Green
-Component of Fog Color
+<doc>Blue component of fog color; (0.9) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC">
+<doc>Green Component of Fog Color</doc>
 <bitfield high="9" low="0" name="GREEN" />
-<doc>Green component of fog color; (0.9) fixed
-format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8">Red
-Component of Fog Color
+<doc>Green component of fog color; (0.9) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8">
+<doc>Red Component of Fog Color</doc>
 <bitfield high="9" low="0" name="RED" />
-<doc>Red component of fog color; (0.9) fixed format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4">Constant
-Factor for Fog Blending
+<doc>Red component of fog color; (0.9) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4">
+<doc>Constant Factor for Fog Blending</doc>
 <bitfield high="9" low="0" name="FACTOR" />
-<doc>Constant fog factor; fixed (0.9) format.</doc></reg32>
-<reg32 access="rw" name="GA_ENHANCE" offset="0x4274">GA Enhancement
-Register
+<doc>Constant fog factor; fixed (0.9) format.</doc>
+</reg32>
+<reg32 access="rw" name="GA_ENHANCE" offset="0x4274">
+<doc>GA Enhancement Register</doc>
 <bitfield high="0" low="0" name="DEADLOCK_CNTL">
 <use-enum ref="ENUM32" />
 </bitfield>
@@ -3252,29 +3360,35 @@ Register
 <bitfield high="1" low="1" name="FASTSYNC_CNTL">
 <use-enum ref="ENUM33" />
 </bitfield>
-<doc>Enables Fast register/primitive switching</doc></reg32>
-<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234">Line control
+<doc>Enables Fast register/primitive switching</doc>
+</reg32>
+<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234">
+<doc>Line control</doc>
 <bitfield high="15" low="0" name="WIDTH" />
 <doc>1/2 width of line, in subpixels; (16.0) fixed format.</doc>
 <bitfield high="17" low="16" name="END_TYPE">
 <use-enum ref="ENUM34" />
 </bitfield>
-<doc>Specifies how ends of lines should be drawn.</doc></reg32>
-<reg32 access="rw" name="GA_OFFSET" offset="0x4290">Specifies x
-&amp; y offsets for vertex data after conversion to FP.
+<doc>Specifies how ends of lines should be drawn.</doc>
+</reg32>
+<reg32 access="rw" name="GA_OFFSET" offset="0x4290">
+<doc>Specifies x &amp; y offsets for vertex data after conversion
+to FP.</doc>
 <bitfield high="15" low="0" name="X_OFFSET" />
 <doc>Specifies X offset in S15 format (subpixels).</doc>
 <bitfield high="31" low="16" name="Y_OFFSET" />
-<doc>Specifies Y offset in S15 format (subpixels).</doc></reg32>
-<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C">Dimensions
-for Points
+<doc>Specifies Y offset in S15 format (subpixels).</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C">
+<doc>Dimensions for Points</doc>
 <bitfield high="15" low="0" name="HEIGHT" />
 <doc>1/2 Height of point; fixed (16.0), subpixel format.</doc>
 <bitfield high="31" low="16" name="WIDTH" />
-<doc>1/2 Width of point; fixed (16.0), subpixel
-format.</doc></reg32>
-<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C">Specifies
-the rouding mode for geometry &amp; color SPFP to FP conversions.
+<doc>1/2 Width of point; fixed (16.0), subpixel format.</doc>
+</reg32>
+<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C">
+<doc>Specifies the rouding mode for geometry &amp; color SPFP to FP
+conversions.</doc>
 <bitfield high="1" low="0" name="GEOMETRY_ROUND">
 <use-enum ref="ENUM38" />
 </bitfield>
@@ -3301,27 +3415,30 @@ RGB.</doc>
 <doc>Clamp to [-7.9999, 7.9999] for Alpha</doc>
 </value>
 </bitfield>
-<doc>Specifies SPFP alpha clamp range of [0,1] or
-[-8,8].</doc></reg32>
-<reg32 access="rw" name="GA_SOFT_RESET" offset="0x429C">Specifies
-number of cycles to assert reset, and also causes RB3D soft reset
-to assert.
+<doc>Specifies SPFP alpha clamp range of [0,1] or [-8,8].</doc>
+</reg32>
+<reg32 access="rw" name="GA_SOFT_RESET" offset="0x429C">
+<doc>Specifies number of cycles to assert reset, and also causes
+RB3D soft reset to assert.</doc>
 <bitfield high="15" low="0" name="SOFT_RESET_COUNT" />
-<doc>Count in cycles (def 256).</doc></reg32>
-<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280">Specifies
-blue &amp; alpha components of fill color.
+<doc>Count in cycles (def 256).</doc>
+</reg32>
+<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280">
+<doc>Specifies blue &amp; alpha components of fill color.</doc>
 <bitfield high="15" low="0" name="COLOR_ALPHA" />
 <doc>Component alpha value. (S3.12)</doc>
 <bitfield high="31" low="16" name="COLOR_BLUE" />
-<doc>Component blue value. (S3.12)</doc></reg32>
-<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C">Specifies red
-&amp; green components of fill color.
+<doc>Component blue value. (S3.12)</doc>
+</reg32>
+<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C">
+<doc>Specifies red &amp; green components of fill color.</doc>
 <bitfield high="15" low="0" name="COLOR_GREEN" />
 <doc>Component green value (S3.12).</doc>
 <bitfield high="31" low="16" name="COLOR_RED" />
-<doc>Component red value (S3.12).</doc></reg32>
-<reg32 access="rw" name="GB_ENABLE" offset="0x4008">Specifies top
-of Raster pipe specific enable controls.
+<doc>Component red value (S3.12).</doc>
+</reg32>
+<reg32 access="rw" name="GB_ENABLE" offset="0x4008">
+<doc>Specifies top of Raster pipe specific enable controls.</doc>
 <bitfield high="0" low="0" name="POINT_STUFF_ENABLE">
 <use-enum ref="ENUM43" />
 </bitfield>
@@ -3445,10 +3562,11 @@ texture.</doc>
 </value>
 </bitfield>
 <doc>Specifies the source of the texture coordinates for this
-texture.</doc></reg32>
-<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024">Specifies
-the sizes of the various FIFO`s in the sc/rs/us. This register must
-be the first one written
+texture.</doc>
+</reg32>
+<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024">
+<doc>Specifies the sizes of the various FIFO`s in the sc/rs/us.
+This register must be the first one written</doc>
 <bitfield high="1" low="0" name="SC_IFIFO_SIZE">
 <use-enum ref="ENUM55" />
 </bitfield>
@@ -3491,9 +3609,10 @@ be the first one written
 <doc>High water mark for US output FIFO (0-12, default 4)</doc>
 <bitfield high="27" low="24" name="US_CUBE_FIFO_HIGHWATER" />
 <doc>High water mark for US texture output FIFO (0-15, default
-11)</doc></reg32>
-<reg32 access="rw" name="GB_MSPOS0" offset="0x4010">Specifies the
-position of multisamples 0 through 2
+11)</doc>
+</reg32>
+<reg32 access="rw" name="GB_MSPOS0" offset="0x4010">
+<doc>Specifies the position of multisamples 0 through 2</doc>
 <bitfield high="3" low="0" name="MS_X0" />
 <doc>Specifies the x and y position (in subpixels) of multisample
 0</doc>
@@ -3522,9 +3641,10 @@ between the pixel edge and the multisample bounding box. This value
 is used in the tile scan converter. The special case value of 8 is
 represented by msbd0_x[2:0]=7. msbd0_x[3] is used to force a
 bounding box based tile scan conversion instead of an intercept
-based one. This value should always be set to 0.</doc></reg32>
-<reg32 access="rw" name="GB_MSPOS1" offset="0x4014">Specifies the
-position of multisamples 3 through 5
+based one. This value should always be set to 0.</doc>
+</reg32>
+<reg32 access="rw" name="GB_MSPOS1" offset="0x4014">
+<doc>Specifies the position of multisamples 3 through 5</doc>
 <bitfield high="3" low="0" name="MS_X3" />
 <doc>Specifies the x and y position (in subpixels) of multisample
 3</doc>
@@ -3546,9 +3666,11 @@ position of multisamples 3 through 5
 <bitfield high="27" low="24" name="MSBD1" />
 <doc>Specifies the minimum distance (in subpixels) between the
 pixel edge and the multisample bounding box. This value is used in
-the quad scan converter</doc></reg32>
-<reg32 access="rw" name="GB_SELECT" offset="0x401C">Specifies
-various polygon specific selects (fog, depth, perspective).
+the quad scan converter</doc>
+</reg32>
+<reg32 access="rw" name="GB_SELECT" offset="0x401C">
+<doc>Specifies various polygon specific selects (fog, depth,
+perspective).</doc>
 <bitfield high="2" low="0" name="FOG_SELECT">
 <use-enum ref="ENUM59" />
 </bitfield>
@@ -3562,9 +3684,11 @@ value.</doc>
 <use-enum ref="ENUM61" />
 </bitfield>
 <doc>Specifies source for outgoing (1/W) value, used to disable
-perspective correct colors/textures.</doc></reg32>
-<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018">Specifies
-the graphics pipeline configuration for rasterization
+perspective correct colors/textures.</doc>
+</reg32>
+<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018">
+<doc>Specifies the graphics pipeline configuration for
+rasterization</doc>
 <bitfield high="0" low="0" name="ENABLE">
 <use-enum ref="ENUM62" />
 </bitfield>
@@ -3612,9 +3736,11 @@ of 2,8,32 or 128).</doc>
 <bitfield high="18" low="17" name="QUADS_PER_RAS" />
 <doc>unused</doc>
 <bitfield high="19" low="19" name="BB_SCAN" />
-<doc>unused</doc></reg32>
-<reg32 access="rw" name="RS_COUNT" offset="0x4300">This register
-specifies the rasterizer input packet configuration
+<doc>unused</doc>
+</reg32>
+<reg32 access="rw" name="RS_COUNT" offset="0x4300">
+<doc>This register specifies the rasterizer input packet
+configuration</doc>
 <bitfield high="6" low="0" name="IT_COUNT" />
 <doc>Specifies the total number of texture address components
 contained in the rasterizer input packet (0:32).</doc>
@@ -3629,10 +3755,12 @@ rasterizer input packet (0 or 1).</doc>
 (if w_count==1)</doc>
 <bitfield high="18" low="18" name="HIRES_EN" />
 <doc>Enable high resolution texture coordinate output when q is
-equal to 1</doc></reg32>
-<stripe addr="0x4330" length="16" stride="0x0004">
-<reg32 access="rw" name="RS_INST" offset="0x0">This table specifies
-what happens during each rasterizer instruction
+equal to 1</doc>
+</reg32>
+<stripe length="16" offset="0x4330" stride="0x0004">
+<reg32 access="rw" name="RS_INST" offset="0x0">
+<doc>This table specifies what happens during each rasterizer
+instruction</doc>
 <bitfield high="2" low="0" name="TEX_ID" />
 <doc>Specifies the index (into the RS_IP table) of the texture
 address output during this rasterizer instruction</doc>
@@ -3666,10 +3794,12 @@ instruction</doc>
 <doc>Specifies whether to sample texture coordinates at the real or
 adjusted pixel centers</doc>
 <bitfield high="24" low="23" name="COL_BIAS" />
-<doc>unused</doc></reg32>
+<doc>unused</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304">This
-register specifies the number of rasterizer instructions
+<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304">
+<doc>This register specifies the number of rasterizer
+instructions</doc>
 <bitfield high="3" low="0" name="INST_COUNT" />
 <doc>Number of rasterizer instructions (1:16)</doc>
 <bitfield high="4" low="4" name="W_EN" />
@@ -3702,11 +3832,12 @@ register specifies the number of rasterizer instructions
 </bitfield>
 <doc>Defines texture coordinate offset (based on min/max coordinate
 range of triangle) used to minimize or eliminate peroidic errors on
-texels sampled right on their edges</doc></reg32>
-<stripe addr="0x4310" length="8" stride="0x0000">
-<reg32 access="rw" name="RS_IP" offset="0x0">This table specifies
-the source location and format for up to 8 texture addresses
-(i[0]:i[7]) and four colors (c[0]:c[3])
+texels sampled right on their edges</doc>
+</reg32>
+<stripe length="8" offset="0x4310" stride="0x0000">
+<reg32 access="rw" name="RS_IP" offset="0x0">
+<doc>This table specifies the source location and format for up to
+8 texture addresses (i[0]:i[7]) and four colors (c[0]:c[3])</doc>
 <bitfield high="5" low="0" name="TEX_PTR" />
 <doc>Specifies the relative rasterizer input packet location of
 texture address (i[i]).</doc>
@@ -3732,10 +3863,12 @@ color (c[i]).</doc>
 <bitfield high="24" low="22" name="SEL_Q">
 <use-enum ref="ENUM73" />
 </bitfield>
-<doc>Source select for S, T, R, and Q</doc></reg32>
+<doc>Source select for S, T, R, and Q</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8">Edge rules -
-what happens when an edge falls exactly on a sample point
+<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8">
+<doc>Edge rules - what happens when an edge falls exactly on a
+sample point</doc>
 <bitfield high="4" low="0" name="ER_TRI">
 <use-enum ref="ENUM74" />
 </bitfield>
@@ -3813,9 +3946,10 @@ specifies whether a sample on a left edge is in. For values 16 to
 31, bit 0 specifies whether a sample on a vertical-right edge is
 in, bit 1 specifies whether a sample on a vertical-left edge is in,
 bit 2 species whether a sample on a bottom edge is in, bit 3
-specifies whether a sample on a top edge is in</doc></reg32>
-<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8">SU Raster
-pipe destination select for registers
+specifies whether a sample on a top edge is in</doc>
+</reg32>
+<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8">
+<doc>SU Raster pipe destination select for registers</doc>
 <bitfield high="3" low="0" name="SELECT">
 <value name="P0_ENABLE" value="0">
 <doc>P0 enable, b</doc>
@@ -3825,9 +3959,10 @@ pipe destination select for registers
 </value>
 </bitfield>
 <doc>Select which of the 2 pipes (enable per pipe) to send register
-read/write to. b0: P0 enable, b3: P1 enable</doc></reg32>
-<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0">Enables for
-Cylindrical Wrapping
+read/write to. b0: P0 enable, b3: P1 enable</doc>
+</reg32>
+<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0">
+<doc>Enables for Cylindrical Wrapping</doc>
 <bitfield high="0" low="0" name="T0C0">
 <value name="DISABLE_CYLINDRICAL_WRAPPING_FOR_TEX_0_COMP_0"
 value="0">
@@ -4179,17 +4314,20 @@ value="1">
 <doc>Enable cylindrical wrapping for tex 7 comp 3.</doc>
 </value>
 </bitfield>
-<doc /></reg32>
-<stripe addr="0x45C0" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0">Border Color
-for Map 0</reg32>
+<doc />
+</reg32>
+<stripe length="16" offset="0x45C0" stride="0x0004">
+<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0">
+<doc>Border Color for Map 0</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4580" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0">Texture Chroma
-Key for Map 0</reg32>
+<stripe length="16" offset="0x4580" stride="0x0004">
+<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0">
+<doc>Texture Chroma Key for Map 0</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="TX_ENABLE" offset="0x4104">Texture Enables
-for Maps 0 to 15
+<reg32 access="rw" name="TX_ENABLE" offset="0x4104">
+<doc>Texture Enables for Maps 0 to 15</doc>
 <bitfield high="0" low="0" name="TEX_0_ENABLE">
 <value name="DISABLE" value="0">
 <doc>Disable, T0(ARGB) = 1,0,0,0</doc>
@@ -4333,10 +4471,11 @@ for Maps 0 to 15
 <doc>Enable</doc>
 </value>
 </bitfield>
-<doc>Texture Map 15 Enable.</doc></reg32>
-<stripe addr="0x4400" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FILTER0" offset="0x0">Texture Filter
-State for Map 0
+<doc>Texture Map 15 Enable.</doc>
+</reg32>
+<stripe length="16" offset="0x4400" stride="0x0004">
+<reg32 access="rw" name="TX_FILTER0" offset="0x0">
+<doc>Texture Filter State for Map 0</doc>
 <bitfield high="2" low="0" name="CLAMP_S">
 <use-enum ref="ENUM136" />
 </bitfield>
@@ -4369,11 +4508,12 @@ State for Map 0
 <doc>LOD index of largest (finest) mipmap to use (0 is largest).
 Ranges from 0 to NUM_LEVELS.</doc>
 <bitfield high="31" low="28" name="ID" />
-<doc>Logical id for this physical texture</doc></reg32>
+<doc>Logical id for this physical texture</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4440" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FILTER1" offset="0x0">Texture Filter
-State for Map 0
+<stripe length="16" offset="0x4440" stride="0x0004">
+<reg32 access="rw" name="TX_FILTER1" offset="0x0">
+<doc>Texture Filter State for Map 0</doc>
 <bitfield high="1" low="0" name="CHROMA_KEY_MODE">
 <use-enum ref="ENUM140" />
 </bitfield>
@@ -4389,11 +4529,12 @@ is clamped.</doc>
 <bitfield high="14" low="14" name="MC_COORD_TRUNCATE">
 <use-enum ref="ENUM142" />
 </bitfield>
-<doc>MPEG coordinate truncation mode</doc></reg32>
+<doc>MPEG coordinate truncation mode</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4480" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT0" offset="0x0">Texture Format
-State for Map 0
+<stripe length="16" offset="0x4480" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT0" offset="0x0">
+<doc>Texture Format State for Map 0</doc>
 <bitfield high="10" low="0" name="TXWIDTH" />
 <doc>Image width - 1. The largest image is 2048 texels. When
 wrapping or mirroring, must be a power of 2. When mipmapping, must
@@ -4417,11 +4558,12 @@ Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc>
 <use-enum ref="ENUM144" />
 </bitfield>
 <doc>Indicates when TXPITCH should be used instead of TXWIDTH for
-image addressing</doc></reg32>
+image addressing</doc>
+</reg32>
 </stripe>
-<stripe addr="0x44C0" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT1" offset="0x0">Texture Format
-State for Map 0
+<stripe length="16" offset="0x44C0" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT1" offset="0x0">
+<doc>Texture Format State for Map 0</doc>
 <bitfield high="4" low="0" name="TXFORMAT">
 <value name="TX_FMT_8" value="0">
 <doc>TX_FMT_8</doc>
@@ -4688,19 +4830,21 @@ Only apply to 8bit or less components.</doc>
 </bitfield>
 <doc>Multi-texture performance can be optimized and made
 deterministic by assigning textures to separate regions under sw
-control.</doc></reg32>
+control.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4500" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT2" offset="0x0">Texture Format
-State for Map 0
+<stripe length="16" offset="0x4500" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT2" offset="0x0">
+<doc>Texture Format State for Map 0</doc>
 <bitfield high="13" low="0" name="TXPITCH" />
 <doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN
 is asserted. Pitch is given as number of texels minus one. Maximum
-pitch is 16K texels.</doc></reg32>
+pitch is 16K texels.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4540" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_OFFSET" offset="0x0">Texture Offset
-State for Map 0
+<stripe length="16" offset="0x4540" stride="0x0004">
+<reg32 access="rw" name="TX_OFFSET" offset="0x0">
+<doc>Texture Offset State for Map 0</doc>
 <bitfield high="1" low="0" name="ENDIAN_SWAP">
 <use-enum ref="ENUM159" />
 </bitfield>
@@ -4714,13 +4858,14 @@ State for Map 0
 </bitfield>
 <doc>Micro Tile Control</doc>
 <bitfield high="31" low="5" name="TXOFFSET" />
-<doc>32-byte aligned pointer to base map</doc></reg32>
+<doc>32-byte aligned pointer to base map</doc>
+</reg32>
 </stripe>
-<stripe addr="0x47C0" length="64" stride="0x0004">
-<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0">This table
-specifies the Alpha source addresses for up to 64 ALU instruction.
-The ALU expects 6 source operands - three for color (rgb0, rgb1,
-rgb2) and three for alpha (a0, a1, a2).
+<stripe length="64" offset="0x47C0" stride="0x0004">
+<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0">
+<doc>This table specifies the Alpha source addresses for up to 64
+ALU instruction. The ALU expects 6 source operands - three for
+color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc>
 <bitfield high="5" low="0" name="ADDR0" />
 <doc>Specifies the identity of source operands a0, a1, and a2.
 Values 0 through 31 specify a location within the current pixel
@@ -4772,11 +4917,12 @@ result of this instruction to the output fifo.</doc>
 result of this instuction to the depth output fifo.</doc>
 <bitfield high="31" low="28" name="STAT_WE" />
 <doc>Specifies which components (R,G,B,A) contribute to the stat
-count (see performance counter field in US_CONFIG).</doc></reg32>
+count (see performance counter field in US_CONFIG).</doc>
+</reg32>
 </stripe>
-<stripe addr="0x49C0" length="64" stride="0x0004">
-<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0">ALU Alpha
-Instruction
+<stripe length="64" offset="0x49C0" stride="0x0004">
+<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0">
+<doc>ALU Alpha Instruction</doc>
 <bitfield high="4" low="0" name="SEL_A">
 <use-enum ref="ENUM166" />
 </bitfield>
@@ -4857,13 +5003,15 @@ and C.</doc>
 <bitfield high="30" low="30" name="CLAMP">
 <use-enum ref="ENUM171" />
 </bitfield>
-<doc>Specifies clamp mode for this instruction.</doc></reg32>
+<doc>Specifies clamp mode for this instruction.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x46C0" length="64" stride="0x0004">
-<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0">This table
-specifies the RGB source and destination addresses for up to 64 ALU
-instructions. The ALU expects 6 source operands - three for color
-(rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).
+<stripe length="64" offset="0x46C0" stride="0x0004">
+<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0">
+<doc>This table specifies the RGB source and destination addresses
+for up to 64 ALU instructions. The ALU expects 6 source operands -
+three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1,
+a2).</doc>
 <bitfield high="5" low="0" name="ADDR0" />
 <doc>Specifies the identity of source operands rgb0, rgb1, and
 rgb2. Values 0 through 31 specify a location within the current
@@ -4892,11 +5040,12 @@ this instruction are written to the output fifo.</doc>
 <bitfield high="30" low="29" name="TARGET">
 <use-enum ref="ENUM164" />
 </bitfield>
-<doc>Specifies which frame buffer target to write to.</doc></reg32>
+<doc>Specifies which frame buffer target to write to.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x48C0" length="64" stride="0x0004">
-<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0">ALU RGB
-Instruction
+<stripe length="64" offset="0x48C0" stride="0x0004">
+<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0">
+<doc>ALU RGB Instruction</doc>
 <bitfield high="4" low="0" name="SEL_A">
 <use-enum ref="ENUM173" />
 </bitfield>
@@ -4986,11 +5135,12 @@ value="0">
 </bitfield>
 <doc>Specifies whether to insert a NOP instruction after this. This
 would get specified in order to meet dependency requirements for
-the pre-subtract inputs.</doc></reg32>
+the pre-subtract inputs.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4610" length="4" stride="0x0004">
-<reg32 access="rw" name="US_CODE_ADDR" offset="0x0">Code Address
-for Indirection Levels 0 to 3
+<stripe length="4" offset="0x4610" stride="0x0004">
+<reg32 access="rw" name="US_CODE_ADDR" offset="0x0">
+<doc>Code Address for Indirection Levels 0 to 3</doc>
 <bitfield high="5" low="0" name="ALU_START" />
 <doc>Specifies the start address of the ALU microcode segment
 associated with the current indirection level (0:63)</doc>
@@ -5008,12 +5158,14 @@ with the current indirection level (1:32)</doc>
 level</doc>
 <bitfield high="23" low="23" name="W_OUT" />
 <doc>Indicates at least one W output instruction at this
-level</doc></reg32>
+level</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4608">Specifies
-the offset and size for the ALU and Texture micrcode. These values
-are used to support relocatable code, and to support register
-writes to the code store without requiring a pipeline flush.
+<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4608">
+<doc>Specifies the offset and size for the ALU and Texture
+micrcode. These values are used to support relocatable code, and to
+support register writes to the code store without requiring a
+pipeline flush.</doc>
 <bitfield high="5" low="0" name="ALU_OFFSET" />
 <doc>Specifies the offset for the ALU code. This value is added to
 the ALU_START field in the US_CODE_ADDR registers (0:63)</doc>
@@ -5025,9 +5177,10 @@ the ALU_START field in the US_CODE_ADDR registers (0:63)</doc>
 to the TEX_START field in the US_CODE_ADDR registers (0:31)</doc>
 <bitfield high="23" low="18" name="TEX_SIZE" />
 <doc>Specifies the total size for the Texture code for all levels
-(0:32)</doc></reg32>
-<reg32 access="rw" name="US_CONFIG" offset="0x4600">Shader
-Configuration
+(0:32)</doc>
+</reg32>
+<reg32 access="rw" name="US_CONFIG" offset="0x4600">
+<doc>Shader Configuration</doc>
 <bitfield high="2" low="0" name="NLEVEL">
 <value name="LEVEL_3_ONLY" value="0">
 <doc>Level 3 only (normal DX7-style texturing)</doc>
@@ -5047,11 +5200,12 @@ Configuration
 <use-enum ref="ENUM178" />
 </bitfield>
 <doc>Specifies whether or not the texture code for the first valid
-level is enabled</doc></reg32>
-<stripe addr="0x46A4" length="4" stride="0x0004">
-<reg32 access="rw" name="US_OUT_FMT" offset="0x0">Specifies how the
-shader output is written to the fog unit for each of up to four
-render targets
+level is enabled</doc>
+</reg32>
+<stripe length="4" offset="0x46A4" stride="0x0004">
+<reg32 access="rw" name="US_OUT_FMT" offset="0x0">
+<doc>Specifies how the shader output is written to the fog unit for
+each of up to four render targets</doc>
 <bitfield high="4" low="0" name="OUT_FMT">
 <use-enum ref="ENUM179" />
 </bitfield>
@@ -5074,17 +5228,19 @@ render targets
 <doc>Specifies the source for components C0, C1, C2, C3</doc>
 <bitfield high="19" low="16" name="OUT_SIGN" />
 <doc>Mask specifying whether components C3, C2, C1 and C0 are
-signed (C4_8, C_16, C2_16 and C4_16 formats only)</doc></reg32>
+signed (C4_8, C_16, C2_16 and C4_16 formats only)</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_PIXSIZE" offset="0x4604">Shader pixel
-size. This register specifies the size and partitioning of the
-current pixel stack frame
+<reg32 access="rw" name="US_PIXSIZE" offset="0x4604">
+<doc>Shader pixel size. This register specifies the size and
+partitioning of the current pixel stack frame</doc>
 <bitfield high="4" low="0" name="PIX_SIZE" />
 <doc>Specifies the total size of the current pixel stack frame
-(1:32)</doc></reg32>
-<stripe addr="0x4620" length="32" stride="0x0004">
-<reg32 access="rw" name="US_TEX_INST" offset="0x0">Texture
-Instruction
+(1:32)</doc>
+</reg32>
+<stripe length="32" offset="0x4620" stride="0x0004">
+<reg32 access="rw" name="US_TEX_INST" offset="0x0">
+<doc>Texture Instruction</doc>
 <bitfield high="4" low="0" name="SRC_ADDR" />
 <doc>Specifies the location (within the shader pixel stack frame)
 of the texture address for this instruction</doc>
@@ -5114,10 +5270,12 @@ instruction</doc>
 <doc>Specifies the operation taking place for this
 instruction</doc>
 <bitfield high="18" low="18" name="OMOD" />
-<doc>unused</doc></reg32>
+<doc>unused</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_W_FMT" offset="0x46B4">Specifies the
-source and format for the Depth (W) value output by the shader
+<reg32 access="rw" name="US_W_FMT" offset="0x46B4">
+<doc>Specifies the source and format for the Depth (W) value output
+by the shader</doc>
 <bitfield high="1" low="0" name="W_FMT">
 <value name="W" value="0">
 <doc>W</doc>
@@ -5139,37 +5297,38 @@ source and format for the Depth (W) value output by the shader
 <bitfield high="2" low="2" name="W_SRC">
 <use-enum ref="ENUM183" />
 </bitfield>
-<doc>Source for W</doc></reg32>
-<stripe addr="0x4C0C" length="32" stride="0x0010">
-<reg32 access="rw" name="US_ALU_CONST_A" offset="0x0">Shader
-Constant Color 0 Alpha Component
+<doc>Source for W</doc>
+</reg32>
+<stripe length="32" offset="0x4C0C" stride="0x0010">
+<reg32 access="rw" name="US_ALU_CONST_A" offset="0x0">
+<doc>Shader Constant Color 0 Alpha Component</doc>
 <bitfield high="23" low="0" name="KA" />
-<doc>Specifies the alpha component; (S16E7) fixed
-format.</doc></reg32>
+<doc>Specifies the alpha component; (S16E7) fixed format.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4C08" length="32" stride="0x0010">
-<reg32 access="rw" name="US_ALU_CONST_B" offset="0x0">Shader
-Constant Color 0 Blue Component
+<stripe length="32" offset="0x4C08" stride="0x0010">
+<reg32 access="rw" name="US_ALU_CONST_B" offset="0x0">
+<doc>Shader Constant Color 0 Blue Component</doc>
 <bitfield high="23" low="0" name="KB" />
-<doc>Specifies the blue component; (S16E7) fixed
-format.</doc></reg32>
+<doc>Specifies the blue component; (S16E7) fixed format.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4C04" length="32" stride="0x0010">
-<reg32 access="rw" name="US_ALU_CONST_G" offset="0x0">Shader
-Constant Color 0 Green Component
+<stripe length="32" offset="0x4C04" stride="0x0010">
+<reg32 access="rw" name="US_ALU_CONST_G" offset="0x0">
+<doc>Shader Constant Color 0 Green Component</doc>
 <bitfield high="23" low="0" name="KG" />
-<doc>Specifies the green component; (S16E7) fixed
-format.</doc></reg32>
+<doc>Specifies the green component; (S16E7) fixed format.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4C00" length="32" stride="0x0010">
-<reg32 access="rw" name="US_ALU_CONST_R" offset="0x0">Shader
-Constant Color 0 Red Component
+<stripe length="32" offset="0x4C00" stride="0x0010">
+<reg32 access="rw" name="US_ALU_CONST_R" offset="0x0">
+<doc>Shader Constant Color 0 Red Component</doc>
 <bitfield high="23" low="0" name="KR" />
-<doc>Specifies the red component; (S16E7) fixed
-format.</doc></reg32>
+<doc>Specifies the red component; (S16E7) fixed format.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C">Control
-Bits for User Clip Planes and Clipping
+<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C">
+<doc>Control Bits for User Clip Planes and Clipping</doc>
 <bitfield high="0" low="0" name="UCP_ENA_0" />
 <doc>Enable User Clip Plane 0</doc>
 <bitfield high="1" low="1" name="UCP_ENA_1" />
@@ -5194,9 +5353,10 @@ TCL</doc>
 <doc>Cull Primitives against UCPS, but don`t clip</doc>
 <bitfield high="18" low="18" name="BOUNDARY_EDGE_FLAG_ENA" />
 <doc>If set, boundary edges are highlighted, else they are not
-highlighted</doc></reg32>
-<reg32 access="rw" name="VAP_CNTL" offset="0x2080">Vertex
-Assembler/Processor Control Register
+highlighted</doc>
+</reg32>
+<reg32 access="rw" name="VAP_CNTL" offset="0x2080">
+<doc>Vertex Assembler/Processor Control Register</doc>
 <bitfield high="3" low="0" name="PVS_NUM_SLOTS" />
 <doc>Specifies the number of vertex slots to be used in the VAP PVS
 process. A slot represents a single vertex storage location1 across
@@ -5223,9 +5383,10 @@ used which is one less than the number of vertices (i.e. a 12 means
 <bitfield high="22" low="22" name="DX_CLIP_SPACE_DEF">
 <use-enum ref="ENUM184" />
 </bitfield>
-<doc>Clip space is defined as:</doc></reg32>
-<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140">Vertex
-Assemblen/Processor Control Status
+<doc>Clip space is defined as:</doc>
+</reg32>
+<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140">
+<doc>Vertex Assemblen/Processor Control Status</doc>
 <bitfield high="1" low="0" name="VC_SWAP" />
 <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD
 becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3
@@ -5250,10 +5411,11 @@ circuit.</doc>
 <bitfield high="30" low="30" name="REGPIPE_BUSY" />
 <doc>Register Pipeline is Busy. Read-only.</doc>
 <bitfield high="31" low="31" name="VAP_BUSY" />
-<doc>VAP Engine is Busy. Read-only.</doc></reg32>
-<stripe addr="0x2150" length="8" stride="0x0004">
+<doc>VAP Engine is Busy. Read-only.</doc>
+</reg32>
+<stripe length="8" offset="0x2150" stride="0x0004">
 <reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0">
-Programmable Stream Control Word 0
+<doc>Programmable Stream Control Word 0</doc>
 <bitfield high="3" low="0" name="DATA_TYPE_0" />
 <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1
 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4
@@ -5306,12 +5468,14 @@ VAP_PSC_SGN_NORM_CNTL description for details.</doc>
 <bitfield high="30" low="30" name="SIGNED_1" />
 <doc>See SIGNED_0</doc>
 <bitfield high="31" low="31" name="NORMALIZE_1" />
-<doc>See NORMALIZE_0</doc></reg32>
+<doc>See NORMALIZE_0</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2290" length="16" stride="0x0004">
+<stripe length="16" offset="0x2290" stride="0x0004">
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX"
-offset="0x0">Programmable Vertex Shader Flow Control Loop Index
-Register 0
+offset="0x0">
+<doc>Programmable Vertex Shader Flow Control Loop Index Register
+0</doc>
 <bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" />
 <doc>This field stores the automatic loop index register init
 value. This is an 8-bit unsigned value 0-255. This field is only
@@ -5320,10 +5484,11 @@ used if the corresponding control flow instruction is a loop.</doc>
 <doc>This field stores the automatic loop index register step
 value. This is an 8-bit 2`s comp signed value -128-127. This field
 is only used if the corresponding control flow instruction is a
-loop.</doc></reg32>
+loop.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084">Vertex
-Fetcher Control
+<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084">
+<doc>Vertex Fetcher Control</doc>
 <bitfield high="3" low="0" name="PRIM_TYPE" />
 <doc>Primitive Type 0 : None (will not trigger Setup Engine to run)
 1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 :
@@ -5355,9 +5520,10 @@ indices. Bits 23-16 are used as the index for AOS 0 (These are 0
 for 16-bit indices) Bits 15-0 are used as the index for AOS 1-15.
 This mode was added specifically for HOS usage</doc>
 <bitfield high="31" low="16" name="NUM_VERTICES" />
-<doc>Number of vertices in the command packet.</doc></reg32>
-<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0">Vertex
-Array of Structures Control
+<doc>Number of vertices in the command packet.</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0">
+<doc>Vertex Array of Structures Control</doc>
 <bitfield high="4" low="0" name="VTX_NUM_ARRAYS" />
 <doc>The number of arrays required to represent the current vertex
 type. Each Array is described by the following three fields:
@@ -5403,9 +5569,10 @@ data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc>
 <bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" />
 <doc>See AOS_0_FETCH_SIZE</doc>
 <bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" />
-<doc>See AOS_0_FETCH_SIZE</doc></reg32>
-<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180">VAP
-Vertex State Control Register
+<doc>See AOS_0_FETCH_SIZE</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180">
+<doc>VAP Vertex State Control Register</doc>
 <bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" />
 <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User
 Color 1 3 : Reserved</doc>
@@ -5437,23 +5604,24 @@ written.</doc>
 <bitfield high="18" low="18" name="USE_ADDR_IND_TBL" />
 <doc>0 : Use vertex state addresses directly to write to vertex
 state memory. 1 : Use Address Indirection table to write to vertex
-state memory for lower 64 DWORD addresses.</doc></reg32>
-<stripe addr="0x2430" length="4" stride="0x0004">
+state memory for lower 64 DWORD addresses.</doc>
+</reg32>
+<stripe length="4" offset="0x2430" stride="0x0004">
 <reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0" />
 </stripe>
-<stripe addr="0x232C" length="8" stride="0x0010">
+<stripe length="8" offset="0x232C" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0" />
 </stripe>
-<stripe addr="0x2328" length="8" stride="0x0010">
+<stripe length="8" offset="0x2328" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0" />
 </stripe>
-<stripe addr="0x2324" length="8" stride="0x0010">
+<stripe length="8" offset="0x2324" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0" />
 </stripe>
-<stripe addr="0x2470" length="8" stride="0x0004">
+<stripe length="8" offset="0x2470" stride="0x0004">
 <reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0" />
 </stripe>
-<stripe addr="0x2320" length="8" stride="0x0010">
+<stripe length="8" offset="0x2320" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0" />
 </stripe>
 <reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424" />
@@ -5483,16 +5651,16 @@ state memory for lower 64 DWORD addresses.</doc></reg32>
 <reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C" />
 <reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" offset="0x2428" />
 <reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" offset="0x242C" />
-<stripe addr="0x23AC" length="8" stride="0x0010">
+<stripe length="8" offset="0x23AC" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0" />
 </stripe>
-<stripe addr="0x23A8" length="8" stride="0x0010">
+<stripe length="8" offset="0x23A8" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0" />
 </stripe>
-<stripe addr="0x23A0" length="8" stride="0x0010">
+<stripe length="8" offset="0x23A0" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0" />
 </stripe>
-<stripe addr="0x23A4" length="8" stride="0x0010">
+<stripe length="8" offset="0x23A4" stride="0x0010">
 <reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0" />
 </stripe>
 <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C" />
@@ -5500,8 +5668,8 @@ state memory for lower 64 DWORD addresses.</doc></reg32>
 <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464" />
 <reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" offset="0x249C" />
 <reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460" />
-<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C">Z Buffer
-Band-Width Control Bit Defa
+<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C">
+<doc>Z Buffer Band-Width Control Bit Defa</doc>
 <bitfield high="0" low="0" name="HIZ_ENABLE">
 <use-enum ref="ENUM187" />
 </bitfield>
@@ -5538,8 +5706,10 @@ then evicted to main memory. The color value is supplied through
 the ZB_DEPTHCLEARVALUE register.</doc>
 <bitfield high="6" low="6" name="FORCE_COMPRESSED_STENCIL" />
 <doc>Enabling this bit will force all the compressed stencil values
-to be</doc></reg32>
-<reg32 access="rw" name="ZB_CNTL" offset="0x4F00">Z Buffer Control
+to be</doc>
+</reg32>
+<reg32 access="rw" name="ZB_CNTL" offset="0x4F00">
+<doc>Z Buffer Control</doc>
 <bitfield high="0" low="0" name="STENCIL_ENABLE">
 <use-enum ref="ENUM178" />
 </bitfield>
@@ -5568,9 +5738,10 @@ used if the quad is generated from a back faced primitive. If the
 STENCIL_FRONT_BACK is not set, then
 stencilfunc/stencilfail/stencilzpass/stencilzfail registers
 determine the operation independent of the front/back face state of
-the quad.</doc></reg32>
-<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10">Format of the
-Data in the Z buffer
+the quad.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10">
+<doc>Format of the Data in the Z buffer</doc>
 <bitfield high="3" low="0" name="DEPTHFORMAT">
 <use-enum ref="ENUM196" />
 </bitfield>
@@ -5592,23 +5763,26 @@ Data in the Z buffer
 <doc>8 bytes per plane equation, no bytes for stencil</doc>
 </value>
 </bitfield>
-<doc>This bit is unused</doc></reg32>
+<doc>This bit is unused</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44">
-Hierarchical Z Memory Offset
+<doc>Hierarchical Z Memory Offset</doc>
 <bitfield high="16" low="2" name="HIZ_OFFSET" />
 <doc>DWORD offset into HiZ RAM. A DWORD can hold an 8-bit HiZ value
 for 4 blocks, so this offset is aligned on 4 4x4 blocks. In each
 pipe, the HIZ RAM DWORD address is generated from a pixel x[11:0] ,
 y[11:0] as follows: HIZ_DWORD_ADDRESS[13:0] = HIZ_OFFSET[16:3] +
-Y[11:3] * HIZ_PITCH[13:5] + X[11:5].</doc></reg32>
+Y[11:3] * HIZ_PITCH[13:5] + X[11:5].</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50">
-Hierarchical Z Read Index
+<doc>Hierarchical Z Read Index</doc>
 <bitfield high="16" low="2" name="HIZ_RDINDEX" />
 <doc>Read index into HiZ RAM. The index must start on a DWORD
 boundary. RDINDEX words much like WRINDEX. Every read from
-HIZ_DWORD will increment the register by 2.</doc></reg32>
+HIZ_DWORD will increment the register by 2.</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48">
-Hierarchical Z Write Index
+<doc>Hierarchical Z Write Index</doc>
 <bitfield high="16" low="2" name="HIZ_WRINDEX" />
 <doc>Self-incrementing write index into the HiZ RAM. Starting write
 index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is
@@ -5616,9 +5790,10 @@ written, this index will increment by two DWORD, this due to the
 fact that there are 2 pipes and the data is broadcasted to both
 pipes. HIZ_OFFSET and HIZ_PITCH are not used to compute read/write
 address to HIZ ram, when it is accessed through WRINDEX and
-DWORD</doc></reg32>
-<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04">Z and
-Stencil Function Control
+DWORD</doc>
+</reg32>
+<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04">
+<doc>Z and Stencil Function Control</doc>
 <bitfield high="2" low="0" name="ZFUNC">
 <use-enum ref="ENUM202" />
 </bitfield>
@@ -5653,11 +5828,12 @@ not enabled) for back faced quads, if STENCIL_FRONT_BACK = 1</doc>
 <bitfield high="26" low="24" name="STENCILZFAIL_BF" />
 <doc>Same encoding as STENCILFAIL. Specifies the stencil value to
 be written if the stencil test passes and the Z test fails for back
-faced quads, if STENCIL_FRONT_BACK =1</doc></reg32>
+faced quads, if STENCIL_FRONT_BACK =1</doc>
+</reg32>
 </group>
 <group name="r500_regs" prepend="R500_">
-<reg32 access="r" name="CP_CSQ2_STAT" offset="0x07FC">(RO) Command
-Stream Indirect Queue 2 Status
+<reg32 access="r" name="CP_CSQ2_STAT" offset="0x07FC">
+<doc>(RO) Command Stream Indirect Queue 2 Status</doc>
 <bitfield high="9" low="0" name="CSQ_WPTR_INDIRECT" />
 <doc>Current Write Pointer into the Indirect Queue. Default =
 0.</doc>
@@ -5666,21 +5842,26 @@ Stream Indirect Queue 2 Status
 0.</doc>
 <bitfield high="29" low="20" name="CSQ_WPTR_INDIRECT2" />
 <doc>Current Write Pointer into the Indirect Queue. Default =
-0.</doc></reg32>
-<reg32 access="w" name="CP_CSQ_ADDR" offset="0x07F0">(WO) Command
-Stream Queue Address
+0.</doc>
+</reg32>
+<reg32 access="w" name="CP_CSQ_ADDR" offset="0x07F0">
+<doc>(WO) Command Stream Queue Address</doc>
 <bitfield high="11" low="2" name="CSQ_ADDR" />
 <doc>Address into the Command Stream Queue which is to be read
 from. Used for debug, to read the contents of the Command Stream
-Queue.</doc></reg32>
-<reg32 access="rw" name="CP_CSQ_APER_INDIRECT" offset="0x1300">IB1
-Aperture map in RBBM - PIO</reg32>
-<reg32 access="rw" name="CP_CSQ_APER_INDIRECT2" offset="0x1200">IB2
-Aperture map in RBBM - PIO</reg32>
+Queue.</doc>
+</reg32>
+<reg32 access="rw" name="CP_CSQ_APER_INDIRECT" offset="0x1300">
+<doc>IB1 Aperture map in RBBM - PIO</doc>
+</reg32>
+<reg32 access="rw" name="CP_CSQ_APER_INDIRECT2" offset="0x1200">
+<doc>IB2 Aperture map in RBBM - PIO</doc>
+</reg32>
 <reg32 access="rw" name="CP_CSQ_APER_PRIMARY" offset="0x1000">
-Primary Aperture map in RBBM - PIO</reg32>
-<reg32 access="rw" name="CP_CSQ_AVAIL" offset="0x07B8">Command
-Stream Queue Available Counts
+<doc>Primary Aperture map in RBBM - PIO</doc>
+</reg32>
+<reg32 access="rw" name="CP_CSQ_AVAIL" offset="0x07B8">
+<doc>Command Stream Queue Available Counts</doc>
 <bitfield high="9" low="0" name="CSQ_CNT_PRIMARY" />
 <doc>Count of available dwords in the queue for the Primary Stream.
 Read Only.</doc>
@@ -5689,9 +5870,10 @@ Read Only.</doc>
 Stream. Read Only.</doc>
 <bitfield high="29" low="20" name="CSQ_CNT_INDIRECT2" />
 <doc>Count of available dwords in the queue for the Indirect
-Stream. Read Only.</doc></reg32>
-<reg32 access="rw" name="CP_CSQ_CNTL" offset="0x0740">Command
-Stream Queue Control
+Stream. Read Only.</doc>
+</reg32>
+<reg32 access="rw" name="CP_CSQ_CNTL" offset="0x0740">
+<doc>Command Stream Queue Control</doc>
 <bitfield high="31" low="28" name="CSQ_MODE">
 <value name="PRIMARY_DISABLED" value="0">
 <doc>Primary Disabled, Indirect Disabled.</doc>
@@ -5718,11 +5900,13 @@ or pull mode (Bus-Master). Encodings are chosen to be compatible
 with Rage128. 0= Primary Disabled, Indirect Disabled. 1= Primary
 PIO, Indirect Disabled. 2= Primary BM, Indirect Disabled. 3,5,7=
 Primary PIO, Indirect BM. 4,6,8= Primary BM, Indirect BM. 9-14=
-Reserved. 15= Primary PIO, Indirect PIO Default = 0</doc></reg32>
-<reg32 access="r" name="CP_CSQ_DATA" offset="0x07F4">(RO) Command
-Stream Queue Data</reg32>
-<reg32 access="rw" name="CP_CSQ_MODE" offset="0x0744">Alternate
-Command Stream Queue Control
+Reserved. 15= Primary PIO, Indirect PIO Default = 0</doc>
+</reg32>
+<reg32 access="r" name="CP_CSQ_DATA" offset="0x07F4">
+<doc>(RO) Command Stream Queue Data</doc>
+</reg32>
+<reg32 access="rw" name="CP_CSQ_MODE" offset="0x0744">
+<doc>Alternate Command Stream Queue Control</doc>
 <bitfield high="6" low="0" name="INDIRECT2_START" />
 <doc>Start location of Indirect Queue #2 in the command cache. This
 value also sets the size in double octwords of the Indirect Queue
@@ -5760,9 +5944,10 @@ variable in the CP_CSQ_CNTL register.</doc>
 <bitfield high="31" low="31" name="CSQ_PRIMARY_ENABLE" />
 <doc>Enables Primary Buffer. If this bit is set, the CP_CSQ_MODE
 register overrides the operation of the CSQ_MODE variable in the
-CP_CSQ_CNTL register.</doc></reg32>
-<reg32 access="r" name="CP_CSQ_STAT" offset="0x07F8">(RO) Command
-Stream Queue Status
+CP_CSQ_CNTL register.</doc>
+</reg32>
+<reg32 access="r" name="CP_CSQ_STAT" offset="0x07F8">
+<doc>(RO) Command Stream Queue Status</doc>
 <bitfield high="9" low="0" name="CSQ_RPTR_PRIMARY" />
 <doc>Current Read Pointer into the Primary Queue. Default =
 0.</doc>
@@ -5771,41 +5956,48 @@ Stream Queue Status
 0.</doc>
 <bitfield high="29" low="20" name="CSQ_RPTR_INDIRECT" />
 <doc>Current Read Pointer into the Indirect Queue. Default =
-0.</doc></reg32>
-<reg32 access="rw" name="CP_GUI_COMMAND" offset="0x0728">Command
-for PIO GUI DMAs</reg32>
+0.</doc>
+</reg32>
+<reg32 access="rw" name="CP_GUI_COMMAND" offset="0x0728">
+<doc>Command for PIO GUI DMAs</doc>
+</reg32>
 <reg32 access="rw" name="CP_GUI_DST_ADDR" offset="0x0724">
-Destination Address for PIO GUI DMAs</reg32>
-<reg32 access="rw" name="CP_GUI_SRC_ADDR" offset="0x0720">Source
-Address for PIO GUI DMAs</reg32>
-<reg32 access="rw" name="CP_IB2_BASE" offset="0x0730">Indirect
-Buffer 2 Base
+<doc>Destination Address for PIO GUI DMAs</doc>
+</reg32>
+<reg32 access="rw" name="CP_GUI_SRC_ADDR" offset="0x0720">
+<doc>Source Address for PIO GUI DMAs</doc>
+</reg32>
+<reg32 access="rw" name="CP_IB2_BASE" offset="0x0730">
+<doc>Indirect Buffer 2 Base</doc>
 <bitfield high="31" low="2" name="IB2_BASE" />
 <doc>Indirect Buffer 2 Base. Address of the beginning of the
 indirect buffer. Only DWORD access is allowed to this
-register.</doc></reg32>
-<reg32 access="rw" name="CP_IB2_BUFSZ" offset="0x0734">Indirect
-Buffer 2 Size
+register.</doc>
+</reg32>
+<reg32 access="rw" name="CP_IB2_BUFSZ" offset="0x0734">
+<doc>Indirect Buffer 2 Size</doc>
 <bitfield high="22" low="0" name="IB2_BUFSZ" />
 <doc>Indirect Buffer 2 Size. This size is expressed in dwords. This
 field is an initiator to begin fetching commands from the Indirect
 Buffer. Only DWORD access is allowed to this register. Default =
-0</doc></reg32>
-<reg32 access="rw" name="CP_IB_BASE" offset="0x0738">Indirect
-Buffer Base
+0</doc>
+</reg32>
+<reg32 access="rw" name="CP_IB_BASE" offset="0x0738">
+<doc>Indirect Buffer Base</doc>
 <bitfield high="31" low="2" name="IB_BASE" />
 <doc>Indirect Buffer Base. Address of the beginning of the indirect
-buffer. Only DWORD access is allowed to this
-register.</doc></reg32>
-<reg32 access="rw" name="CP_IB_BUFSZ" offset="0x073C">Indirect
-Buffer Size
+buffer. Only DWORD access is allowed to this register.</doc>
+</reg32>
+<reg32 access="rw" name="CP_IB_BUFSZ" offset="0x073C">
+<doc>Indirect Buffer Size</doc>
 <bitfield high="22" low="0" name="IB_BUFSZ" />
 <doc>Indirect Buffer Size. This size is expressed in dwords. This
 field is an initiator to begin fetching commands from the Indirect
 Buffer. Only DWORD access is allowed to this register. Default =
-0</doc></reg32>
-<reg32 access="rw" name="CP_ME_CNTL" offset="0x07D0">Micro Engine
-Control
+0</doc>
+</reg32>
+<reg32 access="rw" name="CP_ME_CNTL" offset="0x07D0">
+<doc>Micro Engine Control</doc>
 <bitfield high="15" low="0" name="ME_STAT" />
 <doc>Status of MicroEngine internal registers. This value depends
 on the current value of the ME_STATMUX field. Read Only.</doc>
@@ -5821,30 +6013,35 @@ Free-running Mode. Default = 1</doc>
 <bitfield high="31" low="31" name="ME_STEP" />
 <doc>Step the MicroEngine by one instruction. Writing a `1` to this
 field causes the MicroEngine to step by one instruction, if and
-only if the ME_MODE bit is a `0`. Write Only.</doc></reg32>
+only if the ME_MODE bit is a `0`. Write Only.</doc>
+</reg32>
 <reg32 access="rw" name="CP_ME_RAM_ADDR" offset="0x07D4">
-MicroEngine RAM Address
+<doc>MicroEngine RAM Address</doc>
 <bitfield high="7" low="0" name="ME_RAM_ADDR" />
-<doc>MicroEngine RAM Address (Write Mode) Writing
-this</doc></reg32>
+<doc>MicroEngine RAM Address (Write Mode) Writing this</doc>
+</reg32>
 <reg32 access="rw" name="CP_ME_RAM_DATAH" offset="0x07DC">
-MicroEngine RAM Data High
+<doc>MicroEngine RAM Data High</doc>
 <bitfield high="7" low="0" name="ME_RAM_DATAH" />
 <doc>MicroEngine RAM Data High Used to load the MicroEngine
-RAM.</doc></reg32>
+RAM.</doc>
+</reg32>
 <reg32 access="rw" name="CP_ME_RAM_DATAL" offset="0x07E0">
-MicroEngine RAM Data Low</reg32>
+<doc>MicroEngine RAM Data Low</doc>
+</reg32>
 <reg32 access="rw" name="CP_ME_RAM_RADDR" offset="0x07D8">
-MicroEngine RAM Read Address
+<doc>MicroEngine RAM Read Address</doc>
 <bitfield high="7" low="0" name="ME_RAM_RADDR" />
-<doc>MicroEngine RAM Address (Read Mode) Writing</doc></reg32>
-<reg32 access="rw" name="CP_RB_BASE" offset="0x0700">Ring Buffer
-Base
+<doc>MicroEngine RAM Address (Read Mode) Writing</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_BASE" offset="0x0700">
+<doc>Ring Buffer Base</doc>
 <bitfield high="31" low="2" name="RB_BASE" />
 <doc>Ring Buffer Base. Address of the beginning of the ring
-buffer.</doc></reg32>
-<reg32 access="rw" name="CP_RB_CNTL" offset="0x0704">Ring Buffer
-Control
+buffer.</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_CNTL" offset="0x0704">
+<doc>Ring Buffer Control</doc>
 <bitfield high="5" low="0" name="RB_BUFSZ" />
 <doc>Ring Buffer Size. This size is expressed in log2 of the actual
 size. Values 0 and 1 are clamped to an 8 DWORD ring buffer. A value
@@ -5891,34 +6088,38 @@ performance penalty. Default = 0</doc>
 <doc>Ring Buffer Read Pointer Write Transfer Enable. When set the
 contents of the CP_RB_RPTR_WR register is transferred to the active
 read pointer (CP_RB_RPTR) whenever the CP_RB_WPTR register is
-written. Default =0</doc></reg32>
-<reg32 access="rw" name="CP_RB_RPTR" offset="0x0710">Ring Buffer
-Read Pointer Address (RO)
+written. Default =0</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_RPTR" offset="0x0710">
+<doc>Ring Buffer Read Pointer Address (RO)</doc>
 <bitfield high="22" low="0" name="RB_RPTR" />
 <doc>Ring Buffer Read Pointer. This is an index (in dwords) of the
-current element being read from the ring buffer.</doc></reg32>
-<reg32 access="rw" name="CP_RB_RPTR_ADDR" offset="0x070C">Ring
-Buffer Read Pointer Address
+current element being read from the ring buffer.</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_RPTR_ADDR" offset="0x070C">
+<doc>Ring Buffer Read Pointer Address</doc>
 <bitfield high="1" low="0" name="RB_RPTR_SWAP" />
 <doc>Swap control of the reported read pointer address. See
 CP_RB_CNTL.BUF_SWAP for the encoding.</doc>
 <bitfield high="31" low="2" name="RB_RPTR_ADDR" />
 <doc>Ring Buffer Read Pointer Address. Address of the Host`s copy
-of the Read Pointer. CP_RB_RPTR (RO) Ring Buffer Read
-Pointer</doc></reg32>
-<reg32 access="rw" name="CP_RB_RPTR_WR" offset="0x071C">Writable
-Ring Buffer Read Pointer Address
+of the Read Pointer. CP_RB_RPTR (RO) Ring Buffer Read Pointer</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_RPTR_WR" offset="0x071C">
+<doc>Writable Ring Buffer Read Pointer Address</doc>
 <bitfield high="22" low="0" name="RB_RPTR_WR" />
 <doc>Writable Ring Buffer Read Pointer. Writable for updating the
-RB_RPTR after an ACPI.</doc></reg32>
-<reg32 access="rw" name="CP_RB_WPTR" offset="0x0714">(RO) Ring
-Buffer Write Pointer
+RB_RPTR after an ACPI.</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_WPTR" offset="0x0714">
+<doc>(RO) Ring Buffer Write Pointer</doc>
 <bitfield high="22" low="0" name="RB_WPTR" />
 <doc>Ring Buffer Write Pointer. This is an index (in dwords) of the
 last known element to be written to the ring buffer (by the
-host).</doc></reg32>
-<reg32 access="rw" name="CP_RB_WPTR_DELAY" offset="0x0718">Ring
-Buffer Write Pointer Delay
+host).</doc>
+</reg32>
+<reg32 access="rw" name="CP_RB_WPTR_DELAY" offset="0x0718">
+<doc>Ring Buffer Write Pointer Delay</doc>
 <bitfield high="27" low="0" name="PRE_WRITE_TIMER" />
 <doc>Pre-Write Timer. The number of clocks that a write to the
 CP_RB_WPTR register will be delayed until actually taking effect.
@@ -5927,15 +6128,18 @@ Default = 0</doc>
 <doc>Pre-Write Limit. The number of times that the CP_RB_WPTR
 register can be written (while the PRE_WRITE_TIMER has not expired)
 before the CP_RB_WPTR register is forced to be updated with the
-most recently written value. Default = 0</doc></reg32>
-<reg32 access="rw" name="CP_RESYNC_ADDR" offset="0x0778">Raster
-Engine Sync Address (WO)
+most recently written value. Default = 0</doc>
+</reg32>
+<reg32 access="rw" name="CP_RESYNC_ADDR" offset="0x0778">
+<doc>Raster Engine Sync Address (WO)</doc>
 <bitfield high="2" low="0" name="RESYNC_ADDR" />
-<doc>Scratch Register Offset Address.</doc></reg32>
-<reg32 access="rw" name="CP_RESYNC_DATA" offset="0x077C">Raster
-Engine Sync Data (WO)</reg32>
-<reg32 access="r" name="CP_STAT" offset="0x07C0">(RO) Busy Status
-Signals
+<doc>Scratch Register Offset Address.</doc>
+</reg32>
+<reg32 access="rw" name="CP_RESYNC_DATA" offset="0x077C">
+<doc>Raster Engine Sync Data (WO)</doc>
+</reg32>
+<reg32 access="r" name="CP_STAT" offset="0x07C0">
+<doc>(RO) Busy Status Signals</doc>
 <bitfield high="0" low="0" name="MRU_BUSY" />
 <doc>Memory Read Unit Busy.</doc>
 <bitfield high="1" low="1" name="MWU_BUSY" />
@@ -5965,16 +6169,21 @@ Signals
 <bitfield high="30" low="30" name="CMDSTRM_BUSY" />
 <doc>Command Stream Busy.</doc>
 <bitfield high="31" low="31" name="CP_BUSY" />
-<doc>CP Busy.</doc></reg32>
-<reg32 access="rw" name="CP_VID_COMMAND" offset="0x07CC">Command
-for PIO VID DMAs</reg32>
+<doc>CP Busy.</doc>
+</reg32>
+<reg32 access="rw" name="CP_VID_COMMAND" offset="0x07CC">
+<doc>Command for PIO VID DMAs</doc>
+</reg32>
 <reg32 access="rw" name="CP_VID_DST_ADDR" offset="0x07C8">
-Destination Address for PIO VID DMAs</reg32>
-<reg32 access="rw" name="CP_VID_SRC_ADDR" offset="0x07C4">Source
-Address for PIO VID DMAs</reg32>
-<reg32 access="rw" name="CP_VP_ADDR_CNTL" offset="0x07E8">Virtual
-vs Physical Address Control - Selects whether the address
-corresponds to a physical or virtual address in memory.
+<doc>Destination Address for PIO VID DMAs</doc>
+</reg32>
+<reg32 access="rw" name="CP_VID_SRC_ADDR" offset="0x07C4">
+<doc>Source Address for PIO VID DMAs</doc>
+</reg32>
+<reg32 access="rw" name="CP_VP_ADDR_CNTL" offset="0x07E8">
+<doc>Virtual vs Physical Address Control - Selects whether the
+address corresponds to a physical or virtual address in
+memory.</doc>
 <bitfield high="0" low="0" name="SCRATCH_ALT_VP_WR">
 <use-enum ref="ENUM209" />
 </bitfield>
@@ -6014,9 +6223,10 @@ corresponds to a physical or virtual address in memory.
 <bitfield high="9" low="9" name="RING_VP_FETCH">
 <use-enum ref="ENUM209" />
 </bitfield>
-<doc /></reg32>
+<doc />
+</reg32>
 <reg32 access="rw" name="RB3D_AARESOLVE_CTL" offset="0x4E88">
-Resolve Buffer Control. Unpipelined
+<doc>Resolve Buffer Control. Unpipelined</doc>
 <bitfield high="0" low="0" name="AARESOLVE_MODE" />
 <doc>Specifies if the color buffer is in resolve mode. The cache
 must be empty before changing this register.</doc>
@@ -6043,9 +6253,11 @@ average is not gamma corrected.</doc>
 <doc>Controls whether alpha is averaged in the resolve. 0 =&gt; the
 resolved alpha value is selected from the sample 0 value. 1=&gt;
 the resolved alpha value is a filtered (average) result of of the
-samples.</doc></reg32>
-<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04">Alpha
-Blend Control for Color Channels. Pipelined through the blender.
+samples.</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_BLENDCNTL" offset="0x4E04">
+<doc>Alpha Blend Control for Color Channels. Pipelined through the
+blender.</doc>
 <bitfield high="0" low="0" name="ALPHA_BLEND_ENABLE">
 <use-enum ref="ENUM5" />
 </bitfield>
@@ -6132,10 +6344,11 @@ reads</doc>
 </value>
 </bitfield>
 <doc>Enables source alpha one performance optimization to skip
-reads.</doc></reg32>
+reads.</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD"
-offset="0x4EA4">Discard src pixels greater than or equal to
-threshold.
+offset="0x4EA4">
+<doc>Discard src pixels greater than or equal to threshold.</doc>
 <bitfield high="7" low="0" name="BLUE" />
 <doc>Blue</doc>
 <bitfield high="15" low="8" name="GREEN" />
@@ -6143,9 +6356,11 @@ threshold.
 <bitfield high="23" low="16" name="RED" />
 <doc>Red</doc>
 <bitfield high="31" low="24" name="ALPHA" />
-<doc>Alpha</doc></reg32>
+<doc>Alpha</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD"
-offset="0x4EA0">Discard src pixels less than or equal to threshold.
+offset="0x4EA0">
+<doc>Discard src pixels less than or equal to threshold.</doc>
 <bitfield high="7" low="0" name="BLUE" />
 <doc>Blue</doc>
 <bitfield high="15" low="8" name="GREEN" />
@@ -6153,8 +6368,10 @@ offset="0x4EA0">Discard src pixels less than or equal to threshold.
 <bitfield high="23" low="16" name="RED" />
 <doc>Red</doc>
 <bitfield high="31" low="24" name="ALPHA" />
-<doc>Alpha</doc></reg32>
-<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00">Unpipelined.
+<doc>Alpha</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_CCTL" offset="0x4E00">
+<doc>Unpipelined.</doc>
 <bitfield high="6" low="5" name="NUM_MULTIWRITES">
 <use-enum ref="ENUM9" />
 </bitfield>
@@ -6198,13 +6415,13 @@ this feature will cause all the MRTs to use color channel mask
 <use-enum ref="ENUM5" />
 </bitfield>
 <doc>Enables independent color format for the MRTs. Disabling this
-feature will cause all the MRTs to use color format
-0.</doc></reg32>
-<stripe addr="0x4E38" length="4" stride="0x0004">
-<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0">Color buffer
-format and tiling control for all the multibuffers and the pitch of
-multibuffer 0. Unpipelined. The cache must be empty before any of
-the registers are changed.
+feature will cause all the MRTs to use color format 0.</doc>
+</reg32>
+<stripe length="4" offset="0x4E38" stride="0x0004">
+<reg32 access="rw" name="RB3D_COLORPITCH" offset="0x0">
+<doc>Color buffer format and tiling control for all the
+multibuffers and the pitch of multibuffer 0. Unpipelined. The cache
+must be empty before any of the registers are changed.</doc>
 <bitfield high="13" low="1" name="COLORPITCH" />
 <doc>3D destination pitch in multiples of 2-pixels.</doc>
 <bitfield high="16" low="16" name="COLORTILE">
@@ -6268,12 +6485,13 @@ format.</doc>
 <doc>ARGB4444</doc>
 </value>
 </bitfield>
-<doc>3D destination color format.</doc></reg32>
+<doc>3D destination color format.</doc>
+</reg32>
 </stripe>
 <reg32 access="rw" name="RB3D_COLOR_CHANNEL_MASK" offset="0x4E0C">
-3D Color Channel Mask. If all the channels used in the current
+<doc>3D Color Channel Mask. If all the channels used in the current
 color format are disabled, then the cb will discard all the
-incoming quads. Pipelined through the blender.
+incoming quads. Pipelined through the blender.</doc>
 <bitfield high="0" low="0" name="BLUE_MASK">
 <use-enum ref="ENUM16" />
 </bitfield>
@@ -6337,11 +6555,12 @@ incoming quads. Pipelined through the blender.
 <bitfield high="15" low="15" name="ALPHA_MASK3">
 <use-enum ref="ENUM16" />
 </bitfield>
-<doc>mask bit for the alpha channel of MRT 3</doc></reg32>
+<doc>mask bit for the alpha channel of MRT 3</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE" offset="0x4E14">
-Clear color that is used when the color mask is set to 00.
+<doc>Clear color that is used when the color mask is set to 00.
 Unpipelined. Program this register with a 32-bit value in ARGB8888
-or ARGB2101010 formats, ignoring the fields.
+or ARGB2101010 formats, ignoring the fields.</doc>
 <bitfield high="7" low="0" name="BLUE" />
 <doc>blue clear color</doc>
 <bitfield high="15" low="8" name="GREEN" />
@@ -6349,25 +6568,29 @@ or ARGB2101010 formats, ignoring the fields.
 <bitfield high="23" low="16" name="RED" />
 <doc>red clear color</doc>
 <bitfield high="31" low="24" name="ALPHA" />
-<doc>alpha clear color</doc></reg32>
+<doc>alpha clear color</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_AR"
-offset="0x46C0">Alpha and red clear color values that are used when
-the color mask is set to 00 in FP16 per component mode.
-Unpipelined.
+offset="0x46C0">
+<doc>Alpha and red clear color values that are used when the color
+mask is set to 00 in FP16 per component mode. Unpipelined.</doc>
 <bitfield high="15" low="0" name="RED" />
 <doc>red clear color</doc>
 <bitfield high="31" low="16" name="ALPHA" />
-<doc>alpha clear color</doc></reg32>
+<doc>alpha clear color</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_COLOR_CLEAR_VALUE_GB"
-offset="0x46C4">Green and blue clear color values that are used
-when the color mask is set to 00 in FP16 per component mode.
-Unpipelined.
+offset="0x46C4">
+<doc>Green and blue clear color values that are used when the color
+mask is set to 00 in FP16 per component mode. Unpipelined.</doc>
 <bitfield high="15" low="0" name="BLUE" />
 <doc>blue clear color</doc>
 <bitfield high="31" low="16" name="GREEN" />
-<doc>green clear color</doc></reg32>
+<doc>green clear color</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_CONSTANT_COLOR" offset="0x4E10">
-Constant color used by the blender. Pipelined through the blender.
+<doc>Constant color used by the blender. Pipelined through the
+blender.</doc>
 <bitfield high="7" low="0" name="BLUE" />
 <doc>blue constant color (For R520, this field is ignored, use
 RB3D_CONSTANT_COLOR_GB__BLUE instead)</doc>
@@ -6379,29 +6602,33 @@ RB3D_CONSTANT_COLOR_GB__GREEN instead)</doc>
 RB3D_CONSTANT_COLOR_AR__RED instead)</doc>
 <bitfield high="31" low="24" name="ALPHA" />
 <doc>alpha constant color (For R520, this field is ignored, use
-RB3D_CONSTANT_COLOR_AR__ALPHA instead)</doc></reg32>
+RB3D_CONSTANT_COLOR_AR__ALPHA instead)</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_CONSTANT_COLOR_AR" offset="0x4EF8">
-Constant color used by the blender. Pipelined through the blender.
+<doc>Constant color used by the blender. Pipelined through the
+blender.</doc>
 <bitfield high="15" low="0" name="RED" />
 <doc>red constant color in 0.10 fixed or FP16 format</doc>
 <bitfield high="31" low="16" name="ALPHA" />
-<doc>alpha constant color in 0.10 fixed or FP16
-format</doc></reg32>
+<doc>alpha constant color in 0.10 fixed or FP16 format</doc>
+</reg32>
 <reg32 access="rw" name="RB3D_CONSTANT_COLOR_GB" offset="0x4EFC">
-Constant color used by the blender. Pipelined through the blender.
+<doc>Constant color used by the blender. Pipelined through the
+blender.</doc>
 <bitfield high="15" low="0" name="BLUE" />
 <doc>blue constant color in 0.10 fixed or FP16 format</doc>
 <bitfield high="31" low="16" name="GREEN" />
-<doc>green constant color in 0.10 fixed or FP16
-format</doc></reg32>
-<reg32 access="rw" name="RB3D_FIFO_SIZE" offset="0x4EF4">Sets the
-fifo sizes
+<doc>green constant color in 0.10 fixed or FP16 format</doc>
+</reg32>
+<reg32 access="rw" name="RB3D_FIFO_SIZE" offset="0x4EF4">
+<doc>Sets the fifo sizes</doc>
 <bitfield high="1" low="0" name="OP_FIFO_SIZE">
 <use-enum ref="ENUM216" />
 </bitfield>
-<doc>Determines the size of the op fifo</doc></reg32>
-<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4">Alpha
-Function
+<doc>Determines the size of the op fifo</doc>
+</reg32>
+<reg32 access="rw" name="FG_ALPHA_FUNC" offset="0x4BD4">
+<doc>Alpha Function</doc>
 <bitfield high="7" low="0" name="AF_VAL" />
 <doc>Specifies the 8-bit alpha compare value when AF_EN_8BIT is
 enabled</doc>
@@ -6463,32 +6690,36 @@ value="1">
 <doc>Enable FP16 alpha compare and alpha-to-mask function</doc>
 </value>
 </bitfield>
-<doc>Enables/Disables FP16 alpha function</doc></reg32>
-<reg32 access="rw" name="FG_ALPHA_VALUE" offset="0x4BE0">Alpha
-Compare Value
+<doc>Enables/Disables FP16 alpha function</doc>
+</reg32>
+<reg32 access="rw" name="FG_ALPHA_VALUE" offset="0x4BE0">
+<doc>Alpha Compare Value</doc>
 <bitfield high="15" low="0" name="AF_VAL" />
 <doc>Specifies the alpha compare value, 0.10 fixed or FP16
-format</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0">Blue
-Component of Fog Color
+format</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_B" offset="0x4BD0">
+<doc>Blue Component of Fog Color</doc>
 <bitfield high="9" low="0" name="BLUE" />
-<doc>Blue component of fog color; (0.10) fixed
-format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC">Green
-Component of Fog Color
+<doc>Blue component of fog color; (0.10) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_G" offset="0x4BCC">
+<doc>Green Component of Fog Color</doc>
 <bitfield high="9" low="0" name="GREEN" />
-<doc>Green component of fog color; (0.10) fixed
-format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8">Red
-Component of Fog Color
+<doc>Green component of fog color; (0.10) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_COLOR_R" offset="0x4BC8">
+<doc>Red Component of Fog Color</doc>
 <bitfield high="9" low="0" name="RED" />
-<doc>Red component of fog color; (0.10) fixed format.</doc></reg32>
-<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4">Constant
-Factor for Fog Blending
+<doc>Red component of fog color; (0.10) fixed format.</doc>
+</reg32>
+<reg32 access="rw" name="FG_FOG_FACTOR" offset="0x4BC4">
+<doc>Constant Factor for Fog Blending</doc>
 <bitfield high="9" low="0" name="FACTOR" />
-<doc>Constant fog factor; fixed (0.10) format.</doc></reg32>
+<doc>Constant fog factor; fixed (0.10) format.</doc>
+</reg32>
 <reg32 access="rw" name="GA_COLOR_CONTROL_PS3" offset="0x4258">
-Specifies color properties and mappings of textures.
+<doc>Specifies color properties and mappings of textures.</doc>
 <bitfield high="1" low="0" name="TEX0_SHADING_PS3">
 <use-enum ref="ENUM30" />
 </bitfield>
@@ -6553,9 +6784,10 @@ one.</doc>
 <use-enum ref="ENUM221" />
 </bitfield>
 <doc>Specifies if each color should come from a texture and which
-one.</doc></reg32>
-<reg32 access="rw" name="GA_ENHANCE" offset="0x4274">GA Enhancement
-Register
+one.</doc>
+</reg32>
+<reg32 access="rw" name="GA_ENHANCE" offset="0x4274">
+<doc>GA Enhancement Register</doc>
 <bitfield high="0" low="0" name="DEADLOCK_CNTL">
 <use-enum ref="ENUM32" />
 </bitfield>
@@ -6585,9 +6817,10 @@ writes</doc>
 back.</doc>
 </value>
 </bitfield>
-<doc /></reg32>
-<reg32 access="rw" name="GA_FIFO_CNTL" offset="0x4270">GA Input
-fifo high water marks
+<doc />
+</reg32>
+<reg32 access="rw" name="GA_FIFO_CNTL" offset="0x4270">
+<doc>GA Input fifo high water marks</doc>
 <bitfield high="2" low="0" name="VERTEX_FIFO" />
 <doc>Number of words remaining in input vertex fifo before
 asserting nearly full</doc>
@@ -6596,18 +6829,23 @@ asserting nearly full</doc>
 asserting nearly full</doc>
 <bitfield high="13" low="6" name="REG_FIFO" />
 <doc>Number of words remaining in input register fifo before
-asserting nearly full</doc></reg32>
-<reg32 access="rw" name="GA_FILL_A" offset="0x422C">Alpha fill
-color</reg32>
-<reg32 access="rw" name="GA_FILL_B" offset="0x4228">Blue fill
-color</reg32>
-<reg32 access="rw" name="GA_FILL_G" offset="0x4224">Green fill
-color</reg32>
-<reg32 access="rw" name="GA_FILL_R" offset="0x4220">Red fill
-color</reg32>
-<reg32 access="rw" name="GA_IDLE" offset="0x425C">Returns idle
-status of various G3D block, captured when GA_IDLE written or when
-hard or soft reset asserted.
+asserting nearly full</doc>
+</reg32>
+<reg32 access="rw" name="GA_FILL_A" offset="0x422C">
+<doc>Alpha fill color</doc>
+</reg32>
+<reg32 access="rw" name="GA_FILL_B" offset="0x4228">
+<doc>Blue fill color</doc>
+</reg32>
+<reg32 access="rw" name="GA_FILL_G" offset="0x4224">
+<doc>Green fill color</doc>
+</reg32>
+<reg32 access="rw" name="GA_FILL_R" offset="0x4220">
+<doc>Red fill color</doc>
+</reg32>
+<reg32 access="rw" name="GA_IDLE" offset="0x425C">
+<doc>Returns idle status of various G3D block, captured when
+GA_IDLE written or when hard or soft reset asserted.</doc>
 <bitfield high="0" low="0" name="PIPE3_Z_IDLE" />
 <doc>Idle status of physical pipe 3 Z unit</doc>
 <bitfield high="1" low="1" name="PIPE2_Z_IDLE" />
@@ -6661,8 +6899,10 @@ hard or soft reset asserted.
 <bitfield high="25" low="25" name="GA_IDLE" />
 <doc>Idle status of GA unit</doc>
 <bitfield high="26" low="26" name="GA_UNIT2_IDLE" />
-<doc>Idle status of GA unit2</doc></reg32>
-<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234">Line control
+<doc>Idle status of GA unit2</doc>
+</reg32>
+<reg32 access="rw" name="GA_LINE_CNTL" offset="0x4234">
+<doc>Line control</doc>
 <bitfield high="15" low="0" name="WIDTH" />
 <doc>1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b
 subprecision); (16.0) fixed format.</doc>
@@ -6679,25 +6919,30 @@ subprecision); (16.0) fixed format.</doc>
 </value>
 </bitfield>
 <doc>R520+: When enabled, all lines are sorted so that V0 is vertex
-with smallest X, or if X equal, smallest Y.</doc></reg32>
-<reg32 access="rw" name="GA_OFFSET" offset="0x4290">Specifies x
-&amp; y offsets for vertex data after conversion to FP.
+with smallest X, or if X equal, smallest Y.</doc>
+</reg32>
+<reg32 access="rw" name="GA_OFFSET" offset="0x4290">
+<doc>Specifies x &amp; y offsets for vertex data after conversion
+to FP.</doc>
 <bitfield high="15" low="0" name="X_OFFSET" />
 <doc>Specifies X offset in S15 format (subpixels -- 1/12 or 1/16,
 even in 8b subprecision).</doc>
 <bitfield high="31" low="16" name="Y_OFFSET" />
 <doc>Specifies Y offset in S15 format (subpixels -- 1/12 or 1/16,
-even in 8b subprecision).</doc></reg32>
-<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C">Dimensions
-for Points
+even in 8b subprecision).</doc>
+</reg32>
+<reg32 access="rw" name="GA_POINT_SIZE" offset="0x421C">
+<doc>Dimensions for Points</doc>
 <bitfield high="15" low="0" name="HEIGHT" />
 <doc>1/2 Height of point; fixed (16.0), subpixel format (1/12 or
 1/16, even if in 8b precision).</doc>
 <bitfield high="31" low="16" name="WIDTH" />
 <doc>1/2 Width of point; fixed (16.0), subpixel format (1/12 or
-1/16, even if in 8b precision)</doc></reg32>
-<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C">Specifies
-the rouding mode for geometry &amp; color SPFP to FP conversions.
+1/16, even if in 8b precision)</doc>
+</reg32>
+<reg32 access="rw" name="GA_ROUND_MODE" offset="0x428C">
+<doc>Specifies the rouding mode for geometry &amp; color SPFP to FP
+conversions.</doc>
 <bitfield high="1" low="0" name="GEOMETRY_ROUND">
 <use-enum ref="ENUM38" />
 </bitfield>
@@ -6728,25 +6973,29 @@ RGB.</doc>
 <doc>Specifies SPFP alpha clamp range of [0,1] or FP20.</doc>
 <bitfield high="9" low="6" name="GEOMETRY_MASK" />
 <doc>4b negative polarity mask for subpixel precision. Inverted
-version gets ANDed with subpixel X, Y masks.</doc></reg32>
-<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280">Specifies
-blue &amp; alpha components of fill color -- S312 format --
-Backwards comp.
+version gets ANDed with subpixel X, Y masks.</doc>
+</reg32>
+<reg32 access="rw" name="GA_SOLID_BA" offset="0x4280">
+<doc>Specifies blue &amp; alpha components of fill color -- S312
+format -- Backwards comp.</doc>
 <bitfield high="15" low="0" name="COLOR_ALPHA" />
 <doc>Component alpha value. (S3.12)</doc>
 <bitfield high="31" low="16" name="COLOR_BLUE" />
-<doc>Component blue value. (S3.12)</doc></reg32>
-<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C">Specifies red
-&amp; green components of fill color -- S312 format -- Backwards
-comp.
+<doc>Component blue value. (S3.12)</doc>
+</reg32>
+<reg32 access="rw" name="GA_SOLID_RG" offset="0x427C">
+<doc>Specifies red &amp; green components of fill color -- S312
+format -- Backwards comp.</doc>
 <bitfield high="15" low="0" name="COLOR_GREEN" />
 <doc>Component green value (S3.12).</doc>
 <bitfield high="31" low="16" name="COLOR_RED" />
-<doc>Component red value (S3.12).</doc></reg32>
-<reg32 access="rw" name="GA_US_VECTOR_DATA" offset="0x4254">Data
-register for loading US instructions and constants</reg32>
-<reg32 access="rw" name="GA_US_VECTOR_INDEX" offset="0x4250">Used
-to load US instructions and constants
+<doc>Component red value (S3.12).</doc>
+</reg32>
+<reg32 access="rw" name="GA_US_VECTOR_DATA" offset="0x4254">
+<doc>Data register for loading US instructions and constants</doc>
+</reg32>
+<reg32 access="rw" name="GA_US_VECTOR_INDEX" offset="0x4250">
+<doc>Used to load US instructions and constants</doc>
 <bitfield high="8" low="0" name="INDEX" />
 <doc>Instruction (TYPE == GA_US_VECTOR_INST) or constant (TYPE ==
 GA_US_VECTOR_CONST) number at which to start loading. The GA will
@@ -6775,9 +7024,10 @@ constants.</doc>
 <doc>Clamp to [-1.0,1.0] constant data</doc>
 </value>
 </bitfield>
-<doc /></reg32>
-<reg32 access="rw" name="GB_ENABLE" offset="0x4008">Specifies top
-of Raster pipe specific enable controls.
+<doc />
+</reg32>
+<reg32 access="rw" name="GB_ENABLE" offset="0x4008">
+<doc>Specifies top of Raster pipe specific enable controls.</doc>
 <bitfield high="0" low="0" name="POINT_STUFF_ENABLE">
 <use-enum ref="ENUM43" />
 </bitfield>
@@ -6837,10 +7087,11 @@ texture.</doc>
 <use-enum ref="ENUM229" />
 </bitfield>
 <doc>Specifies the sources of the texture coordinates for each
-texture.</doc></reg32>
-<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024">Specifies
-the sizes of the various FIFO`s in the sc/rs/us. This register must
-be the first one written
+texture.</doc>
+</reg32>
+<reg32 access="rw" name="GB_FIFO_SIZE" offset="0x4024">
+<doc>Specifies the sizes of the various FIFO`s in the sc/rs/us.
+This register must be the first one written</doc>
 <bitfield high="1" low="0" name="SC_IFIFO_SIZE">
 <use-enum ref="ENUM55" />
 </bitfield>
@@ -6882,9 +7133,10 @@ be the first one written
 </bitfield>
 <doc>High water mark for US output fifo</doc>
 <bitfield high="28" low="24" name="US_CUBE_FIFO_HIGHWATER" />
-<doc>High water mark for US cube map fifo</doc></reg32>
-<reg32 access="rw" name="GB_FIFO_SIZE1" offset="0x4070">Specifies
-the sizes of the various FIFO`s in the sc/rs.
+<doc>High water mark for US cube map fifo</doc>
+</reg32>
+<reg32 access="rw" name="GB_FIFO_SIZE1" offset="0x4070">
+<doc>Specifies the sizes of the various FIFO`s in the sc/rs.</doc>
 <bitfield high="5" low="0" name="SC_HIGHWATER_IFIFO" />
 <doc>High water mark for SC input fifo</doc>
 <bitfield high="11" low="6" name="SC_HIGHWATER_BFIFO" />
@@ -6892,9 +7144,10 @@ the sizes of the various FIFO`s in the sc/rs.
 <bitfield high="17" low="12" name="RS_HIGHWATER_COL" />
 <doc>High water mark for RS colors` fifo</doc>
 <bitfield high="23" low="18" name="RS_HIGHWATER_TEX" />
-<doc>High water mark for RS textures` fifo</doc></reg32>
-<reg32 access="rw" name="GB_MSPOS0" offset="0x4010">Specifies the
-position of multisamples 0 through 2
+<doc>High water mark for RS textures` fifo</doc>
+</reg32>
+<reg32 access="rw" name="GB_MSPOS0" offset="0x4010">
+<doc>Specifies the position of multisamples 0 through 2</doc>
 <bitfield high="3" low="0" name="MS_X0" />
 <doc>Specifies the x and y position (in subpixels) of multisample
 0</doc>
@@ -6920,9 +7173,10 @@ first (coarse) scan converter</doc>
 <bitfield high="31" low="28" name="MSBD0_X" />
 <doc>Specifies the minimum x and y distance (in subpixels) between
 the pixel edge and the multisamples. These values are used in the
-first (coarse) scan converter</doc></reg32>
-<reg32 access="rw" name="GB_MSPOS1" offset="0x4014">Specifies the
-position of multisamples 3 through 5
+first (coarse) scan converter</doc>
+</reg32>
+<reg32 access="rw" name="GB_MSPOS1" offset="0x4014">
+<doc>Specifies the position of multisamples 3 through 5</doc>
 <bitfield high="3" low="0" name="MS_X3" />
 <doc>Specifies the x and y position (in subpixels) of multisample
 3</doc>
@@ -6944,9 +7198,10 @@ position of multisamples 3 through 5
 <bitfield high="27" low="24" name="MSBD1" />
 <doc>Specifies the minimum distance (in subpixels) between the
 pixel edge and the multisamples. This value is used in the second
-(quad) scan converter</doc></reg32>
-<reg32 access="rw" name="GB_PIPE_SELECT" offset="0x402C">Selects
-which of 4 pipes are active.
+(quad) scan converter</doc>
+</reg32>
+<reg32 access="rw" name="GB_PIPE_SELECT" offset="0x402C">
+<doc>Selects which of 4 pipes are active.</doc>
 <bitfield high="1" low="0" name="PIPE0_ID" />
 <doc>Maps physical pipe 0 to logical pipe ID (def 0).</doc>
 <bitfield high="3" low="2" name="PIPE1_ID" />
@@ -7011,9 +7266,11 @@ B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only</doc>
 <doc>If this bit is set when writing this register, the logical
 pipe ID values are assigned automatically based on the values that
 are read back in the MAX_PIPE and BAD_PIPES fields. This field is
-always read back as 0.</doc></reg32>
-<reg32 access="rw" name="GB_SELECT" offset="0x401C">Specifies
-various polygon specific selects (fog, depth, perspective).
+always read back as 0.</doc>
+</reg32>
+<reg32 access="rw" name="GB_SELECT" offset="0x401C">
+<doc>Specifies various polygon specific selects (fog, depth,
+perspective).</doc>
 <bitfield high="2" low="0" name="FOG_SELECT">
 <use-enum ref="ENUM59" />
 </bitfield>
@@ -7041,10 +7298,11 @@ coordinate.</doc>
 <bitfield high="9" low="6" name="FOG_STUFF_TEX" />
 <doc>Controls which texture gets fog value</doc>
 <bitfield high="11" low="10" name="FOG_STUFF_COMP" />
-<doc>Controls which component of texture gets fog
-value</doc></reg32>
-<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018">Specifies
-the graphics pipeline configuration for rasterization
+<doc>Controls which component of texture gets fog value</doc>
+</reg32>
+<reg32 access="rw" name="GB_TILE_CONFIG" offset="0x4018">
+<doc>Specifies the graphics pipeline configuration for
+rasterization</doc>
 <bitfield high="0" low="0" name="ENABLE">
 <use-enum ref="ENUM62" />
 </bitfield>
@@ -7164,9 +7422,10 @@ pixel [1.0,0.0]</doc>
 </value>
 </bitfield>
 <doc>Support for extended setup Z range from [0,1] to [-2,2] with
-per pixel clamping</doc></reg32>
-<reg32 access="rw" name="GB_Z_PEQ_CONFIG" offset="0x4028">Specifies
-the z plane equation configuration.
+per pixel clamping</doc>
+</reg32>
+<reg32 access="rw" name="GB_Z_PEQ_CONFIG" offset="0x4028">
+<doc>Specifies the z plane equation configuration.</doc>
 <bitfield high="0" low="0" name="Z_PEQ_SIZE">
 <value name="4X4_Z_PLANE_EQUATIONS" value="0">
 <doc>4x4 z plane equations (point-sampled or aa)</doc>
@@ -7175,9 +7434,11 @@ the z plane equation configuration.
 <doc>8x8 z plane equations (point-sampled only)</doc>
 </value>
 </bitfield>
-<doc>Specifies the z plane equation size.</doc></reg32>
-<reg32 access="rw" name="RS_COUNT" offset="0x4300">This register
-specifies the rasterizer input packet configuration
+<doc>Specifies the z plane equation size.</doc>
+</reg32>
+<reg32 access="rw" name="RS_COUNT" offset="0x4300">
+<doc>This register specifies the rasterizer input packet
+configuration</doc>
 <bitfield high="6" low="0" name="IT_COUNT" />
 <doc>Specifies the total number of texture address components
 contained in the rasterizer input packet (0:32).</doc>
@@ -7189,10 +7450,12 @@ rasterizer input packet (0:4).</doc>
 (if w_count==1)</doc>
 <bitfield high="18" low="18" name="HIRES_EN" />
 <doc>Enable high resolution texture coordinate output when q is
-equal to 1</doc></reg32>
-<stripe addr="0x4320" length="16" stride="0x0004">
-<reg32 access="rw" name="RS_INST" offset="0x0">This table specifies
-what happens during each rasterizer instruction
+equal to 1</doc>
+</reg32>
+<stripe length="16" offset="0x4320" stride="0x0004">
+<reg32 access="rw" name="RS_INST" offset="0x0">
+<doc>This table specifies what happens during each rasterizer
+instruction</doc>
 <bitfield high="3" low="0" name="TEX_ID" />
 <doc>Specifies the index (into the RS_IP table) of the texture
 address output during this rasterizer instruction</doc>
@@ -7239,19 +7502,22 @@ adjusted pixel centers</doc>
 <doc>write - w valid</doc>
 </value>
 </bitfield>
-<doc>Specifies that the rasterizer should output w</doc></reg32>
+<doc>Specifies that the rasterizer should output w</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304">This
-register specifies the number of rasterizer instructions
+<reg32 access="rw" name="RS_INST_COUNT" offset="0x4304">
+<doc>This register specifies the number of rasterizer
+instructions</doc>
 <bitfield high="3" low="0" name="INST_COUNT" />
 <doc>Number of rasterizer instructions (1:16)</doc>
 <bitfield high="7" low="5" name="TX_OFFSET" />
 <doc>Indicates range of texture offset to minimize peroidic errors
-on texels sampled right on their edges</doc></reg32>
-<stripe addr="0x4074" length="16" stride="0x0004">
-<reg32 access="rw" name="RS_IP" offset="0x0">This table specifies
-the source location and format for up to 16 texture addresses
-(i[0]:i[15]) and four colors (c[0]:c[3])
+on texels sampled right on their edges</doc>
+</reg32>
+<stripe length="16" offset="0x4074" stride="0x0004">
+<reg32 access="rw" name="RS_IP" offset="0x0">
+<doc>This table specifies the source location and format for up to
+16 texture addresses (i[0]:i[15]) and four colors (c[0]:c[3])</doc>
 <bitfield high="5" low="0" name="TEX_PTR_S" />
 <doc>Specifies the relative rasterizer input packet location of
 each component (S, T, R, and Q) of texture address (i[i]). The
@@ -7289,11 +7555,12 @@ value="1">
 <doc>Apply the TX_OFFSET specified by RS_INST_COUNT</doc>
 </value>
 </bitfield>
-<doc>Enable application of the TX_OFFSET in
-RS_INST_COUNT</doc></reg32>
+<doc>Enable application of the TX_OFFSET in RS_INST_COUNT</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8">Edge rules -
-what happens when an edge falls exactly on a sample point
+<reg32 access="rw" name="SC_EDGERULE" offset="0x43A8">
+<doc>Edge rules - what happens when an edge falls exactly on a
+sample point</doc>
 <bitfield high="4" low="0" name="ER_TRI">
 <use-enum ref="ENUM74" />
 </bitfield>
@@ -7371,9 +7638,10 @@ specifies whether a sample on a left edge is in. For values 16 to
 31, bit 0 specifies whether a sample on a vertical-right edge is
 in, bit 1 specifies whether a sample on a vertical-left edge is in,
 bit 2 species whether a sample on a bottom edge is in, bit 3
-specifies whether a sample on a top edge is in</doc></reg32>
-<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8">SU Raster
-pipe destination select for registers
+specifies whether a sample on a top edge is in</doc>
+</reg32>
+<reg32 access="rw" name="SU_REG_DEST" offset="0x42C8">
+<doc>SU Raster pipe destination select for registers</doc>
 <bitfield high="3" low="0" name="SELECT">
 <value name="LOGICAL_PIPE0" value="0">
 <doc>logical pipe0, b</doc>
@@ -7389,10 +7657,10 @@ pipe destination select for registers
 </value>
 </bitfield>
 <doc>Register read/write destination select: b0: logical pipe0, b1:
-logical pipe1, b2: logical pipe2 and b3: logical
-pipe3</doc></reg32>
-<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0">Enables for
-Cylindrical Wrapping
+logical pipe1, b2: logical pipe2 and b3: logical pipe3</doc>
+</reg32>
+<reg32 access="rw" name="SU_TEX_WRAP" offset="0x42A0">
+<doc>Enables for Cylindrical Wrapping</doc>
 <bitfield high="0" low="0" name="T0C0">
 <use-enum ref="ENUM247" />
 </bitfield>
@@ -7552,9 +7820,10 @@ texture N.</doc>
 <use-enum ref="ENUM247" />
 </bitfield>
 <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of
-texture N.</doc></reg32>
-<reg32 access="rw" name="SU_TEX_WRAP_PS3" offset="0x4114">Specifies
-texture wrapping for new PS3 textures.
+texture N.</doc>
+</reg32>
+<reg32 access="rw" name="SU_TEX_WRAP_PS3" offset="0x4114">
+<doc>Specifies texture wrapping for new PS3 textures.</doc>
 <bitfield high="0" low="0" name="T9C0">
 <use-enum ref="ENUM247" />
 </bitfield>
@@ -7594,17 +7863,20 @@ texture N.</doc>
 <use-enum ref="ENUM247" />
 </bitfield>
 <doc>tNcM -- Enable texture wrapping on component M (S,T,R,Q) of
-texture N.</doc></reg32>
-<stripe addr="0x45C0" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0">Border
-Color</reg32>
+texture N.</doc>
+</reg32>
+<stripe length="16" offset="0x45C0" stride="0x0004">
+<reg32 access="rw" name="TX_BORDER_COLOR" offset="0x0">
+<doc>Border Color</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4580" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0">Texture Chroma
-Key</reg32>
+<stripe length="16" offset="0x4580" stride="0x0004">
+<reg32 access="rw" name="TX_CHROMA_KEY" offset="0x0">
+<doc>Texture Chroma Key</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="TX_ENABLE" offset="0x4104">Texture Enables
-for Maps 0 to 15
+<reg32 access="rw" name="TX_ENABLE" offset="0x4104">
+<doc>Texture Enables for Maps 0 to 15</doc>
 <bitfield high="0" low="0" name="TEX_0_ENABLE">
 <use-enum ref="ENUM248" />
 </bitfield>
@@ -7668,10 +7940,11 @@ for Maps 0 to 15
 <bitfield high="15" low="15" name="TEX_15_ENABLE">
 <use-enum ref="ENUM248" />
 </bitfield>
-<doc>Texture Map Enables.</doc></reg32>
-<stripe addr="0x4400" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FILTER0" offset="0x0">Texture Filter
-State
+<doc>Texture Map Enables.</doc>
+</reg32>
+<stripe length="16" offset="0x4400" stride="0x0004">
+<reg32 access="rw" name="TX_FILTER0" offset="0x0">
+<doc>Texture Filter State</doc>
 <bitfield high="2" low="0" name="CLAMP_S">
 <use-enum ref="ENUM136" />
 </bitfield>
@@ -7704,11 +7977,12 @@ State
 <doc>LOD index of largest (finest) mipmap to use (0 is largest).
 Ranges from 0 to NUM_LEVELS.</doc>
 <bitfield high="31" low="28" name="ID" />
-<doc>Logical id for this physical texture</doc></reg32>
+<doc>Logical id for this physical texture</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4440" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FILTER1" offset="0x0">Texture Filter
-State
+<stripe length="16" offset="0x4440" stride="0x0004">
+<reg32 access="rw" name="TX_FILTER1" offset="0x0">
+<doc>Texture Filter State</doc>
 <bitfield high="1" low="0" name="CHROMA_KEY_MODE">
 <use-enum ref="ENUM140" />
 </bitfield>
@@ -7771,9 +8045,11 @@ value="1">
 </value>
 </bitfield>
 <doc>To fix issues when using non-square mipmaps, with
-border_color, and extreme minification.</doc></reg32>
+border_color, and extreme minification.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="TX_FILTER4" offset="0x4110">Filter4 Kernel
+<reg32 access="rw" name="TX_FILTER4" offset="0x4110">
+<doc>Filter4 Kernel</doc>
 <bitfield high="10" low="0" name="WEIGHT_1" />
 <doc>(s1.9). Bottom or Right weight of pair.</doc>
 <bitfield high="21" low="11" name="WEIGHT_0" />
@@ -7798,10 +8074,11 @@ border_color, and extreme minification.</doc></reg32>
 </value>
 </bitfield>
 <doc>Indicates whether to load the horizontal or vertical
-weights</doc></reg32>
-<stripe addr="0x4480" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT0" offset="0x0">Texture Format
-State
+weights</doc>
+</reg32>
+<stripe length="16" offset="0x4480" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT0" offset="0x0">
+<doc>Texture Format State</doc>
 <bitfield high="10" low="0" name="TXWIDTH" />
 <doc>Image width - 1. The largest image is 4096 texels. When
 wrapping or mirroring, must be a power of 2. When mipmapping, must
@@ -7825,11 +8102,12 @@ Equivalent to LOD index of smallest (coarsest) mipmap to use.</doc>
 <use-enum ref="ENUM144" />
 </bitfield>
 <doc>Indicates when TXPITCH should be used instead of TXWIDTH for
-image addressing</doc></reg32>
+image addressing</doc>
+</reg32>
 </stripe>
-<stripe addr="0x44C0" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT1" offset="0x0">Texture Format
-State
+<stripe length="16" offset="0x44C0" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT1" offset="0x0">
+<doc>Texture Format State</doc>
 <bitfield high="4" low="0" name="TXFORMAT">
 <value name="TX_FMT_8_OR_TX_FMT_1" value="0">
 <doc>TX_FMT_8 or TX_FMT_1 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc>
@@ -7986,11 +8264,12 @@ Only apply to 8bit or less components.</doc>
 <bitfield high="31" low="27" name="CACHE">
 <use-enum ref="ENUM158" />
 </bitfield>
-<doc>This field is ignored on R520 and RV510.</doc></reg32>
+<doc>This field is ignored on R520 and RV510.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4500" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_FORMAT2" offset="0x0">Texture Format
-State
+<stripe length="16" offset="0x4500" stride="0x0004">
+<reg32 access="rw" name="TX_FORMAT2" offset="0x0">
+<doc>Texture Format State</doc>
 <bitfield high="13" low="0" name="TXPITCH" />
 <doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN
 is asserted. Pitch is given as number of texels minus one. Maximum
@@ -8029,11 +8308,12 @@ only be asserted for 8-bit components.</doc>
 </value>
 </bitfield>
 <doc>If filter4 is enabled, specifies which texture component to
-apply filter4 to.</doc></reg32>
+apply filter4 to.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4540" length="16" stride="0x0004">
-<reg32 access="rw" name="TX_OFFSET" offset="0x0">Texture Offset
-State
+<stripe length="16" offset="0x4540" stride="0x0004">
+<reg32 access="rw" name="TX_OFFSET" offset="0x0">
+<doc>Texture Offset State</doc>
 <bitfield high="1" low="0" name="ENDIAN_SWAP">
 <use-enum ref="ENUM159" />
 </bitfield>
@@ -8047,11 +8327,12 @@ State
 </bitfield>
 <doc>Micro Tile Control</doc>
 <bitfield high="31" low="5" name="TXOFFSET" />
-<doc>32-byte aligned pointer to base map</doc></reg32>
+<doc>32-byte aligned pointer to base map</doc>
+</reg32>
 </stripe>
-<stripe addr="0xA800" length="512" stride="0x0004">
-<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0">ALU Alpha
-Instruction
+<stripe length="512" offset="0xA800" stride="0x0004">
+<reg32 access="rw" name="US_ALU_ALPHA_INST" offset="0x0">
+<doc>ALU Alpha Instruction</doc>
 <bitfield high="3" low="0" name="ALPHA_OP">
 <value name="OP_MAD" value="0">
 <doc>OP_MAD: Result = A*B + C</doc>
@@ -8162,14 +8443,16 @@ results against zero when setting the predicate bits.</doc>
 </value>
 </bitfield>
 <doc>Specifies whether or not to write the Alpha component of the
-result of this instuction to the depth output fifo.</doc></reg32>
+result of this instuction to the depth output fifo.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x9800" length="512" stride="0x0004">
-<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0">This table
-specifies the Alpha source addresses and pre-subtract operation for
-up to 512 ALU instruction. The ALU expects 6 source operands -
-three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1,
-a2). The pre-subtract operation creates two more (rgbp and ap).
+<stripe length="512" offset="0x9800" stride="0x0004">
+<reg32 access="rw" name="US_ALU_ALPHA_ADDR" offset="0x0">
+<doc>This table specifies the Alpha source addresses and
+pre-subtract operation for up to 512 ALU instruction. The ALU
+expects 6 source operands - three for color (rgb0, rgb1, rgb2) and
+three for alpha (a0, a1, a2). The pre-subtract operation creates
+two more (rgbp and ap).</doc>
 <bitfield high="7" low="0" name="ADDR0" />
 <doc>Specifies the identity of source operands a0, a1, and a2. If
 the const field is set, this number ranges from 0 to 255 and
@@ -8236,12 +8519,12 @@ addressing.</doc>
 <bitfield high="31" low="30" name="SRCP_OP">
 <use-enum ref="ENUM168" />
 </bitfield>
-<doc>Specifies how the pre-subtract value (SRCP) is
-computed.</doc></reg32>
+<doc>Specifies how the pre-subtract value (SRCP) is computed.</doc>
+</reg32>
 </stripe>
-<stripe addr="0xB000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_ALU_RGBA_INST" offset="0x0">ALU Shared
-RGBA Instruction
+<stripe length="512" offset="0xB000" stride="0x0004">
+<reg32 access="rw" name="US_ALU_RGBA_INST" offset="0x0">
+<doc>ALU Shared RGBA Instruction</doc>
 <bitfield high="3" low="0" name="RGB_OP">
 <value name="OP_MAD" value="0">
 <doc>OP_MAD: Result = A*B + C</doc>
@@ -8335,12 +8618,12 @@ C.</doc>
 <bitfield high="31" low="30" name="ALPHA_MOD_C">
 <use-enum ref="ENUM167" />
 </bitfield>
-<doc>Specifies the input modifiers for RGB and Alpha input
-C.</doc></reg32>
+<doc>Specifies the input modifiers for RGB and Alpha input C.</doc>
+</reg32>
 </stripe>
-<stripe addr="0xA000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0">ALU RGB
-Instruction
+<stripe length="512" offset="0xA000" stride="0x0004">
+<reg32 access="rw" name="US_ALU_RGB_INST" offset="0x0">
+<doc>ALU RGB Instruction</doc>
 <bitfield high="1" low="0" name="RGB_SEL_A">
 <use-enum ref="ENUM262" />
 </bitfield>
@@ -8407,15 +8690,16 @@ value="1">
 ALU_RESULT_SEL and ALU_RESULT_OP.</doc>
 </value>
 </bitfield>
-<doc>Specifies whether to update the current ALU
-result.</doc></reg32>
+<doc>Specifies whether to update the current ALU result.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x9000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0">This table
-specifies the RGB source addresses and pre-subtract operation for
-up to 512 ALU instructions. The ALU expects 6 source operands -
-three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1,
-a2). The pre-subtract operation creates two more (rgbp and ap).
+<stripe length="512" offset="0x9000" stride="0x0004">
+<reg32 access="rw" name="US_ALU_RGB_ADDR" offset="0x0">
+<doc>This table specifies the RGB source addresses and pre-subtract
+operation for up to 512 ALU instructions. The ALU expects 6 source
+operands - three for color (rgb0, rgb1, rgb2) and three for alpha
+(a0, a1, a2). The pre-subtract operation creates two more (rgbp and
+ap).</doc>
 <bitfield high="7" low="0" name="ADDR0" />
 <doc>Specifies the identity of source operands rgb0, rgb1, and
 rgb2. If the const field is set, this number ranges from 0 to 255
@@ -8482,12 +8766,12 @@ addressing.</doc>
 <bitfield high="31" low="30" name="SRCP_OP">
 <use-enum ref="ENUM174" />
 </bitfield>
-<doc>Specifies how the pre-subtract value (SRCP) is
-computed.</doc></reg32>
+<doc>Specifies how the pre-subtract value (SRCP) is computed.</doc>
+</reg32>
 </stripe>
-<stripe addr="0xB800" length="512" stride="0x0004">
-<reg32 access="rw" name="US_CMN_INST" offset="0x0">Shared
-instruction fields for all instruction types
+<stripe length="512" offset="0xB800" stride="0x0004">
+<reg32 access="rw" name="US_CMN_INST" offset="0x0">
+<doc>Shared instruction fields for all instruction types</doc>
 <bitfield high="1" low="0" name="TYPE">
 <value name="US_INST_TYPE_ALU" value="0">
 <doc>US_INST_TYPE_ALU: This instruction is an ALU
@@ -8704,10 +8988,11 @@ ALU/TEX/Output this specifies predication for the alpha channel
 only. This field has no effect on FC instructions.</doc>
 <bitfield high="31" low="28" name="STAT_WE" />
 <doc>Specifies which components (R,G,B,A) contribute to the stat
-count</doc></reg32>
+count</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_CODE_ADDR" offset="0x4630">Code start
-and end instruction addresses.
+<reg32 access="rw" name="US_CODE_ADDR" offset="0x4630">
+<doc>Code start and end instruction addresses.</doc>
 <bitfield high="8" low="0" name="START_ADDR" />
 <doc>Specifies the address of the first instruction to execute in
 the shader program. This address is relative to the shader program
@@ -8717,26 +9002,30 @@ offset given in US_CODE_OFFSET.OFFSET_ADDR.</doc>
 the shader program. This address is relative to the shader program
 offset given in US_CODE_OFFSET.OFFSET_ADDR. Shader program
 execution will always terminate after the instruction at this
-address is executed.</doc></reg32>
-<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4638">Offsets
-used for relative instruction addresses in the shader program,
-including START_ADDR, END_ADDR, and any non-global flow control
-jump addresses.
+address is executed.</doc>
+</reg32>
+<reg32 access="rw" name="US_CODE_OFFSET" offset="0x4638">
+<doc>Offsets used for relative instruction addresses in the shader
+program, including START_ADDR, END_ADDR, and any non-global flow
+control jump addresses.</doc>
 <bitfield high="8" low="0" name="OFFSET_ADDR" />
 <doc>Specifies the offset to add to relative instruction addresses,
 including START_ADDR, END_ADDR, and some flow control jump
-addresses.</doc></reg32>
-<reg32 access="rw" name="US_CODE_RANGE" offset="0x4634">Range of
-instructions that contains the current shader program.
+addresses.</doc>
+</reg32>
+<reg32 access="rw" name="US_CODE_RANGE" offset="0x4634">
+<doc>Range of instructions that contains the current shader
+program.</doc>
 <bitfield high="8" low="0" name="CODE_ADDR" />
 <doc>Specifies the start address of the current code window. This
 address is an absolute address.</doc>
 <bitfield high="24" low="16" name="CODE_SIZE" />
 <doc>Specifies the size of the current code window, minus one. The
 last instruction in the code window is given by CODE_ADDR +
-CODE_SIZE.</doc></reg32>
-<reg32 access="rw" name="US_CONFIG" offset="0x4600">Shader
-Configuration
+CODE_SIZE.</doc>
+</reg32>
+<reg32 access="rw" name="US_CONFIG" offset="0x4600">
+<doc>Shader Configuration</doc>
 <bitfield high="0" low="0" name="Reserved" />
 <doc>Set to 0</doc>
 <bitfield high="1" low="1" name="ZERO_TIMES_ANYTHING_EQUALS_ZERO">
@@ -8749,10 +9038,11 @@ Configuration
 </bitfield>
 <doc>Control how ALU multiplier behaves when one argument is zero.
 This affects the multiplier used in MAD and dot product
-calculations.</doc></reg32>
-<stripe addr="0xA000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_FC_ADDR" offset="0x0">Flow Control
-Instruction Address Fields
+calculations.</doc>
+</reg32>
+<stripe length="512" offset="0xA000" stride="0x0004">
+<reg32 access="rw" name="US_FC_ADDR" offset="0x0">
+<doc>Flow Control Instruction Address Fields</doc>
 <bitfield high="4" low="0" name="BOOL_ADDR" />
 <doc>The address of the static boolean register to use in the jump
 function.</doc>
@@ -8774,13 +9064,15 @@ destination address jump</doc>
 </value>
 </bitfield>
 <doc>Specifies whether to interpret JUMP_ADDR as a global
-address.</doc></reg32>
+address.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_FC_BOOL_CONST" offset="0x4620">Static
-Boolean Constants for Flow Control Branching Instructions.
-Quad-buffered.</reg32>
-<reg32 access="rw" name="US_FC_CTRL" offset="0x4624">Flow Control
-Options. Quad-buffered.
+<reg32 access="rw" name="US_FC_BOOL_CONST" offset="0x4620">
+<doc>Static Boolean Constants for Flow Control Branching
+Instructions. Quad-buffered.</doc>
+</reg32>
+<reg32 access="rw" name="US_FC_CTRL" offset="0x4624">
+<doc>Flow Control Options. Quad-buffered.</doc>
 <bitfield high="30" low="30" name="TEST_EN">
 <value name="NORMAL_MODE" value="0">
 <doc>Normal mode</doc>
@@ -8803,10 +9095,11 @@ subroutines.</doc>
 </value>
 </bitfield>
 <doc>Specifies whether full flow control functionality is
-enabled.</doc></reg32>
-<stripe addr="0x9800" length="512" stride="0x0004">
-<reg32 access="rw" name="US_FC_INST" offset="0x0">Flow Control
-Instruction
+enabled.</doc>
+</reg32>
+<stripe length="512" offset="0x9800" stride="0x0004">
+<reg32 access="rw" name="US_FC_INST" offset="0x0">
+<doc>Flow Control Instruction</doc>
 <bitfield high="2" low="0" name="OP">
 <value name="US_FC_OP_JUMP" value="0">
 <doc>US_FC_OP_JUMP: (if, endif, call, etc)</doc>
@@ -8943,11 +9236,13 @@ value="1">
 </value>
 </bitfield>
 <doc>If set, uncovered pixels will not participate in flow control
-decisions.</doc></reg32>
+decisions.</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4C00" length="32" stride="0x0004">
-<reg32 access="rw" name="US_FC_INT_CONST" offset="0x0">Integer
-Constants used by Flow Control Loop Instructions. Single buffered.
+<stripe length="32" offset="0x4C00" stride="0x0004">
+<reg32 access="rw" name="US_FC_INT_CONST" offset="0x0">
+<doc>Integer Constants used by Flow Control Loop Instructions.
+Single buffered.</doc>
 <bitfield high="7" low="0" name="KR" />
 <doc>Specifies the number of iterations. Unsigned 8-bit integer in
 [0, 255].</doc>
@@ -8956,10 +9251,10 @@ Constants used by Flow Control Loop Instructions. Single buffered.
 Unsigned 8-bit integer in [0, 255].</doc>
 <bitfield high="23" low="16" name="KB" />
 <doc>Specifies the increment used to change the loop register (aL)
-on each iteration. Signed 7-bit integer in [-128,
-127].</doc></reg32>
+on each iteration. Signed 7-bit integer in [-128, 127].</doc>
+</reg32>
 </stripe>
-<stripe addr="0x4640" length="16" stride="0x0004">
+<stripe length="16" offset="0x4640" stride="0x0004">
 <reg32 access="rw" name="US_FORMAT0" offset="0x0">
 <bitfield high="25" low="22" name="TXDEPTH">
 <value name="WIDTH" value="13">
@@ -8975,7 +9270,7 @@ on each iteration. Signed 7-bit integer in [-128,
 <doc />
 </reg32>
 </stripe>
-<stripe addr="0x46A4" length="4" stride="0x0004">
+<stripe length="4" offset="0x46A4" stride="0x0004">
 <reg32 access="rw" name="US_OUT_FMT" offset="0x0">
 <bitfield high="4" low="0" name="OUT_FMT">
 <use-enum ref="ENUM179" />
@@ -9008,15 +9303,16 @@ on each iteration. Signed 7-bit integer in [-128,
 <doc />
 </reg32>
 </stripe>
-<reg32 access="rw" name="US_PIXSIZE" offset="0x4604">Shader pixel
-size. This register specifies the size and partitioning of the
-current pixel stack frame
+<reg32 access="rw" name="US_PIXSIZE" offset="0x4604">
+<doc>Shader pixel size. This register specifies the size and
+partitioning of the current pixel stack frame</doc>
 <bitfield high="6" low="0" name="PIX_SIZE" />
 <doc>Specifies the total size of the current pixel stack frame
-(1:128)</doc></reg32>
-<stripe addr="0x9800" length="512" stride="0x0004">
-<reg32 access="rw" name="US_TEX_ADDR" offset="0x0">Texture
-addresses and swizzles
+(1:128)</doc>
+</reg32>
+<stripe length="512" offset="0x9800" stride="0x0004">
+<reg32 access="rw" name="US_TEX_ADDR" offset="0x0">
+<doc>Texture addresses and swizzles</doc>
 <bitfield high="6" low="0" name="SRC_ADDR" />
 <doc>Specifies the location (within the shader pixel stack frame)
 of the texture address for this instruction</doc>
@@ -9123,11 +9419,13 @@ write to the blue channel of dst_addr</doc>
 </value>
 </bitfield>
 <doc>Specify which colour channel of the returned texture data to
-write to the alpha channel of dst_addr</doc></reg32>
+write to the alpha channel of dst_addr</doc>
+</reg32>
 </stripe>
-<stripe addr="0xA000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_TEX_ADDR_DXDY" offset="0x0">Additional
-texture addresses and swizzles for DX/DY inputs
+<stripe length="512" offset="0xA000" stride="0x0004">
+<reg32 access="rw" name="US_TEX_ADDR_DXDY" offset="0x0">
+<doc>Additional texture addresses and swizzles for DX/DY
+inputs</doc>
 <bitfield high="6" low="0" name="DX_ADDR" />
 <doc>Specifies the location (within the shader pixel stack frame)
 of the DX value for this instruction</doc>
@@ -9185,11 +9483,12 @@ coordinate</doc>
 <use-enum ref="ENUM302" />
 </bitfield>
 <doc>Specify which colour channel of dy_addr to use for Q
-coordinate</doc></reg32>
+coordinate</doc>
+</reg32>
 </stripe>
-<stripe addr="0x9000" length="512" stride="0x0004">
-<reg32 access="rw" name="US_TEX_INST" offset="0x0">Texture
-Instruction
+<stripe length="512" offset="0x9000" stride="0x0004">
+<reg32 access="rw" name="US_TEX_INST" offset="0x0">
+<doc>Texture Instruction</doc>
 <bitfield high="19" low="16" name="TEX_ID" />
 <doc>Specifies the id of the texture map used for this
 instruction</doc>
@@ -9251,10 +9550,12 @@ dimensions of the target texture</doc>
 </value>
 </bitfield>
 <doc>Whether to scale texture coordinates when sending them to the
-texture unit.</doc></reg32>
+texture unit.</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="US_W_FMT" offset="0x46B4">Specifies the
-source and format for the Depth (W) value output by the shader
+<reg32 access="rw" name="US_W_FMT" offset="0x46B4">
+<doc>Specifies the source and format for the Depth (W) value output
+by the shader</doc>
 <bitfield high="1" low="0" name="W_FMT">
 <value name="W" value="0">
 <doc>W</doc>
@@ -9279,15 +9580,17 @@ additional logic in other blocks.</doc>
 <bitfield high="2" low="2" name="W_SRC">
 <use-enum ref="ENUM183" />
 </bitfield>
-<doc>Source for W</doc></reg32>
+<doc>Source for W</doc>
+</reg32>
 <reg32 access="rw" name="VAP_ALT_NUM_VERTICES" offset="0x2088">
-Alternate Number of Vertices to allow &gt; 16-bits of Vertex count
+<doc>Alternate Number of Vertices to allow &gt; 16-bits of Vertex
+count</doc>
 <bitfield high="23" low="0" name="NUM_VERTICES" />
 <doc>24-bit vertex count for command packet. Used instead of bits
-31:16 of VAP_VF_CNTL if VAP_VF_CNTL.USE_ALT_NUM_VERTS is
-set.</doc></reg32>
-<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C">Control
-Bits for User Clip Planes and Clipping
+31:16 of VAP_VF_CNTL if VAP_VF_CNTL.USE_ALT_NUM_VERTS is set.</doc>
+</reg32>
+<reg32 access="rw" name="VAP_CLIP_CNTL" offset="0x221C">
+<doc>Control Bits for User Clip Planes and Clipping</doc>
 <bitfield high="0" low="0" name="UCP_ENA_0" />
 <doc>Enable User Clip Plane 0</doc>
 <bitfield high="1" low="1" name="UCP_ENA_1" />
@@ -9318,9 +9621,10 @@ highlighted</doc>
 requirement)</doc>
 <bitfield high="21" low="21" name="COLOR3_IS_TEXTURE" />
 <doc>If set, color3 is used as texture9 by GA (PS3.0
-requirement)</doc></reg32>
-<reg32 access="rw" name="VAP_CNTL" offset="0x2080">Vertex
-Assembler/Processor Control Register
+requirement)</doc>
+</reg32>
+<reg32 access="rw" name="VAP_CNTL" offset="0x2080">
+<doc>Vertex Assembler/Processor Control Register</doc>
 <bitfield high="3" low="0" name="PVS_NUM_SLOTS" />
 <doc>Specifies the number of vertex slots to be used in the VAP PVS
 process. A slot represents a single vertex storage location1 across
@@ -9355,9 +9659,10 @@ used which is one less than the number of vertices (i.e. a 12 means
 <bitfield high="23" low="23" name="TCL_STATE_OPTIMIZATION" />
 <doc>If set, enables the TCL state optimization, and the new state
 is used only if there is a change in TCL state, between VF_CNTL
-(triggers)</doc></reg32>
-<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140">Vertex
-Assemblen/Processor Control Status
+(triggers)</doc>
+</reg32>
+<reg32 access="rw" name="VAP_CNTL_STATUS" offset="0x2140">
+<doc>Vertex Assemblen/Processor Control Status</doc>
 <bitfield high="1" low="0" name="VC_SWAP" />
 <doc>Endian-Swap Control. 0 = No swap 1 = 16-bit swap: 0xAABBCCDD
 becomes 0xBBAADDCC 2 = 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA 3
@@ -9397,15 +9702,17 @@ MPs is not available</doc>
 <bitfield high="30" low="30" name="REGPIPE_BUSY" />
 <doc>Register Pipeline is Busy. Read-only.</doc>
 <bitfield high="31" low="31" name="VAP_BUSY" />
-<doc>VAP Engine is Busy. Read-only.</doc></reg32>
-<reg32 access="rw" name="VAP_INDEX_OFFSET" offset="0x208C">Offset
-Value added to index value in both Indexed and Auto-indexed modes.
-Disabled by setting to 0
+<doc>VAP Engine is Busy. Read-only.</doc>
+</reg32>
+<reg32 access="rw" name="VAP_INDEX_OFFSET" offset="0x208C">
+<doc>Offset Value added to index value in both Indexed and
+Auto-indexed modes. Disabled by setting to 0</doc>
 <bitfield high="24" low="0" name="INDEX_OFFSET" />
-<doc>25-bit signed 2`s comp offset value</doc></reg32>
-<stripe addr="0x2150" length="8" stride="0x0004">
+<doc>25-bit signed 2`s comp offset value</doc>
+</reg32>
+<stripe length="8" offset="0x2150" stride="0x0004">
 <reg32 access="rw" name="VAP_PROG_STREAM_CNTL" offset="0x0">
-Programmable Stream Control Word 0
+<doc>Programmable Stream Control Word 0</doc>
 <bitfield high="3" low="0" name="DATA_TYPE_0" />
 <doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1
 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4
@@ -9467,13 +9774,14 @@ VAP_PSC_SGN_NORM_CNTL description for details.</doc>
 <bitfield high="30" low="30" name="SIGNED_1" />
 <doc>See SIGNED_0</doc>
 <bitfield high="31" low="31" name="NORMALIZE_1" />
-<doc>See NORMALIZE_0</doc></reg32>
+<doc>See NORMALIZE_0</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2500" length="16" stride="0x0008">
+<stripe length="16" offset="0x2500" stride="0x0008">
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_LW" offset="0x0">
-For VS3.0 - To support more PVS instructions, increase the address
-range - Programmable Vertex Shader Flow Control Lower Word
-Addresses Register 0
+<doc>For VS3.0 - To support more PVS instructions, increase the
+address range - Programmable Vertex Shader Flow Control Lower Word
+Addresses Register 0</doc>
 <bitfield high="15" low="0" name="PVS_FC_ACT_ADRS_0">
 <use-enum ref="ENUM313" />
 </bitfield>
@@ -9490,13 +9798,14 @@ instruction executed prior to the jump to the subroutine.
 instruction address to jump to. LOOP - The loop count. *Note loop
 count of 0 must be replaced by a jump. JSR - The instruction
 address to jump to (first inst of subroutine).
-(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc></reg32>
+(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2504" length="16" stride="0x0008">
+<stripe length="16" offset="0x2504" stride="0x0008">
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_ADDRS_UW" offset="0x0">
-For VS3.0 - To support more PVS instructions, increase the address
-range - Programmable Vertex Shader Flow Control Upper Word
-Addresses Register 0
+<doc>For VS3.0 - To support more PVS instructions, increase the
+address range - Programmable Vertex Shader Flow Control Upper Word
+Addresses Register 0</doc>
 <bitfield high="15" low="0" name="PVS_FC_LAST_INST_0">
 <use-enum ref="ENUM313" />
 </bitfield>
@@ -9510,12 +9819,14 @@ instruction of the subroutine.
 <doc>This field has multiple definitions as follows: JUMP - Not
 Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS +
 1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1).
-(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc></reg32>
+(Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2290" length="16" stride="0x0004">
+<stripe length="16" offset="0x2290" stride="0x0004">
 <reg32 access="rw" name="VAP_PVS_FLOW_CNTL_LOOP_INDEX"
-offset="0x0">Programmable Vertex Shader Flow Control Loop Index
-Register 0
+offset="0x0">
+<doc>Programmable Vertex Shader Flow Control Loop Index Register
+0</doc>
 <bitfield high="7" low="0" name="PVS_FC_LOOP_INIT_VAL_0" />
 <doc>This field stores the automatic loop index register init
 value. This is an 8-bit unsigned value 0-255. This field is only
@@ -9530,14 +9841,16 @@ loop.</doc>
 value is not used at loop activation. The intial loop index is
 inherited from outer loop. The loop index register step value is
 used at the end of each loop iteration ; after loop completion, the
-outer loop index register is restored</doc></reg32>
+outer loop index register is restored</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_TEX_TO_COLOR_CNTL" offset="0x2218">For
-VS3.0 color2texture - flat shading on textures - limitation: only
-first 8 vectors can have clipping with wrap shortest or point
-sprite generated textures</reg32>
-<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084">Vertex
-Fetcher Control
+<reg32 access="rw" name="VAP_TEX_TO_COLOR_CNTL" offset="0x2218">
+<doc>For VS3.0 color2texture - flat shading on textures -
+limitation: only first 8 vectors can have clipping with wrap
+shortest or point sprite generated textures</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VF_CNTL" offset="0x2084">
+<doc>Vertex Fetcher Control</doc>
 <bitfield high="3" low="0" name="PRIM_TYPE" />
 <doc>Primitive Type 0 : None (will not trigger Setup Engine to run)
 1 : Point List 2 : Line List 3 : Line Strip 4 : Triangle List 5 :
@@ -9575,9 +9888,10 @@ This mode was added specifically for HOS usage</doc>
 taken from VAP_ALT_NUM_VERTICES register instead of bits 31:16 of
 VAP_VF_CNTL</doc>
 <bitfield high="31" low="16" name="NUM_VERTICES" />
-<doc>Number of vertices in the command packet.</doc></reg32>
-<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0">Vertex
-Array of Structures Control
+<doc>Number of vertices in the command packet.</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_NUM_ARRAYS" offset="0x20C0">
+<doc>Vertex Array of Structures Control</doc>
 <bitfield high="4" low="0" name="VTX_NUM_ARRAYS" />
 <doc>The number of arrays required to represent the current vertex
 type. Each Array is described by the following three fields:
@@ -9628,9 +9942,10 @@ data if the DWORDS/VTX/AOS is less than TBD (128?) bits.</doc>
 <bitfield high="30" low="30" name="AOS_14_FETCH_SIZE" />
 <doc>See AOS_0_FETCH_SIZE</doc>
 <bitfield high="31" low="31" name="AOS_15_FETCH_SIZE" />
-<doc>See AOS_0_FETCH_SIZE</doc></reg32>
-<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180">VAP
-Vertex State Control Register
+<doc>See AOS_0_FETCH_SIZE</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_STATE_CNTL" offset="0x2180">
+<doc>VAP Vertex State Control Register</doc>
 <bitfield high="1" low="0" name="COLOR_0_ASSEMBLY_CNTL" />
 <doc>0 : Select Color 0 1 : Select User Color 0 2 : Select User
 Color 1 3 : Reserved</doc>
@@ -9660,115 +9975,158 @@ Color 1 3 : Reserved</doc>
 written. 1 : User Color 1 State IS updated when User Color 0 is
 written.</doc>
 <bitfield high="18" low="18" name="Reserved" />
-<doc>Set to 0</doc></reg32>
-<stripe addr="0x2430" length="4" stride="0x0004">
-<reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0">Data
-register</reg32>
+<doc>Set to 0</doc>
+</reg32>
+<stripe length="4" offset="0x2430" stride="0x0004">
+<reg32 access="rw" name="VAP_VTX_ST_BLND_WT" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x232C" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x232C" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_CLR_A" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2328" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x2328" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_CLR_B" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2324" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x2324" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_CLR_G" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2470" length="8" stride="0x0004">
-<reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x2470" stride="0x0004">
+<reg32 access="w" name="VAP_VTX_ST_CLR_PKD" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x2320" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x2320" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_CLR_R" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424">Data
-register</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_DISC_FOG" offset="0x2424">
+<doc>Data register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VTX_ST_EDGE_FLAGS" offset="0x245C">
-Data register
+<doc>Data register</doc>
 <bitfield high="0" low="0" name="DATA_REGISTER" />
-<doc>EDGE_FLAGS</doc></reg32>
-<reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" offset="0x24AC">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" offset="0x2498">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" offset="0x2310">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" offset="0x2314">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" offset="0x2318">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" offset="0x2450">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" offset="0x2454">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" offset="0x2458">Data
-register</reg32>
+<doc>EDGE_FLAGS</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_END_OF_PKT" offset="0x24AC">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_NORM_0_PKD" offset="0x2498">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_0_X" offset="0x2310">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Y" offset="0x2314">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_0_Z" offset="0x2318">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_1_X" offset="0x2450">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Y" offset="0x2454">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_NORM_1_Z" offset="0x2458">
+<doc>Data register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VTX_ST_PNT_SPRT_SZ" offset="0x2420">
-Data register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" offset="0x230C">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" offset="0x2490">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" offset="0x24A0">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" offset="0x2300">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" offset="0x2494">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" offset="0x24A4">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" offset="0x2304">Data
-register</reg32>
-<reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" offset="0x24A8">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" offset="0x2308">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C">Data
-register</reg32>
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_0_W_4" offset="0x230C">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_POS_0_X_2" offset="0x2490">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_POS_0_X_3" offset="0x24A0">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_0_X_4" offset="0x2300">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_2" offset="0x2494">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_POS_0_Y_3" offset="0x24A4">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_0_Y_4" offset="0x2304">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="w" name="VAP_VTX_ST_POS_0_Z_3" offset="0x24A8">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_0_Z_4" offset="0x2308">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_1_W" offset="0x244C">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_1_X" offset="0x2440">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_1_Y" offset="0x2444">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_POS_1_Z" offset="0x2448">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_PVMS" offset="0x231C">
+<doc>Data register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VTX_ST_SHININESS_0" offset="0x2428">
-Data register</reg32>
+<doc>Data register</doc>
+</reg32>
 <reg32 access="rw" name="VAP_VTX_ST_SHININESS_1" offset="0x242C">
-Data register</reg32>
-<stripe addr="0x23AC" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0">Data
-register</reg32>
+<doc>Data register</doc>
+</reg32>
+<stripe length="8" offset="0x23AC" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_TEX_Q" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x23A8" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x23A8" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_TEX_R" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x23A0" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x23A0" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_TEX_S" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<stripe addr="0x23A4" length="8" stride="0x0010">
-<reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0">Data
-register</reg32>
+<stripe length="8" offset="0x23A4" stride="0x0010">
+<reg32 access="rw" name="VAP_VTX_ST_TEX_T" offset="0x0">
+<doc>Data register</doc>
+</reg32>
 </stripe>
-<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" offset="0x2468">Data
-register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464">Data
-register</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_A" offset="0x246C">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_B" offset="0x2468">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_G" offset="0x2464">
+<doc>Data register</doc>
+</reg32>
 <reg32 access="w" name="VAP_VTX_ST_USR_CLR_PKD" offset="0x249C">
-Data register</reg32>
-<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460">Data
-register</reg32>
-<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C">Z Buffer
-Band-Width Control Defa
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="VAP_VTX_ST_USR_CLR_R" offset="0x2460">
+<doc>Data register</doc>
+</reg32>
+<reg32 access="rw" name="ZB_BW_CNTL" offset="0x4F1C">
+<doc>Z Buffer Band-Width Control Defa</doc>
 <bitfield high="0" low="0" name="HIZ_ENABLE">
 <use-enum ref="ENUM187" />
 </bitfield>
@@ -9861,8 +10219,10 @@ completely</doc>
 slots.</doc>
 <bitfield high="19" low="19" name="COVERED_PTR_MASKING_ENABL" />
 <doc>Enables discarding of pointers from pixels that are going to
-be</doc></reg32>
-<reg32 access="rw" name="ZB_CNTL" offset="0x4F00">Z Buffer Control
+be</doc>
+</reg32>
+<reg32 access="rw" name="ZB_CNTL" offset="0x4F00">
+<doc>Z Buffer Control</doc>
 <bitfield high="0" low="0" name="STENCIL_ENABLE">
 <use-enum ref="ENUM178" />
 </bitfield>
@@ -9906,15 +10266,17 @@ enabled.</doc>
 <bitfield high="6" low="6" name="STENCIL_REFMASK_FRONT_BACK">
 <use-enum ref="ENUM5" />
 </bitfield>
-<doc /></reg32>
-<reg32 access="rw" name="ZB_FIFO_SIZE" offset="0x4FD0">Sets the
-fifo sizes
+<doc />
+</reg32>
+<reg32 access="rw" name="ZB_FIFO_SIZE" offset="0x4FD0">
+<doc>Sets the fifo sizes</doc>
 <bitfield high="1" low="0" name="OP_FIFO_SIZE">
 <use-enum ref="ENUM216" />
 </bitfield>
-<doc>Determines the size of the op fifo</doc></reg32>
-<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10">Format of the
-Data in the Z buffer
+<doc>Determines the size of the op fifo</doc>
+</reg32>
+<reg32 access="rw" name="ZB_FORMAT" offset="0x4F10">
+<doc>Format of the Data in the Z buffer</doc>
 <bitfield high="3" low="0" name="DEPTHFORMAT">
 <use-enum ref="ENUM196" />
 </bitfield>
@@ -9929,34 +10291,39 @@ Data in the Z buffer
 </bitfield>
 <doc />
 <bitfield high="5" low="5" name="PEQ8" />
-<doc>This bit is unused</doc></reg32>
+<doc>This bit is unused</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_OFFSET" offset="0x4F44">
-Hierarchical Z Memory Offset
+<doc>Hierarchical Z Memory Offset</doc>
 <bitfield high="17" low="2" name="HIZ_OFFSET" />
-<doc>DWORD offset into HiZ RAM.</doc></reg32>
+<doc>DWORD offset into HiZ RAM.</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_RDINDEX" offset="0x4F50">
-Hierarchical Z Read Index
+<doc>Hierarchical Z Read Index</doc>
 <bitfield high="17" low="2" name="HIZ_RDINDEX" />
-<doc>Read index into HiZ RAM.</doc></reg32>
+<doc>Read index into HiZ RAM.</doc>
+</reg32>
 <reg32 access="rw" name="ZB_HIZ_WRINDEX" offset="0x4F48">
-Hierarchical Z Write Index
+<doc>Hierarchical Z Write Index</doc>
 <bitfield high="17" low="2" name="HIZ_WRINDEX" />
 <doc>Self-incrementing write index into the HiZ RAM. Starting write
 index must start on a DWORD boundary. Each time ZB_HIZ_DWORD is
 written, this index will autoincrement. HIZ_OFFSET and HIZ_PITCH
 are not used to compute read/write address to HIZ ram, when it is
-accessed through WRINDEX and DWORD</doc></reg32>
+accessed through WRINDEX and DWORD</doc>
+</reg32>
 <reg32 access="rw" name="ZB_STENCILREFMASK_BF" offset="0x4FD4">
-Stencil Reference Value and Mask for backfacing quads
+<doc>Stencil Reference Value and Mask for backfacing quads</doc>
 <bitfield high="7" low="0" name="STENCILREF" />
 <doc>Specifies the reference stencil value.</doc>
 <bitfield high="15" low="8" name="STENCILMASK" />
 <doc>This value is ANDed with both the reference and the current
 stencil value prior to the stencil test.</doc>
 <bitfield high="23" low="16" name="STENCILWRITEMASK" />
-<doc>Specifies the write mask for the stencil planes.</doc></reg32>
-<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04">Z and
-Stencil Function Control
+<doc>Specifies the write mask for the stencil planes.</doc>
+</reg32>
+<reg32 access="rw" name="ZB_ZSTENCILCNTL" offset="0x4F04">
+<doc>Z and Stencil Function Control</doc>
 <bitfield high="2" low="0" name="ZFUNC">
 <use-enum ref="ENUM202" />
 </bitfield>
@@ -9996,7 +10363,8 @@ faced quads, if STENCIL_FRONT_BACK =1</doc>
 <use-enum ref="ENUM5" />
 </bitfield>
 <doc>Zeroes the zb coverage mask output. This does not affect the
-updating of the depth or stencil values.</doc></reg32>
+updating of the depth or stencil values.</doc>
+</reg32>
 </group>
 <variant id="r300">
 <use-group ref="rX00_regs" />
diff --git a/radeonreg.py b/radeonreg.py
index 9b9aaa3..c7b6a7e 100755
--- a/radeonreg.py
+++ b/radeonreg.py
@@ -247,7 +247,7 @@ before attempting to read it.
         for reg in group:
             if reg.count > 1:
                 stripe = ElementTree.SubElement(group_tag, "stripe")
-                stripe.attrib["addr"] = "0x%04X" % reg.addr
+                stripe.attrib["offset"] = "0x%04X" % reg.addr
                 stripe.attrib["stride"] = "0x%04X" % reg.stride
                 stripe.attrib["length"] = str(reg.count)
 
@@ -259,7 +259,7 @@ before attempting to read it.
                 reg32.attrib["offset"] = "0x%04X" % reg.addr
 
             if reg.desc:
-                reg32.text = reg.desc
+                ElementTree.SubElement(reg32, "doc").text = reg.desc
 
             for field in reg.fields:
                 bitfield = ElementTree.SubElement(reg32, "bitfield",