diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2012-01-08 20:42:22 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2012-03-14 15:02:48 -0700 |
| commit | 99cd475cc9d3bd54140f84c24b55b9e05d7310a1 (patch) | |
| tree | d574411d6139c4d515c1203e5ceee9d0579c3992 | |
| parent | fe34006908f1ff99ada34d52c06fd80197e452ec (diff) | |
i965: Enable SIMD16 mode for shaders with loops on Gen6+.
The hardware supports it; there's no reason not to.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 15eae43f48..b4ef80b654 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1676,7 +1676,7 @@ fs_visitor::visit(ir_loop *ir) { fs_reg counter = reg_undef; - if (c->dispatch_width == 16) { + if (intel->gen < 6 && c->dispatch_width == 16) { fail("Can't support (non-uniform) control flow on 16-wide\n"); } |