diff options
| author | Ben Widawsky <ben@bwidawsk.net> | 2013-02-18 16:00:55 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-06 09:39:41 -0800 |
| commit | 4f1410d978ad4b184b61bfa0559cfd9c35f1aa0f (patch) | |
| tree | 5437b9ec75ce9e0c9e04b104e120e98b6c5a5a51 /tools | |
| parent | e35126d30ce6deda2b472498882195e37ecde81f (diff) | |
quick_dump/bdw: Just basic stuff for now
Just the interrupt registers for now.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/quick_dump/Makefile.am | 1 | ||||
| -rw-r--r-- | tools/quick_dump/broadwell | 1 | ||||
| -rw-r--r-- | tools/quick_dump/gen8_interrupt.txt | 44 |
3 files changed, 46 insertions, 0 deletions
diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index ea480827..9eb5f37a 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -26,6 +26,7 @@ EXTRA_DIST = \ gen6_other.txt sandybridge \ gen7_other.txt ivybridge \ vlv_display.txt vlv_dpio.txt valleyview \ + gen8_interrupt.txt \ quick_dump.py \ reg_access.py \ chipset.i chipset.py diff --git a/tools/quick_dump/broadwell b/tools/quick_dump/broadwell new file mode 100644 index 00000000..c73b7ca3 --- /dev/null +++ b/tools/quick_dump/broadwell @@ -0,0 +1 @@ +gen8_interrupt.txt diff --git a/tools/quick_dump/gen8_interrupt.txt b/tools/quick_dump/gen8_interrupt.txt new file mode 100644 index 00000000..d3966488 --- /dev/null +++ b/tools/quick_dump/gen8_interrupt.txt @@ -0,0 +1,44 @@ +('GEN8_MASTER_IRQ', '0x00044200', '') +('GEN8_GT_ISR0', '0x00044300', '') +('GEN8_GT_IMR0', '0x00044304', '') +('GEN8_GT_IIR0', '0x00044308', '') +('GEN8_GT_IER0', '0x0004430c', '') +('GEN8_GT_ISR1', '0x00044310', '') +('GEN8_GT_IMR1', '0x00044314', '') +('GEN8_GT_IIR1', '0x00044318', '') +('GEN8_GT_IER1', '0x0004431c', '') +('GEN8_GT_ISR2', '0x00044320', '') +('GEN8_GT_IMR2', '0x00044324', '') +('GEN8_GT_IIR2', '0x00044328', '') +('GEN8_GT_IER2', '0x0004432c', '') +('GEN8_GT_ISR3', '0x00044330', '') +('GEN8_GT_IMR3', '0x00044334', '') +('GEN8_GT_IIR3', '0x00044338', '') +('GEN8_GT_IER3', '0x0004433c', '') +('GEN8_DE_PIPE_ISR0', '0x44400', '') +('GEN8_DE_PIPE_IMR0', '0x44404', '') +('GEN8_DE_PIPE_IIR0', '0x44408', '') +('GEN8_DE_PIPE_IER0', '0x4440c', '') +('GEN8_DE_PIPE_ISR1', '0x44410', '') +('GEN8_DE_PIPE_IMR1', '0x44414', '') +('GEN8_DE_PIPE_IIR1', '0x44418', '') +('GEN8_DE_PIPE_IER1', '0x4441c', '') +('GEN8_DE_PIPE_ISR2', '0x44420', '') +('GEN8_DE_PIPE_IMR2', '0x44424', '') +('GEN8_DE_PIPE_IIR2', '0x44428', '') +('GEN8_DE_PIPE_IER2', '0x4442c', '') +('GEN8_DE_PORT_ISR', '0x44440', '') +('GEN8_DE_PORT_IMR', '0x44444', '') +('GEN8_DE_PORT_IIR', '0x44448', '') +('GEN8_DE_PORT_IER', '0x4444c', '') +('GEN8_DE_MISC_ISR', '0x44460', '') +('GEN8_DE_MISC_IMR', '0x44464', '') +('GEN8_DE_MISC_IIR', '0x44468', '') +('GEN8_DE_MISC_IER', '0x4446c', '') +('GEN8_PCU_ISR', '0x444e0', '') +('GEN8_PCU_IMR', '0x444e4', '') +('GEN8_PCU_IIR', '0x444e8', '') +('GEN8_PCU_IER', '0x444ec', '') +('RENDER_IMR', '0x000020a8', '') +('BSD_IMR', '0x000120a8', '') +('BLT_IMR', '0x000220a8', '') |