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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-12-05 14:14:35 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-12-05 14:30:14 -0800 |
| commit | 672911d7149735ee51cbcff5540b8dcb8a2de321 (patch) | |
| tree | ea66c0f34fcf8136069d452d8e922ee9751feef3 /tests | |
| parent | 40b586188c021db58a37ef23ac7d3e20547461a1 (diff) | |
gem_pipe_control_store_loop: BDW update
I've opted to not use the PIPE_CONTROL w/a for now. I am unclear if it
is actually required (the test does pass).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/gem_pipe_control_store_loop.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c index 7a400915..cef7160f 100644 --- a/tests/gem_pipe_control_store_loop.c +++ b/tests/gem_pipe_control_store_loop.c @@ -76,8 +76,7 @@ store_pipe_control_loop(bool preuse_buffer) igt_assert(target_bo); if (preuse_buffer) { - BEGIN_BATCH(6); - OUT_BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); + COLOR_BLIT_COPY_BATCH_START(devid, 0); OUT_BATCH((3 << 24) | (0xf0 << 16) | 64); OUT_BATCH(0); OUT_BATCH(1 << 16 | 1); @@ -90,6 +89,7 @@ store_pipe_control_loop(bool preuse_buffer) OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); + BLIT_RELOC_UDW(devid); OUT_BATCH(0xdeadbeef); ADVANCE_BATCH(); @@ -101,7 +101,18 @@ store_pipe_control_loop(bool preuse_buffer) /* gem_storedw_batches_loop.c is a bit overenthusiastic with * creating new batchbuffers - with buffer reuse disabled, the * support code will do that for us. */ - if (intel_gen(devid) >= 6) { + if (intel_gen(devid) >= 8) { + BEGIN_BATCH(5); + OUT_BATCH(GFX_OP_PIPE_CONTROL + 1); + OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); + OUT_RELOC(target_bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + PIPE_CONTROL_GLOBAL_GTT); + BLIT_RELOC_UDW(devid); + OUT_BATCH(val); /* write data */ + ADVANCE_BATCH(); + + } else if (intel_gen(devid) >= 6) { /* work-around hw issue, see intel_emit_post_sync_nonzero_flush * in mesa sources. */ BEGIN_BATCH(4); |