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path: root/i965_drv_video/gen6_mfc.c
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Diffstat (limited to 'i965_drv_video/gen6_mfc.c')
-rw-r--r--i965_drv_video/gen6_mfc.c317
1 files changed, 176 insertions, 141 deletions
diff --git a/i965_drv_video/gen6_mfc.c b/i965_drv_video/gen6_mfc.c
index 4540697..83540b4 100644
--- a/i965_drv_video/gen6_mfc.c
+++ b/i965_drv_video/gen6_mfc.c
@@ -41,10 +41,13 @@
static void
gen6_mfc_pipe_mode_select(VADriverContextP ctx)
{
- BEGIN_BCS_BATCH(ctx,4);
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
- OUT_BCS_BATCH(ctx, MFX_PIPE_MODE_SELECT | (4 - 2));
- OUT_BCS_BATCH(ctx,
+ BEGIN_BCS_BATCH(batch,4);
+
+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
+ OUT_BCS_BATCH(batch,
(0 << 10) | /* disable Stream-Out */
(1 << 9) | /* Post Deblocking Output */
(0 << 8) | /* Pre Deblocking Output */
@@ -52,7 +55,7 @@ gen6_mfc_pipe_mode_select(VADriverContextP ctx)
(0 << 5) | /* not in stitch mode */
(1 << 4) | /* encoding mode */
(2 << 0)); /* Standard Select: AVC */
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(0 << 20) | /* round flag in PB slice */
(0 << 19) | /* round flag in Intra8x8 */
(0 << 7) | /* expand NOA bus flag */
@@ -63,24 +66,26 @@ gen6_mfc_pipe_mode_select(VADriverContextP ctx)
(0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
(0 << 1) | /* AVC long field motion vector */
(0 << 0)); /* always calculate AVC ILDB boundary strength */
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
- BEGIN_BCS_BATCH(ctx, 6);
+ BEGIN_BCS_BATCH(batch, 6);
- OUT_BCS_BATCH(ctx, MFX_SURFACE_STATE | (6 - 2));
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch,
((mfc_context->surface_state.height - 1) << 19) |
((mfc_context->surface_state.width - 1) << 6));
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
(1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
(0 << 22) | /* surface object control state, FIXME??? */
@@ -88,112 +93,120 @@ gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_e
(0 << 2) | /* must be 0 for interleave U/V */
(1 << 1) | /* must be y-tiled */
(I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(0 << 16) | /* must be 0 for interleave U/V */
(mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
- OUT_BCS_BATCH(ctx, 0);
- ADVANCE_BCS_BATCH(ctx);
+ OUT_BCS_BATCH(batch, 0);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int i;
- BEGIN_BCS_BATCH(ctx, 24);
+ BEGIN_BCS_BATCH(batch, 24);
- OUT_BCS_BATCH(ctx, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
- OUT_BCS_BATCH(ctx, 0); /* pre output addr */
+ OUT_BCS_BATCH(batch, 0); /* pre output addr */
- OUT_BCS_RELOC(ctx, mfc_context->post_deblocking_output.bo,
+ OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0); /* post output addr */
- OUT_BCS_RELOC(ctx, mfc_context->uncompressed_picture_source.bo,
+ OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0); /* uncompressed data */
- OUT_BCS_BATCH(ctx, 0); /* StreamOut data*/
- OUT_BCS_RELOC(ctx, mfc_context->intra_row_store_scratch_buffer.bo,
+ OUT_BCS_BATCH(batch, 0); /* StreamOut data*/
+ OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
- OUT_BCS_RELOC(ctx, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
+ OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
/* 7..22 Reference pictures*/
for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
if ( mfc_context->reference_surfaces[i].bo != NULL) {
- OUT_BCS_RELOC(ctx, mfc_context->reference_surfaces[i].bo,
+ OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
} else {
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
}
}
- OUT_BCS_BATCH(ctx, 0); /* no block status */
+ OUT_BCS_BATCH(batch, 0); /* no block status */
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
- BEGIN_BCS_BATCH(ctx, 11);
+ BEGIN_BCS_BATCH(batch, 11);
- OUT_BCS_BATCH(ctx, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
/* MFX Indirect MV Object Base Address */
- OUT_BCS_RELOC(ctx, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
/*MFC Indirect PAK-BSE Object Base Address for Encoder*/
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
- BEGIN_BCS_BATCH(ctx, 4);
+ BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(ctx, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
- OUT_BCS_RELOC(ctx, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
+ OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
- BEGIN_BCS_BATCH(ctx, 13);
- OUT_BCS_BATCH(ctx, MFX_AVC_IMG_STATE | (13 - 2));
- OUT_BCS_BATCH(ctx,
+ BEGIN_BCS_BATCH(batch, 13);
+ OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
+ OUT_BCS_BATCH(batch,
((width_in_mbs * height_in_mbs) & 0xFFFF));
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(height_in_mbs << 16) |
(width_in_mbs << 0));
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(0 << 24) | /*Second Chroma QP Offset*/
(0 << 16) | /*Chroma QP Offset*/
(0 << 14) | /*Max-bit conformance Intra flag*/
@@ -202,7 +215,7 @@ gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_e
(0 << 10) | /*QM Preset FLag */
(0 << 8) | /*Image Structure*/
(0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(0 << 16) | /*Mininum Frame size*/
(0 << 15) | /*Disable reading of Macroblock Status Buffer*/
(0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
@@ -217,83 +230,87 @@ gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_e
(1 << 2) | /*Frame MB only flag*/
(0 << 1) | /*MBAFF mode is in active*/
(0 << 0) ); /*Field picture flag*/
- OUT_BCS_BATCH(ctx, 0); /*Mainly about MB rate control and debug, just ignoring*/
- OUT_BCS_BATCH(ctx, /*Inter and Intra Conformance Max size limit*/
+ OUT_BCS_BATCH(batch, 0); /*Mainly about MB rate control and debug, just ignoring*/
+ OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
(0xBB8 << 16) | /*InterMbMaxSz*/
(0xEE8) ); /*IntraMbMaxSz*/
- OUT_BCS_BATCH(ctx, 0); /*Reserved*/
- OUT_BCS_BATCH(ctx, 0); /*Slice QP Delta for bitrate control*/
- OUT_BCS_BATCH(ctx, 0); /*Slice QP Delta for bitrate control*/
- OUT_BCS_BATCH(ctx, 0x8C000000);
- OUT_BCS_BATCH(ctx, 0x00010000);
- OUT_BCS_BATCH(ctx, 0);
-
- ADVANCE_BCS_BATCH(ctx);
+ OUT_BCS_BATCH(batch, 0); /*Reserved*/
+ OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/
+ OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/
+ OUT_BCS_BATCH(batch, 0x8C000000);
+ OUT_BCS_BATCH(batch, 0x00010000);
+ OUT_BCS_BATCH(batch, 0);
+
+ ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_directmode_state(VADriverContextP ctx)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int i;
- BEGIN_BCS_BATCH(ctx, 69);
+ BEGIN_BCS_BATCH(batch, 69);
- OUT_BCS_BATCH(ctx, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
+ OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
//TODO: reference DMV
for(i = 0; i < 16; i++){
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
}
//TODO: current DMV just for test
#if 0
- OUT_BCS_RELOC(ctx, mfc_context->direct_mv_buffers[0].bo,
+ OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
0);
#else
//drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
- //OUT_BCS_BATCH(ctx, mfc_context->direct_mv_buffers[0].bo->offset);
- OUT_BCS_BATCH(ctx, 0);
+ //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
+ OUT_BCS_BATCH(batch, 0);
#endif
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
//TODO: POL list
for(i = 0; i < 34; i++) {
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
}
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
int intra_slice,
struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
- BEGIN_BCS_BATCH(ctx, 11);;
+ BEGIN_BCS_BATCH(batch, 11);;
- OUT_BCS_BATCH(ctx, MFX_AVC_SLICE_STATE | (11 - 2) );
+ OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
if ( intra_slice )
- OUT_BCS_BATCH(ctx, 2); /*Slice Type: I Slice*/
+ OUT_BCS_BATCH(batch, 2); /*Slice Type: I Slice*/
else
- OUT_BCS_BATCH(ctx, 0); /*Slice Type: P Slice*/
+ OUT_BCS_BATCH(batch, 0); /*Slice Type: P Slice*/
if ( intra_slice )
- OUT_BCS_BATCH(ctx, 0); /*no reference frames and pred_weight_table*/
+ OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
else
- OUT_BCS_BATCH(ctx, 0x00010000); /*1 reference frame*/
+ OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/
- OUT_BCS_BATCH(ctx, (0<<24) | /*Enable deblocking operation*/
+ OUT_BCS_BATCH(batch, (0<<24) | /*Enable deblocking operation*/
(26<<16) | /*Slice Quantization Parameter*/
0x0202 );
- OUT_BCS_BATCH(ctx, 0); /*First MB X&Y , the postion of current slice*/
- OUT_BCS_BATCH(ctx, ( ((mfc_context->surface_state.height+15)/16) << 16) );
+ OUT_BCS_BATCH(batch, 0); /*First MB X&Y , the postion of current slice*/
+ OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(0<<31) | /*RateControlCounterEnable = disable*/
(1<<30) | /*ResetRateControlCounter*/
(2<<28) | /*RC Triggle Mode = Loose Rate Control*/
@@ -305,91 +322,102 @@ static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
(1<<13) | /*RBSP NAL TYPE*/
(0<<12) ); /*CabacZeroWordInsertionEnable*/
- OUT_BCS_RELOC(ctx, mfc_context->mfc_indirect_pak_bse_object.bo,
+ OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
mfc_context->mfc_indirect_pak_bse_object.offset);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_qm_state(VADriverContextP ctx)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int i;
- BEGIN_BCS_BATCH(ctx, 58);
+ BEGIN_BCS_BATCH(batch, 58);
- OUT_BCS_BATCH(ctx, MFX_AVC_QM_STATE | 56);
- OUT_BCS_BATCH(ctx, 0xFF ) ;
+ OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
+ OUT_BCS_BATCH(batch, 0xFF ) ;
for( i = 0; i < 56; i++) {
- OUT_BCS_BATCH(ctx, 0x10101010);
+ OUT_BCS_BATCH(batch, 0x10101010);
}
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_fqm_state(VADriverContextP ctx)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int i;
- BEGIN_BCS_BATCH(ctx, 113);
- OUT_BCS_BATCH(ctx, MFC_AVC_FQM_STATE | (113 - 2));
+ BEGIN_BCS_BATCH(batch, 113);
+ OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
for(i = 0; i < 112;i++) {
- OUT_BCS_BATCH(ctx, 0x10001000);
+ OUT_BCS_BATCH(batch, 0x10001000);
}
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int i;
- BEGIN_BCS_BATCH(ctx, 10);
+ BEGIN_BCS_BATCH(batch, 10);
- OUT_BCS_BATCH(ctx, MFX_AVC_REF_IDX_STATE | 8);
- OUT_BCS_BATCH(ctx, 0); //Select L0
+ OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
+ OUT_BCS_BATCH(batch, 0); //Select L0
- OUT_BCS_BATCH(ctx, 0x80808000); //Only 1 reference
+ OUT_BCS_BATCH(batch, 0x80808000); //Only 1 reference
for(i = 0; i < 7; i++) {
- OUT_BCS_BATCH(ctx, 0x80808080);
+ OUT_BCS_BATCH(batch, 0x80808080);
}
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static void
gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data)
{
- BEGIN_BCS_BATCH(ctx, 4);
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
+
+ BEGIN_BCS_BATCH(batch, 4);
- OUT_BCS_BATCH(ctx, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
- OUT_BCS_BATCH(ctx, (32<<8) |
+ OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
+ OUT_BCS_BATCH(batch, (32<<8) |
(1 << 3) |
(1 << 2) |
(flush_data << 1) |
(1<<0) );
- OUT_BCS_BATCH(ctx, 0x00000003);
- OUT_BCS_BATCH(ctx, 0xABCD1234);
+ OUT_BCS_BATCH(batch, 0x00000003);
+ OUT_BCS_BATCH(batch, 0xABCD1234);
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
}
static int
gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int len_in_dwords = 11;
- BEGIN_BCS_BATCH(ctx, len_in_dwords);
+ BEGIN_BCS_BATCH(batch, len_in_dwords);
- OUT_BCS_BATCH(ctx, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx, 0);
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch, 0);
+ OUT_BCS_BATCH(batch,
(0 << 24) | /* PackedMvNum, Debug*/
(0 << 20) | /* No motion vector */
(1 << 19) | /* CbpDcY */
@@ -397,34 +425,36 @@ gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, in
(1 << 17) | /* CbpDcV */
(msg[0] & 0xFFFF) );
- OUT_BCS_BATCH(ctx, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(ctx, 0x000F000F); /* Code Block Pattern */
- OUT_BCS_BATCH(ctx, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
+ OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
+ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
+ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
/*Stuff for Intra MB*/
- OUT_BCS_BATCH(ctx, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
- OUT_BCS_BATCH(ctx, msg[2]);
- OUT_BCS_BATCH(ctx, msg[3]&0xFC);
+ OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
+ OUT_BCS_BATCH(batch, msg[2]);
+ OUT_BCS_BATCH(batch, msg[3]&0xFC);
- OUT_BCS_BATCH(ctx, 0x8040000); /*MaxSizeInWord and TargetSzieInWord*/
+ OUT_BCS_BATCH(batch, 0x8040000); /*MaxSizeInWord and TargetSzieInWord*/
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
return len_in_dwords;
}
static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
int len_in_dwords = 11;
- BEGIN_BCS_BATCH(ctx, len_in_dwords);
+ BEGIN_BCS_BATCH(batch, len_in_dwords);
- OUT_BCS_BATCH(ctx, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
+ OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
- OUT_BCS_BATCH(ctx, 32); /* 32 MV*/
- OUT_BCS_BATCH(ctx, offset);
+ OUT_BCS_BATCH(batch, 32); /* 32 MV*/
+ OUT_BCS_BATCH(batch, offset);
- OUT_BCS_BATCH(ctx,
+ OUT_BCS_BATCH(batch,
(1 << 24) | /* PackedMvNum, Debug*/
(4 << 20) | /* 8 MV, SNB don't use it*/
(1 << 19) | /* CbpDcY */
@@ -441,18 +471,18 @@ static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int
(0 << 2) | /* SkipMbFlag */
(0 << 0)); /* InterMbMode */
- OUT_BCS_BATCH(ctx, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
- OUT_BCS_BATCH(ctx, 0x000F000F); /* Code Block Pattern */
- OUT_BCS_BATCH(ctx, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
+ OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
+ OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
+ OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
/*Stuff for Inter MB*/
- OUT_BCS_BATCH(ctx, 0x0);
- OUT_BCS_BATCH(ctx, 0x0);
- OUT_BCS_BATCH(ctx, 0x0);
+ OUT_BCS_BATCH(batch, 0x0);
+ OUT_BCS_BATCH(batch, 0x0);
+ OUT_BCS_BATCH(batch, 0x0);
- OUT_BCS_BATCH(ctx, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
+ OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
- ADVANCE_BCS_BATCH(ctx);
+ ADVANCE_BCS_BATCH(batch);
return len_in_dwords;
}
@@ -517,6 +547,8 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
struct encode_state *encode_state,
struct gen6_encoder_context *gen6_encoder_context)
{
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
@@ -528,7 +560,7 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
int x,y;
- intel_batchbuffer_start_atomic_bcs(ctx, 0x1000);
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
if (is_intra) {
dri_bo_map(vme_context->vme_output.bo , 1);
@@ -541,7 +573,7 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
int qp = pSequenceParameter->initial_qp;
if (emit_new_state) {
- intel_batchbuffer_emit_mi_flush_bcs(ctx);
+ intel_batchbuffer_emit_mi_flush(batch);
gen6_mfc_pipe_mode_select(ctx);
gen6_mfc_surface_state(ctx, gen6_encoder_context);
gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
@@ -566,11 +598,11 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
offset += 64;
}
- if (intel_batchbuffer_check_free_space_bcs(ctx, object_len_in_bytes) == 0) {
- intel_batchbuffer_end_atomic_bcs(ctx);
- intel_batchbuffer_flush_bcs(ctx);
+ if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
+ intel_batchbuffer_end_atomic(batch);
+ intel_batchbuffer_flush(batch);
emit_new_state = 1;
- intel_batchbuffer_start_atomic_bcs(ctx, 0x1000);
+ intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
}
}
}
@@ -578,7 +610,7 @@ void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
if (is_intra)
dri_bo_unmap(vme_context->vme_output.bo);
- intel_batchbuffer_end_atomic_bcs(ctx);
+ intel_batchbuffer_end_atomic(batch);
}
static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
@@ -651,7 +683,10 @@ static VAStatus gen6_mfc_run(VADriverContextP ctx,
struct encode_state *encode_state,
struct gen6_encoder_context *gen6_encoder_context)
{
- intel_batchbuffer_flush_bcs(ctx); //run the pipeline
+ struct intel_driver_data *intel = intel_driver_data(ctx);
+ struct intel_batchbuffer *batch = intel->batch;
+
+ intel_batchbuffer_flush(batch); //run the pipeline
return VA_STATUS_SUCCESS;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-10 06:42:08 +0000