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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-02-15 16:03:09 -0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-02-16 00:01:28 +0100
commitad87b06fd6a5af4836562c1d318ca06a918d5466 (patch)
tree4b7715a8b9ebdbd8d165c1a011ee8957f830d7d2
parent3310db08d874d696241b84aceb9380e8e17d6e9e (diff)
reg_dumper: add interlaced information to TRANSCONF
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--tools/intel_reg_dumper.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 8c07bbb8..66470c41 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1308,9 +1308,28 @@ DEBUGSTRING(ironlake_debug_fdi_rx_misc)
DEBUGSTRING(ironlake_debug_transconf)
{
- snprintf(result, len, "%s, %s",
- val & TRANS_ENABLE ? "enable" : "disable",
- val & TRANS_STATE_ENABLE ? "active" : "inactive");
+ const char *enable = val & TRANS_ENABLE ? "enable" : "disable";
+ const char *state = val & TRANS_STATE_ENABLE ? "active" : "inactive";
+ const char *interlace;
+
+ switch ((val >> 21) & 7) {
+ case 0:
+ interlace = "progressive";
+ break;
+ case 2:
+ if (IS_GEN5(devid))
+ interlace = "interlaced sdvo";
+ else
+ interlace = "rsvd";
+ break;
+ case 3:
+ interlace = "interlaced";
+ break;
+ default:
+ interlace = "rsvd";
+ }
+
+ snprintf(result, len, "%s, %s, %s", enable, state, interlace);
}
DEBUGSTRING(ironlake_debug_panel_fitting)