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authorMichel Dänzer <michel.daenzer@amd.com>2013-11-18 11:40:08 +0100
committerMarek Olšák <marek.olsak@amd.com>2013-11-23 00:35:42 +0100
commitf0e399d8f0c3c006687e0fc8e68268087607d5f5 (patch)
tree492c94e5030e45b1fb70ff0b0b510bd181f4d577
parent67d92404d62044972599dcef3011d17fca46eed5 (diff)
radeon: don't overallocate stencil by 4 on SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
-rw-r--r--radeon/radeon_surface.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index ea7c0900..555db8d9 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -1436,16 +1436,17 @@ static void si_surf_minify(struct radeon_surface *surf,
*/
if (level == 0 && surf->last_level == 0)
/* Non-mipmap pitch padded to slice alignment */
+ /* Using just bpe here breaks stencil blitting; surf->bpe works. */
xalign = MAX2(xalign, slice_align / surf->bpe);
else if (surflevel->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
/* Small rows evenly distributed across slice */
- xalign = MAX2(xalign, slice_align / surf->bpe / surflevel->nblk_y);
+ xalign = MAX2(xalign, slice_align / bpe / surflevel->nblk_y);
surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign);
surflevel->nblk_z = ALIGN(surflevel->nblk_z, zalign);
surflevel->offset = offset;
- surflevel->pitch_bytes = surflevel->nblk_x * surf->bpe * surf->nsamples;
+ surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
surflevel->slice_size = ALIGN(surflevel->pitch_bytes * surflevel->nblk_y, slice_align);
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;