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authorEdgar E. Iglesias <edgar.iglesias@gmail.com>2010-07-05 10:24:56 +0200
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2010-07-05 10:24:56 +0200
commit3c4fe427edc88b04bd528351f5ce1c8a2e14f5f8 (patch)
tree4ef8918f3a2d0bfdc552796675da6d2a2dcfcdbd /target-cris
parent253248a3beb2440561bb28b48292ead9c2fd157f (diff)
cris: Dont clobber the MMU state across calls to cpu_get_phys_page_debug.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-cris')
-rw-r--r--target-cris/helper.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 240bda056..19c375581 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -248,9 +248,26 @@ void do_interrupt(CPUState *env)
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
uint32_t phy = addr;
+ uint32_t r_cause, r_tlb_sel, rand_lfsr;
struct cris_mmu_result res;
int miss;
+
+ /* Save MMU state. */
+ r_tlb_sel = env->sregs[SFR_RW_MM_TLB_SEL];
+ r_cause = env->sregs[SFR_R_MM_CAUSE];
+ rand_lfsr = env->mmu_rand_lfsr;
+
miss = cris_mmu_translate(&res, env, addr, 0, 0);
+ /* If D TLB misses, try I TLB. */
+ if (miss) {
+ miss = cris_mmu_translate(&res, env, addr, 2, 0);
+ }
+
+ /* Restore MMU state. */
+ env->sregs[SFR_RW_MM_TLB_SEL] = r_tlb_sel;
+ env->sregs[SFR_R_MM_CAUSE] = r_cause;
+ env->mmu_rand_lfsr = rand_lfsr;
+
if (!miss)
phy = res.phy;
D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));