pipeconf fixes

1 files changed, 28 insertions, 12 deletions

diff --git a/src/i830_display.c b/src/i830_display.c
index 287277dd..c109448c 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1009,14 +1009,21 @@ static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
 	}
 
 	ErrorF("PCH FDI RX PLL enable\n");
-	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
-	while (!((temp = INREG(fdi_rx_reg)) & FDI_RX_PLL_ENABLE)) {
-	    temp &= (~FDI_DP_PORT_WIDTH_MASK | FDI_BPC_MASK);
-	    temp |= FDI_RX_PLL_ENABLE | FDI_SEL_PCDCLK | FDI_DP_PORT_WIDTH_X4;
-	    temp |= (pipe_bpc << 11);
-	    OUTREG(fdi_rx_reg, temp); /* default 4 lanes */
-	    usleep(200);
-	}
+	temp = INREG(fdi_rx_reg);
+	
+	temp &= ~(0x7 << 16);
+	temp |= (pipe_bpc << 11);
+	temp &= ~(FDI_DP_PORT_WIDTH_MASK << 19);
+	temp |= FDI_DP_PORT_WIDTH_X4;
+
+	OUTREG(fdi_rx_reg, temp); /* default 4 lanes */
+	INREG(fdi_rx_reg);
+	usleep(200);
+
+	temp = INREG(fdi_rx_reg);
+	OUTREG(fdi_rx_reg, temp | FDI_SEL_PCDCLK); 
+	INREG(fdi_rx_reg);
+	usleep(200);
 
 	ErrorF("PCH FDI TX PLL enable\n");
 	/* Enable CPU FDI TX PLL, always on for IGDNG */
@@ -1181,7 +1188,7 @@ static void igdng_crtc_dpms(xf86CrtcPtr crtc, int mode)
 	n = 0;
 	while (!((temp = INREG(transconf_reg)) & TRANS_STATE_ENABLE)) {
 	    temp |= TRANS_ENABLE;
-	    temp &= ~FDI_BPC_MASK;
+	    temp &= ~PIPE_BPC_MASK;
 	    temp |= pipe_bpc;
 	    OUTREG(transconf_reg, temp | TRANS_ENABLE);
 	    n++;
@@ -1767,6 +1774,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
     int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
     int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
+    int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
     int lvds_reg = LVDS;
     uint32_t temp;
     int sdvo_pixel_multiply;
@@ -1974,6 +1982,7 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     }
 
     if (IS_IGDNG(pI830)) {
+	pipeconf &= ~(7 << 5);
 	if (intel_crtc->bpc == 6)
 	    pipeconf |= (1 << 6); /* 0 is 8bpc */
 	if (intel_crtc->bpc != 8)
@@ -2113,13 +2122,20 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	OUTREG(link_m1_reg, m_n.link_m);
 	OUTREG(link_n1_reg, m_n.link_n);
 
-#if 0
 	/* enable FDI RX PLL too */
-	/* XXX this doesn't work */
 	temp = INREG(fdi_rx_reg);
 	OUTREG(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
+	INREG(fdi_rx_reg);
+	usleep(200);
+
+	temp = INREG(fdi_tx_reg);
+	OUTREG(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
+	INREG(fdi_tx_reg);
+
+	temp = INREG(fdi_rx_reg);
+	OUTREG(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
+	INREG(fdi_rx_reg);
 	usleep(200);
-#endif
     }
 
     OUTREG(pipeconf_reg, pipeconf);