diff options
| author | Dave Airlie <airlied@airlied-rhel5.(none)> | 2010-04-21 11:06:37 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@airlied-rhel5.(none)> | 2010-04-21 11:06:37 +1000 |
| commit | b716410b42630ad314961f00fbe1eb906cb9f6eb (patch) | |
| tree | d2d91e0ddac0ae006dcf6f3b93404df172b99b30 | |
| parent | 2be77547cae98a438384a00de37452b468f67a3d (diff) | |
intel-2.2.1-g40-setup-fixes.patch
| -rw-r--r-- | src/i810_reg.h | 3 | ||||
| -rw-r--r-- | src/i830_crt.c | 10 | ||||
| -rw-r--r-- | src/i830_driver.c | 18 |
3 files changed, 30 insertions, 1 deletions
diff --git a/src/i810_reg.h b/src/i810_reg.h index b21f8c4a..f50c92e3 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -1082,6 +1082,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) #define RENCLK_GATE_D2 0x6208 +#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) +#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) +#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) #define RAMCLK_GATE_D 0x6210 /* CRL only */ /* diff --git a/src/i830_crt.c b/src/i830_crt.c index 4c192271..42067d4d 100644 --- a/src/i830_crt.c +++ b/src/i830_crt.c @@ -161,7 +161,15 @@ i830_crt_detect_hotplug(xf86OutputPtr output) CARD32 temp; const int timeout_ms = 1000; int starttime, curtime; + int tries = 1; + /* On 4 series desktop, CRT detect sequence need to be done twice + * to get a reliable result. */ + if (IS_G4X(pI830) && !IS_GM45(pI830)) + tries = 2; + +retry: + tries--; temp = INREG(PORT_HOTPLUG_EN); OUTREG(PORT_HOTPLUG_EN, temp | CRT_HOTPLUG_FORCE_DETECT | (1 << 5)); @@ -173,6 +181,8 @@ i830_crt_detect_hotplug(xf86OutputPtr output) break; } + if (tries > 0) + goto retry; if ((INREG(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) == CRT_HOTPLUG_MONITOR_COLOR) { diff --git a/src/i830_driver.c b/src/i830_driver.c index bbad9010..bf2a4a38 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -1876,8 +1876,24 @@ SetHWOperatingState(ScrnInfoPtr pScrn) /* Disable clock gating reported to work incorrectly according to the specs. */ - if (IS_I965GM(pI830) || IS_GM45(pI830)) { + if (IS_G4X(pI830) || IS_GM45(pI830)) { + uint32_t dspclk_gate; + OUTREG(RENCLK_GATE_D1, 0); + OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | + GS_UNIT_CLOCK_GATE_DISABLE | + CL_UNIT_CLOCK_GATE_DISABLE); + OUTREG(RAMCLK_GATE_D, 0); + dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | + OVRUNIT_CLOCK_GATE_DISABLE | + OVCUNIT_CLOCK_GATE_DISABLE; + if (IS_GM45(pI830)) + dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; + OUTREG(DSPCLK_GATE_D, dspclk_gate); + } else if (IS_I965GM(pI830)) { OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); + OUTREG(RENCLK_GATE_D2, 0); + OUTREG(DSPCLK_GATE_D, 0); + OUTREG(RAMCLK_GATE_D, 0); } else if (IS_I965G(pI830)) { OUTREG(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE | I965_ISC_CLOCK_GATE_DISABLE); |