summaryrefslogtreecommitdiff
path: root/radeondemo.h
blob: 89fb265b2bb4bc91de1f4ccd07012702b19ddc6e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
#ifndef RADEONDEMO_H
#define RADEONDEMO_H

#include <stdint.h>
#include <sys/types.h>
#include <pciaccess.h>

#define le32_to_cpu(x) (x)
#define le16_to_cpu(x) (x)
#define cpu_to_le32(x) (x)
#define cpu_to_le16(x) (x)

#include <stdbool.h>

#include "simple_list.h"

#include "radeon_bo.h"
#include "radeon_cs.h"

#include "radeon.h"

struct radeon_vbo_object {
	struct radeon_bo *vb_bo;
	unsigned verts_per_op;
	int vb_offset;
	uint32_t vb_start_op;
	uint32_t vb_op_vert_size;
	uint32_t vb_size;
	int               vb_total;
	void              *vb_ptr;
};

#define DMA_BO_FREE_TIME 1000

struct radeon_dma_bo {
    struct radeon_dma_bo *next, *prev;
    struct radeon_bo  *bo;
    int expire_counter;
};


struct r600_accel_object {
    uint32_t pitch;
    uint32_t width;
    uint32_t height;
    uint32_t offset;
    int bpp;
    uint32_t domain;
    struct radeon_bo *bo;
    uint32_t tiling_flags;
};

struct radeon;

struct radeon_accel_state {
	bool              XInited3D; /* X itself has the 3D context */
	struct radeon_vbo_object vbo;
	struct radeon_vbo_object cbuf;
	uint32_t          ib_reset_op;
	uint32_t          src_size[2];
	uint32_t          dst_size;
	struct r600_accel_object src_obj[2];
	struct r600_accel_object dst_obj;
	
	struct radeon_dma_bo bo_free;
	struct radeon_dma_bo bo_wait;
	struct radeon_dma_bo bo_reserved;
	
	void (*finish_op)(struct radeon *, int);
	
	struct radeon_bo  *shaders_bo;
	uint32_t          solid_vs_offset;
	uint32_t          solid_ps_offset;
	uint32_t          copy_vs_offset;
	uint32_t          copy_ps_offset;
};

struct radeon {
	int fd;
	struct radeon_bo *vb;
	struct radeon_accel_state accel_state;
	RADEONCardInfo *cardinfo;
	struct pci_device *pci_device;
	struct radeon_cs_manager *csm;
	struct radeon_bo_manager *bufmgr;
	struct radeon_cs *cs;

    uint64_t vram_size;
    uint64_t gart_size;
};



#       define RADEON_ROP3_ZERO             0x00000000
#       define RADEON_ROP3_DSa              0x00880000
#       define RADEON_ROP3_SDna             0x00440000
#       define RADEON_ROP3_S                0x00cc0000
#       define RADEON_ROP3_DSna             0x00220000
#       define RADEON_ROP3_D                0x00aa0000
#       define RADEON_ROP3_DSx              0x00660000
#       define RADEON_ROP3_DSo              0x00ee0000
#       define RADEON_ROP3_DSon             0x00110000
#       define RADEON_ROP3_DSxn             0x00990000
#       define RADEON_ROP3_Dn               0x00550000
#       define RADEON_ROP3_SDno             0x00dd0000
#       define RADEON_ROP3_Sn               0x00330000
#       define RADEON_ROP3_DSno             0x00bb0000
#       define RADEON_ROP3_DSan             0x00770000
#       define RADEON_ROP3_ONE              0x00ff0000
#       define RADEON_ROP3_DPa              0x00a00000
#       define RADEON_ROP3_PDna             0x00500000
#       define RADEON_ROP3_P                0x00f00000
#       define RADEON_ROP3_DPna             0x000a0000
#       define RADEON_ROP3_D                0x00aa0000
#       define RADEON_ROP3_DPx              0x005a0000
#       define RADEON_ROP3_DPo              0x00fa0000
#       define RADEON_ROP3_DPon             0x00050000
#       define RADEON_ROP3_PDxn             0x00a50000
#       define RADEON_ROP3_PDno             0x00f50000
#       define RADEON_ROP3_Pn               0x000f0000
#       define RADEON_ROP3_DPno             0x00af0000
#       define RADEON_ROP3_DPan             0x005f0000


#define CP_PACKET0(reg, n)						\
	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
#define CP_PACKET1(reg0, reg1)						\
	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
#define CP_PACKET2()							\
	(RADEON_CP_PACKET2)
#define CP_PACKET3(pkt, n)						\
	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))

#define RADEON_CP_PACKET0                           0x00000000
#define RADEON_CP_PACKET3                           0xC0000000

extern void ErrorF(const char *f, ...);

void radeon_ddx_cs_start(struct radeon *radeon,
                         int n, const char *file,
                         const char *func, int line);

#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
#define CS_FULL(cs) ((cs)->cdw > 15 * 1024)

#include "radeon_vbo.h"

void radeon_cs_flush_indirect(struct radeon *radeon);
int radeon_cp_start(struct radeon *radeon);
bool EVERGREENAllocShaders(struct radeon *radeon);
bool EVERGREENLoadShaders(struct radeon *radeon);

void evergreen_finish_op(struct radeon *radeon, int vtx_size);

void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *dst, int fg);
void evergreen_solid(struct radeon *radeon, int x1, int y1, int x2, int y2);

int radeon_detect(struct radeon *radeon);
#endif