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#include <stdlib.h>
#include "radeondemo.h"
#include "evergreen_reg.h"
#include "evergreen_state.h"
void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *dst, int fg)
{
struct radeon_accel_state *accel_state = &radeon->accel_state;
cb_config_t cb_conf;
shader_config_t vs_conf, ps_conf;
uint32_t a, r, g, b;
const_config_t ps_const_conf;
float *ps_alu_consts;
int ret;
CLEAR (cb_conf);
CLEAR (vs_conf);
CLEAR (ps_conf);
CLEAR (ps_const_conf);
accel_state->dst_obj = *dst;
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
radeon_cs_space_reset_bos(radeon->cs);
radeon_cs_space_add_persistent_bo(radeon->cs, accel_state->shaders_bo,
RADEON_GEM_DOMAIN_VRAM, 0);
radeon_cs_space_add_persistent_bo(radeon->cs, accel_state->dst_obj.bo,
0, accel_state->dst_obj.domain);
ret = radeon_cs_space_check(radeon->cs);
if (ret) {
fprintf(stderr,"fail\n");
exit(-1);
}
radeon_vbo_check(radeon, &accel_state->vbo, 16);
radeon_vbo_check(radeon, &accel_state->cbuf, 256);
radeon_cp_start(radeon);
evergreen_set_default_state(radeon);
evergreen_set_generic_scissor(radeon, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
evergreen_set_screen_scissor(radeon, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
evergreen_set_window_scissor(radeon, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
/* Shader */
vs_conf.shader_addr = accel_state->solid_vs_offset;
vs_conf.shader_size = 512;
vs_conf.num_gprs = 2;
vs_conf.stack_size = 0;
vs_conf.bo = accel_state->shaders_bo;
evergreen_vs_setup(radeon, &vs_conf, RADEON_GEM_DOMAIN_VRAM);
ps_conf.shader_addr = accel_state->solid_ps_offset;
ps_conf.shader_size = 512;
ps_conf.num_gprs = 1;
ps_conf.stack_size = 0;
ps_conf.clamp_consts = 0;
ps_conf.export_mode = 2;
ps_conf.bo = accel_state->shaders_bo;
evergreen_ps_setup(radeon, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
cb_conf.id = 0;
cb_conf.w = accel_state->dst_obj.pitch;
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
cb_conf.comp_swap = 3; /* A */
} else if (accel_state->dst_obj.bpp == 16) {
cb_conf.format = COLOR_5_6_5;
cb_conf.comp_swap = 2; /* RGB */
} else {
cb_conf.format = COLOR_8_8_8_8;
cb_conf.comp_swap = 1; /* ARGB */
}
cb_conf.source_format = EXPORT_4C_16BPC;
cb_conf.blend_clamp = 1;
/* Render setup */
cb_conf.pmask |= 4; /* B */
cb_conf.pmask |= 2; /* G */
cb_conf.pmask |= 1; /* R */
cb_conf.pmask |= 8; /* A */
cb_conf.rop = 3;
if (accel_state->dst_obj.tiling_flags == 0) {
cb_conf.array_mode = 1;
cb_conf.non_disp_tiling = 1;
}
evergreen_set_render_target(radeon, &cb_conf, accel_state->dst_obj.domain);
evergreen_set_spi(radeon, 0, 0);
/* PS alu constants */
ps_const_conf.size_bytes = 256;
ps_const_conf.type = SHADER_TYPE_PS;
ps_alu_consts = radeon_vbo_space(radeon, &accel_state->cbuf, 256);
ps_const_conf.bo = accel_state->cbuf.vb_bo;
ps_const_conf.const_addr = accel_state->cbuf.vb_offset;
if (accel_state->dst_obj.bpp == 16) {
r = (fg >> 11) & 0x1f;
g = (fg >> 5) & 0x3f;
b = (fg >> 0) & 0x1f;
ps_alu_consts[0] = (float)r / 31; /* R */
ps_alu_consts[1] = (float)g / 63; /* G */
ps_alu_consts[2] = (float)b / 31; /* B */
ps_alu_consts[3] = 1.0; /* A */
} else if (accel_state->dst_obj.bpp == 8) {
a = (fg >> 0) & 0xff;
ps_alu_consts[0] = 0.0; /* R */
ps_alu_consts[1] = 0.0; /* G */
ps_alu_consts[2] = 0.0; /* B */
ps_alu_consts[3] = (float)a / 255; /* A */
} else {
a = (fg >> 24) & 0xff;
r = (fg >> 16) & 0xff;
g = (fg >> 8) & 0xff;
b = (fg >> 0) & 0xff;
ps_alu_consts[0] = (float)r / 255; /* R */
ps_alu_consts[1] = (float)g / 255; /* G */
ps_alu_consts[2] = (float)b / 255; /* B */
ps_alu_consts[3] = (float)a / 255; /* A */
{
uint32_t *dbg;
dbg = (uint32_t *)ps_alu_consts;
fprintf(stderr,"dbg %x %x %x %x\n", dbg[0],
dbg[1], dbg[2], dbg[3]);
}
}
radeon_vbo_commit(radeon, &accel_state->cbuf);
evergreen_set_alu_consts(radeon, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
}
void evergreen_solid(struct radeon *radeon,
int x1, int y1, int x2, int y2)
{
struct radeon_accel_state *accel_state = &radeon->accel_state;
float *vb;
uint32_t *vb_i;
vb = radeon_vbo_space(radeon, &accel_state->vbo, 8);
vb[0] = (float)x1;
vb[1] = (float)y1;
vb[2] = (float)x1;
vb[3] = (float)y2;
vb[4] = (float)x2;
vb[5] = (float)y2;
{
vb_i = (uint32_t *)vb;
fprintf(stderr,"solid %d %d %d %d %x %x %x %x %x %x\n", x1, y1, x2, y2, vb_i[0],
vb_i[1], vb_i[2], vb_i[3], vb_i[4], vb_i[5]);
}
radeon_vbo_commit(radeon, &accel_state->vbo);
}
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