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|
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors: Alex Deucher <alexander.deucher@amd.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <errno.h>
#include <stdlib.h>
#include "radeondemo.h"
#include "cayman_reg.h"
#include "evergreen_state.h"
#include "radeon_drm.h"
#include "radeon_vbo.h"
/*
* Setup of default state
*/
void
cayman_set_default_state(struct radeon *radeon)
{
tex_resource_t tex_res;
shader_config_t fs_conf;
int i;
struct radeon_accel_state *accel_state = &radeon->accel_state;
if (accel_state->XInited3D)
return;
memset(&tex_res, 0, sizeof(tex_resource_t));
memset(&fs_conf, 0, sizeof(shader_config_t));
accel_state->XInited3D = true;
// evergreen_start_3d(pScrn);
BEGIN_BATCH(4);
PACK0(SQ_CONFIG, 2);
E32(0x2);
E32((93 << NUM_PS_GPRS_shift) |
(46 << NUM_VS_GPRS_shift) |
(4 << NUM_CLAUSE_TEMP_GPRS_shift));
END_BATCH();
BEGIN_BATCH(4);
PACK0(SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
E32(0);
E32(0);
END_BATCH();
BEGIN_BATCH(22);
PACK0(SQ_LDS_ALLOC, 2);
E32(0); // SQ_LDS_ALLOC
E32(0); // SQ_LDS_ALLOC_PS
PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
PACK0(SQ_GS_VERT_ITEMSIZE, 4);
E32(0);
E32(0);
E32(0);
E32(0);
PACK0(SQ_VTX_BASE_VTX_LOC, 2);
E32(0);
E32(0);
END_BATCH();
/* DB */
BEGIN_BATCH(3 + 2);
EREG(DB_Z_INFO, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_STENCIL_INFO, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_HTILE_DATA_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_Z_READ_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_Z_WRITE_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_STENCIL_READ_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(DB_STENCIL_WRITE_BASE, 0);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
// rings
BEGIN_BATCH(3 + 2);
EREG(SQ_ESGS_RING_BASE, 4096 >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_GSVS_RING_BASE, (4096 + (96 * 256 * 1)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3);
EREG(GRBM_GFX_INDEX, 0x40000000);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_ESTMP_RING_BASE, (4096 + (96 * 256 * 2)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_GSTMP_RING_BASE, (4096 + (96 * 256 * 3)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_VSTMP_RING_BASE, (4096 + (96 * 256 * 4)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_PSTMP_RING_BASE, (4096 + (96 * 256 * 5)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_LSTMP_RING_BASE, (4096 + (96 * 256 * 6)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_HSTMP_RING_BASE, (4096 + (96 * 256 * 7)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3);
EREG(GRBM_GFX_INDEX, 0x40010000);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_ESTMP_RING_BASE, (4096 + (96 * 256 * 8)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_GSTMP_RING_BASE, (4096 + (96 * 256 * 9)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_VSTMP_RING_BASE, (4096 + (96 * 256 * 10)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_PSTMP_RING_BASE, (4096 + (96 * 256 * 11)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_LSTMP_RING_BASE, (4096 + (96 * 256 * 12)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3 + 2);
EREG(SQ_HSTMP_RING_BASE, (4096 + (96 * 256 * 13)) >> 8);
RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
BEGIN_BATCH(3);
EREG(GRBM_GFX_INDEX, 0xC0000000);
END_BATCH();
BEGIN_BATCH(24);
EREG(SQ_ESGS_RING_SIZE, 0x50);
EREG(SQ_GSVS_RING_SIZE, 0x60);
EREG(SQ_ESTMP_RING_SIZE, 0x20);
EREG(SQ_GSTMP_RING_SIZE, 0x20);
EREG(SQ_VSTMP_RING_SIZE, 0x20);
EREG(SQ_PSTMP_RING_SIZE, 0x20);
EREG(SQ_LSTMP_RING_SIZE, 0x20);
EREG(SQ_HSTMP_RING_SIZE, 0x20);
END_BATCH();
BEGIN_BATCH(68 + 98 + 15);
// 68
E32(0xC0426900); // ***TYPE 3*** Opcode(0x69) == IT_SET_CONTEXT_REG 0x0043 DWORD 0x001c PKT
E32(0x00000094); // ***TYPE 3*** Body
E32(0x80000000); // 0x0000A094 mmPA_SC_VPORT_SCISSOR_0_TL
E32(0x02000200); // 0x0000A095 mmPA_SC_VPORT_SCISSOR_0_BR
E32(0x80000000); // 0x0000A096 mmPA_SC_VPORT_SCISSOR_1_TL
E32(0x20002000); // 0x0000A097 mmPA_SC_VPORT_SCISSOR_1_BR
E32(0x80000000); // 0x0000A098 mmPA_SC_VPORT_SCISSOR_2_TL
E32(0x20002000); // 0x0000A099 mmPA_SC_VPORT_SCISSOR_2_BR
E32(0x80000000); // 0x0000A09A mmPA_SC_VPORT_SCISSOR_3_TL
E32(0x20002000); // 0x0000A09B mmPA_SC_VPORT_SCISSOR_3_BR
E32(0x80000000); // 0x0000A09C mmPA_SC_VPORT_SCISSOR_4_TL
E32(0x20002000); // 0x0000A09D mmPA_SC_VPORT_SCISSOR_4_BR
E32(0x80000000); // 0x0000A09E mmPA_SC_VPORT_SCISSOR_5_TL
E32(0x20002000); // 0x0000A09F mmPA_SC_VPORT_SCISSOR_5_BR
E32(0x80000000); // 0x0000A0A0 mmPA_SC_VPORT_SCISSOR_6_TL
E32(0x20002000); // 0x0000A0A1 mmPA_SC_VPORT_SCISSOR_6_BR
E32(0x80000000); // 0x0000A0A2 mmPA_SC_VPORT_SCISSOR_7_TL
E32(0x20002000); // 0x0000A0A3 mmPA_SC_VPORT_SCISSOR_7_BR
E32(0x80000000); // 0x0000A0A4 mmPA_SC_VPORT_SCISSOR_8_TL
E32(0x20002000); // 0x0000A0A5 mmPA_SC_VPORT_SCISSOR_8_BR
E32(0x80000000); // 0x0000A0A6 mmPA_SC_VPORT_SCISSOR_9_TL
E32(0x20002000); // 0x0000A0A7 mmPA_SC_VPORT_SCISSOR_9_BR
E32(0x80000000); // 0x0000A0A8 mmPA_SC_VPORT_SCISSOR_10_TL
E32(0x20002000); // 0x0000A0A9 mmPA_SC_VPORT_SCISSOR_10_BR
E32(0x80000000); // 0x0000A0AA mmPA_SC_VPORT_SCISSOR_11_TL
E32(0x20002000); // 0x0000A0AB mmPA_SC_VPORT_SCISSOR_11_BR
E32(0x80000000); // 0x0000A0AC mmPA_SC_VPORT_SCISSOR_12_TL
E32(0x20002000); // 0x0000A0AD mmPA_SC_VPORT_SCISSOR_12_BR
E32(0x80000000); // 0x0000A0AE mmPA_SC_VPORT_SCISSOR_13_TL
E32(0x20002000); // 0x0000A0AF mmPA_SC_VPORT_SCISSOR_13_BR
E32(0x80000000); // 0x0000A0B0 mmPA_SC_VPORT_SCISSOR_14_TL
E32(0x20002000); // 0x0000A0B1 mmPA_SC_VPORT_SCISSOR_14_BR
E32(0x80000000); // 0x0000A0B2 mmPA_SC_VPORT_SCISSOR_15_TL
E32(0x20002000); // 0x0000A0B3 mmPA_SC_VPORT_SCISSOR_15_BR
E32(0x00000000); // 0x0000A0B4 mmPA_SC_VPORT_ZMIN_0
E32(0x3F800000); // 0x0000A0B5 mmPA_SC_VPORT_ZMAX_0
E32(0x00000000); // 0x0000A0B6 mmPA_SC_VPORT_ZMIN_1
E32(0x3F800000); // 0x0000A0B7 mmPA_SC_VPORT_ZMAX_1
E32(0x00000000); // 0x0000A0B8 mmPA_SC_VPORT_ZMIN_2
E32(0x3F800000); // 0x0000A0B9 mmPA_SC_VPORT_ZMAX_2
E32(0x00000000); // 0x0000A0BA mmPA_SC_VPORT_ZMIN_3
E32(0x3F800000); // 0x0000A0BB mmPA_SC_VPORT_ZMAX_3
E32(0x00000000); // 0x0000A0BC mmPA_SC_VPORT_ZMIN_4
E32(0x3F800000); // 0x0000A0BD mmPA_SC_VPORT_ZMAX_4
E32(0x00000000); // 0x0000A0BE mmPA_SC_VPORT_ZMIN_5
E32(0x3F800000); // 0x0000A0BF mmPA_SC_VPORT_ZMAX_5
E32(0x00000000); // 0x0000A0C0 mmPA_SC_VPORT_ZMIN_6
E32(0x3F800000); // 0x0000A0C1 mmPA_SC_VPORT_ZMAX_6
E32(0x00000000); // 0x0000A0C2 mmPA_SC_VPORT_ZMIN_7
E32(0x3F800000); // 0x0000A0C3 mmPA_SC_VPORT_ZMAX_7
E32(0x00000000); // 0x0000A0C4 mmPA_SC_VPORT_ZMIN_8
E32(0x3F800000); // 0x0000A0C5 mmPA_SC_VPORT_ZMAX_8
E32(0x00000000); // 0x0000A0C6 mmPA_SC_VPORT_ZMIN_9
E32(0x3F800000); // 0x0000A0C7 mmPA_SC_VPORT_ZMAX_9
E32(0x00000000); // 0x0000A0C8 mmPA_SC_VPORT_ZMIN_10
E32(0x3F800000); // 0x0000A0C9 mmPA_SC_VPORT_ZMAX_10
E32(0x00000000); // 0x0000A0CA mmPA_SC_VPORT_ZMIN_11
E32(0x3F800000); // 0x0000A0CB mmPA_SC_VPORT_ZMAX_11
E32(0x00000000); // 0x0000A0CC mmPA_SC_VPORT_ZMIN_12
E32(0x3F800000); // 0x0000A0CD mmPA_SC_VPORT_ZMAX_12
E32(0x00000000); // 0x0000A0CE mmPA_SC_VPORT_ZMIN_13
E32(0x3F800000); // 0x0000A0CF mmPA_SC_VPORT_ZMAX_13
E32(0x00000000); // 0x0000A0D0 mmPA_SC_VPORT_ZMIN_14
E32(0x3F800000); // 0x0000A0D1 mmPA_SC_VPORT_ZMAX_14
E32(0x00000000); // 0x0000A0D2 mmPA_SC_VPORT_ZMIN_15
E32(0x3F800000); // 0x0000A0D3 mmPA_SC_VPORT_ZMAX_15
E32(0x00000000); // 0x0000A0D4 mmSX_MISC
E32(0x000001FF); // 0x0000A0D5 mmSX_SURFACE_SYNC
// 98
E32(0xC0606900); // ***TYPE 3*** Opcode(0x69) == IT_SET_CONTEXT_REG 0x0061 DWORD 0x0020 PKT
E32(0x0000010F); // ***TYPE 3*** Body
E32(0x42800000); // 0x0000A10F mmPA_CL_VPORT_XSCALE
E32(0x42800000); // 0x0000A110 mmPA_CL_VPORT_XOFFSET
E32(0xC2800000); // 0x0000A111 mmPA_CL_VPORT_YSCALE
E32(0x42800000); // 0x0000A112 mmPA_CL_VPORT_YOFFSET
E32(0x3F000000); // 0x0000A113 mmPA_CL_VPORT_ZSCALE
E32(0x3F000000); // 0x0000A114 mmPA_CL_VPORT_ZOFFSET
E32(0x43800000); // 0x0000A115 mmPA_CL_VPORT_XSCALE_1
E32(0x43800000); // 0x0000A116 mmPA_CL_VPORT_XOFFSET_1
E32(0xC3800000); // 0x0000A117 mmPA_CL_VPORT_YSCALE_1
E32(0x43800000); // 0x0000A118 mmPA_CL_VPORT_YOFFSET_1
E32(0x3F000000); // 0x0000A119 mmPA_CL_VPORT_ZSCALE_1
E32(0x3F000000); // 0x0000A11A mmPA_CL_VPORT_ZOFFSET_1
E32(0x43800000); // 0x0000A11B mmPA_CL_VPORT_XSCALE_2
E32(0x43800000); // 0x0000A11C mmPA_CL_VPORT_XOFFSET_2
E32(0xC3800000); // 0x0000A11D mmPA_CL_VPORT_YSCALE_2
E32(0x43800000); // 0x0000A11E mmPA_CL_VPORT_YOFFSET_2
E32(0x3F000000); // 0x0000A11F mmPA_CL_VPORT_ZSCALE_2
E32(0x3F000000); // 0x0000A120 mmPA_CL_VPORT_ZOFFSET_2
E32(0x43800000); // 0x0000A121 mmPA_CL_VPORT_XSCALE_3
E32(0x43800000); // 0x0000A122 mmPA_CL_VPORT_XOFFSET_3
E32(0xC3800000); // 0x0000A123 mmPA_CL_VPORT_YSCALE_3
E32(0x43800000); // 0x0000A124 mmPA_CL_VPORT_YOFFSET_3
E32(0x3F000000); // 0x0000A125 mmPA_CL_VPORT_ZSCALE_3
E32(0x3F000000); // 0x0000A126 mmPA_CL_VPORT_ZOFFSET_3
E32(0x43800000); // 0x0000A127 mmPA_CL_VPORT_XSCALE_4
E32(0x43800000); // 0x0000A128 mmPA_CL_VPORT_XOFFSET_4
E32(0xC3800000); // 0x0000A129 mmPA_CL_VPORT_YSCALE_4
E32(0x43800000); // 0x0000A12A mmPA_CL_VPORT_YOFFSET_4
E32(0x3F000000); // 0x0000A12B mmPA_CL_VPORT_ZSCALE_4
E32(0x3F000000); // 0x0000A12C mmPA_CL_VPORT_ZOFFSET_4
E32(0x43800000); // 0x0000A12D mmPA_CL_VPORT_XSCALE_5
E32(0x43800000); // 0x0000A12E mmPA_CL_VPORT_XOFFSET_5
E32(0xC3800000); // 0x0000A12F mmPA_CL_VPORT_YSCALE_5
E32(0x43800000); // 0x0000A130 mmPA_CL_VPORT_YOFFSET_5
E32(0x3F000000); // 0x0000A131 mmPA_CL_VPORT_ZSCALE_5
E32(0x3F000000); // 0x0000A132 mmPA_CL_VPORT_ZOFFSET_5
E32(0x43800000); // 0x0000A133 mmPA_CL_VPORT_XSCALE_6
E32(0x43800000); // 0x0000A134 mmPA_CL_VPORT_XOFFSET_6
E32(0xC3800000); // 0x0000A135 mmPA_CL_VPORT_YSCALE_6
E32(0x43800000); // 0x0000A136 mmPA_CL_VPORT_YOFFSET_6
E32(0x3F000000); // 0x0000A137 mmPA_CL_VPORT_ZSCALE_6
E32(0x3F000000); // 0x0000A138 mmPA_CL_VPORT_ZOFFSET_6
E32(0x43800000); // 0x0000A139 mmPA_CL_VPORT_XSCALE_7
E32(0x43800000); // 0x0000A13A mmPA_CL_VPORT_XOFFSET_7
E32(0xC3800000); // 0x0000A13B mmPA_CL_VPORT_YSCALE_7
E32(0x43800000); // 0x0000A13C mmPA_CL_VPORT_YOFFSET_7
E32(0x3F000000); // 0x0000A13D mmPA_CL_VPORT_ZSCALE_7
E32(0x3F000000); // 0x0000A13E mmPA_CL_VPORT_ZOFFSET_7
E32(0x43800000); // 0x0000A13F mmPA_CL_VPORT_XSCALE_8
E32(0x43800000); // 0x0000A140 mmPA_CL_VPORT_XOFFSET_8
E32(0xC3800000); // 0x0000A141 mmPA_CL_VPORT_YSCALE_8
E32(0x43800000); // 0x0000A142 mmPA_CL_VPORT_YOFFSET_8
E32(0x3F000000); // 0x0000A143 mmPA_CL_VPORT_ZSCALE_8
E32(0x3F000000); // 0x0000A144 mmPA_CL_VPORT_ZOFFSET_8
E32(0x43800000); // 0x0000A145 mmPA_CL_VPORT_XSCALE_9
E32(0x43800000); // 0x0000A146 mmPA_CL_VPORT_XOFFSET_9
E32(0xC3800000); // 0x0000A147 mmPA_CL_VPORT_YSCALE_9
E32(0x43800000); // 0x0000A148 mmPA_CL_VPORT_YOFFSET_9
E32(0x3F000000); // 0x0000A149 mmPA_CL_VPORT_ZSCALE_9
E32(0x3F000000); // 0x0000A14A mmPA_CL_VPORT_ZOFFSET_9
E32(0x43800000); // 0x0000A14B mmPA_CL_VPORT_XSCALE_10
E32(0x43800000); // 0x0000A14C mmPA_CL_VPORT_XOFFSET_10
E32(0xC3800000); // 0x0000A14D mmPA_CL_VPORT_YSCALE_10
E32(0x43800000); // 0x0000A14E mmPA_CL_VPORT_YOFFSET_10
E32(0x3F000000); // 0x0000A14F mmPA_CL_VPORT_ZSCALE_10
E32(0x3F000000); // 0x0000A150 mmPA_CL_VPORT_ZOFFSET_10
E32(0x43800000); // 0x0000A151 mmPA_CL_VPORT_XSCALE_11
E32(0x43800000); // 0x0000A152 mmPA_CL_VPORT_XOFFSET_11
E32(0xC3800000); // 0x0000A153 mmPA_CL_VPORT_YSCALE_11
E32(0x43800000); // 0x0000A154 mmPA_CL_VPORT_YOFFSET_11
E32(0x3F000000); // 0x0000A155 mmPA_CL_VPORT_ZSCALE_11
E32(0x3F000000); // 0x0000A156 mmPA_CL_VPORT_ZOFFSET_11
E32(0x43800000); // 0x0000A157 mmPA_CL_VPORT_XSCALE_12
E32(0x43800000); // 0x0000A158 mmPA_CL_VPORT_XOFFSET_12
E32(0xC3800000); // 0x0000A159 mmPA_CL_VPORT_YSCALE_12
E32(0x43800000); // 0x0000A15A mmPA_CL_VPORT_YOFFSET_12
E32(0x3F000000); // 0x0000A15B mmPA_CL_VPORT_ZSCALE_12
E32(0x3F000000); // 0x0000A15C mmPA_CL_VPORT_ZOFFSET_12
E32(0x43800000); // 0x0000A15D mmPA_CL_VPORT_XSCALE_13
E32(0x43800000); // 0x0000A15E mmPA_CL_VPORT_XOFFSET_13
E32(0xC3800000); // 0x0000A15F mmPA_CL_VPORT_YSCALE_13
E32(0x43800000); // 0x0000A160 mmPA_CL_VPORT_YOFFSET_13
E32(0x3F000000); // 0x0000A161 mmPA_CL_VPORT_ZSCALE_13
E32(0x3F000000); // 0x0000A162 mmPA_CL_VPORT_ZOFFSET_13
E32(0x43800000); // 0x0000A163 mmPA_CL_VPORT_XSCALE_14
E32(0x43800000); // 0x0000A164 mmPA_CL_VPORT_XOFFSET_14
E32(0xC3800000); // 0x0000A165 mmPA_CL_VPORT_YSCALE_14
E32(0x43800000); // 0x0000A166 mmPA_CL_VPORT_YOFFSET_14
E32(0x3F000000); // 0x0000A167 mmPA_CL_VPORT_ZSCALE_14
E32(0x3F000000); // 0x0000A168 mmPA_CL_VPORT_ZOFFSET_14
E32(0x43800000); // 0x0000A169 mmPA_CL_VPORT_XSCALE_15
E32(0x43800000); // 0x0000A16A mmPA_CL_VPORT_XOFFSET_15
E32(0xC3800000); // 0x0000A16B mmPA_CL_VPORT_YSCALE_15
E32(0x43800000); // 0x0000A16C mmPA_CL_VPORT_YOFFSET_15
E32(0x3F000000); // 0x0000A16D mmPA_CL_VPORT_ZSCALE_15
E32(0x3F000000); // 0x0000A16E mmPA_CL_VPORT_ZOFFSET_15
// 15
EREG(SQ_PGM_RESOURCES_2_GS, 0);
EREG(SQ_PGM_RESOURCES_2_ES, 0);
EREG(SQ_PGM_RESOURCES_FS, 0);
EREG(SQ_PGM_RESOURCES_2_HS, 0);
EREG(SQ_PGM_RESOURCES_2_LS, 0);
END_BATCH();
BEGIN_BATCH(4);
PACK0(DB_DEPTH_SIZE, 2);
E32(0); // DB_DEPTH_SIZE
E32(0); // DB_DEPTH_SLICE
END_BATCH();
BEGIN_BATCH(54);
EREG(DB_DEPTH_INFO, 0);
PACK0(DB_DEPTH_CONTROL, 2);
E32(0); // DB_DEPTH_CONTROL
E32(0); //(1 << 16) | (1 << 20)); // DB_EQAA
PACK0(PA_SC_VPORT_ZMIN_0, 2);
EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
PACK0(DB_RENDER_CONTROL, 5);
E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
E32(0); // DB_COUNT_CONTROL
E32((1 << 24) | (1<<25)); // DB_DEPTH_VIEW
E32(0x2a); // DB_RENDER_OVERRIDE
E32(0); // DB_RENDER_OVERRIDE2
PACK0(DB_STENCIL_CLEAR, 2);
E32(0); // DB_STENCIL_CLEAR
E32(0); // DB_DEPTH_CLEAR
EREG(DB_ALPHA_TO_MASK, ((2 << ALPHA_TO_MASK_OFFSET0_shift) |
(2 << ALPHA_TO_MASK_OFFSET1_shift) |
(2 << ALPHA_TO_MASK_OFFSET2_shift) |
(2 << ALPHA_TO_MASK_OFFSET3_shift)));
EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
// SX
PACK0(SX_MISC, 2);
E32(0); // SX_MISC
E32(0x1ff); // SX_SURFACE_SYNC
// CB
PACK0(SX_ALPHA_TEST_CONTROL, 5);
E32(0); // SX_ALPHA_TEST_CONTROL
E32(0x00000000); //CB_BLEND_RED
E32(0x00000000); //CB_BLEND_GREEN
E32(0x00000000); //CB_BLEND_BLUE
E32(0x00000000); //CB_BLEND_ALPHA
EREG(CB_SHADER_MASK, OUTPUT0_ENABLE_mask);
// SC
EREG(PA_SC_WINDOW_OFFSET, ((0 << WINDOW_X_OFFSET_shift) |
(0 << WINDOW_Y_OFFSET_shift)));
EREG(PA_SC_CLIPRECT_RULE, CLIP_RULE_mask);
EREG(PA_SC_EDGERULE, 0xAAAAAAAA);
EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
END_BATCH();
/* clip boolean is set to always visible -> doesn't matter */
for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
evergreen_set_clip_rect (radeon, i, 0, 0, 8192, 8192);
for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
evergreen_set_vport_scissor (radeon, i, 0, 0, 8192, 8192);
BEGIN_BATCH(79);
PACK0(PA_SC_MODE_CNTL_0, 6);
E32(0); // PA_SC_MODE_CNTL_0
E32(0); // PA_SC_MODE_CNTL_1
E32(0); // VGT_ENHANCE
E32(0x00000100); // VGT_GS_PER_ES
E32(0x00000080); // VGT_ES_PER_GS
E32(0x00000002); // VGT_GS_PER_VS
PACK0(PA_SC_CENTROID_PRIORITY_0, 27); /* 28bd4 */
E32((0 << DISTANCE_0_shift) |
(1 << DISTANCE_1_shift) |
(2 << DISTANCE_2_shift) |
(3 << DISTANCE_3_shift) |
(4 << DISTANCE_4_shift) |
(5 << DISTANCE_5_shift) |
(6 << DISTANCE_6_shift) |
(7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0
E32((8 << DISTANCE_8_shift) |
(9 << DISTANCE_9_shift) |
(10 << DISTANCE_10_shift) |
(11 << DISTANCE_11_shift) |
(12 << DISTANCE_12_shift) |
(13 << DISTANCE_13_shift) |
(14 << DISTANCE_14_shift) |
(15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1
E32(0); // PA_SC_LINE_CNTL
E32(0); // PA_SC_AA_CONFIG
E32((PIX_CENTER_bit)); // PA_SU_VTX_CNTL
EFLOAT(1.0); // PA_CL_GB_VERT_CLIP_ADJ
EFLOAT(1.0); // PA_CL_GB_VERT_DISC_ADJ
EFLOAT(1.0); // PA_CL_GB_HORZ_CLIP_ADJ
EFLOAT(1.0); // PA_CL_GB_HORZ_DISC_ADJ
E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_* 0xbf8
E32(0);
E32(0); // 28c00
E32(0);
E32(0);
E32(0);
E32(0); // 28c10
E32(0);
E32(0);
E32(0);
E32(0); // 28c20
E32(0);
E32(0);
E32(0);
E32(0); // 28c03
E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_*
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
// CL
PACK0(PA_CL_CLIP_CNTL, 10);
E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
E32(FACE_bit); // PA_SU_SC_MODE_CNTL
E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
E32(0x01000000); // PA_CL_VS_OUT_CNTL
E32(0); // PA_CL_NANINF_CNTL
E32(0); // PA_SU_LINE_STIPPLE_CNTL
E32(0); // PA_SU_LINE_STIPPLE_SCALE
E32(0); // PA_SU_PRIM_FILTER_CNTL
E32(0); // SQ_LSTMP_RING_ITEMSIZE
E32(0); // SQ_HSTMP_RING_ITEMSIZE
// SU
PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
/* src = semantic id 0; mask = semantic id 1 */
EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
(1 << SEMANTIC_1_shift)));
PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
/* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
E32(((0 << SEMANTIC_shift) |
(0x01 << DEFAULT_VAL_shift))|(1<<11));
/* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
E32(((1 << SEMANTIC_shift) |
(0x01 << DEFAULT_VAL_shift))|(1<<11));
PACK0(SPI_INPUT_Z, 13);
E32(0); // SPI_INPUT_Z
E32(0); // SPI_FOG_CNTL
E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
E32(0); // SPI_PS_IN_CONTROL_2
E32(0);
E32(0);
E32(0);
E32(0);
E32(0); // SPI_GPR_MGMT
E32(0); // SPI_LDS_MGMT
E32(0); // SPI_STACK_MGMT
E32(0); // SPI_WAVE_MGMT_1
E32(0); // SPI_WAVE_MGMT_2
END_BATCH();
// clear FS
fs_conf.bo = accel_state->shaders_bo;
evergreen_fs_setup(radeon, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
BEGIN_BATCH(51);
PACK0(VGT_MAX_VTX_INDX, 4);
E32(0xffffffff); // VGT_MAX_VTX_INDX
E32(0); // VGT_MIN_VTX_INDX
E32(0); // VGT_INDX_OFFSET
E32(0); // VGT_MULTI_PRIM_IB_RESET_INDX
PACK0(VGT_INSTANCE_STEP_RATE_0, 3);
E32(0); // VGT_INSTANCE_STEP_RATE_0
E32(0); // VGT_INSTANCE_STEP_RATE_1
E32(0x0); // IA_MULTI_VGT_PARAM
PACK0(VGT_REUSE_OFF, 6);
E32(0); // VGT_REUSE_OFF
E32(0); // VGT_VTX_CNT_EN
E32(0); // DB_HTILE_SURFACE
E32(0); // DB_SRESULTS_COMPARE_STATE0
E32(0); // DB_SRESULTS_COMPARE_STATE1
E32(0); // DB_PRELOAD_CONTROL
PACK0(PA_SU_POINT_SIZE, 17);
E32(0); // PA_SU_POINT_SIZE
E32(0); // PA_SU_POINT_MINMAX
E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
E32(0); // PA_SC_LINE_STIPPLE
E32(0); // VGT_OUTPUT_PATH_CNTL
E32(0); // VGT_HOS_CNTL
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0);
E32(0); // VGT_GS_MODE
EREG(VGT_PRIMITIVEID_EN, 0);
EREG(VGT_MULTI_PRIM_IB_RESET_EN, 0);
EREG(VGT_SHADER_STAGES_EN, 0);
PACK0(VGT_STRMOUT_CONFIG, 2);
E32(0);
E32(0);
END_BATCH();
}
bool
CAYMANLoadShaders(struct radeon *radeon)
{
struct radeon_accel_state *accel_state = &radeon->accel_state;
RADEONChipFamily ChipSet = radeon->cardinfo->chip_family;
uint32_t *shader;
int ret;
ret = radeon_bo_map(accel_state->shaders_bo, 1);
if (ret) {
ErrorF("failed to map shader %d\n", ret);
exit(-1);
return false;
}
shader = accel_state->shaders_bo->ptr;
/* solid vs --------------------------------------- */
accel_state->solid_vs_offset = 0;
cayman_solid_vs(ChipSet, shader + accel_state->solid_vs_offset / 4);
/* solid ps --------------------------------------- */
accel_state->solid_ps_offset = 512;
cayman_solid_ps(ChipSet, shader + accel_state->solid_ps_offset / 4);
/* copy vs --------------------------------------- */
accel_state->copy_vs_offset = 1024;
cayman_copy_vs(ChipSet, shader + accel_state->copy_vs_offset / 4);
/* copy ps --------------------------------------- */
accel_state->copy_ps_offset = 1536;
cayman_copy_ps(ChipSet, shader + accel_state->copy_ps_offset / 4);
#if 0
/* comp vs --------------------------------------- */
accel_state->comp_vs_offset = 2048;
cayman_comp_vs(ChipSet, shader + accel_state->comp_vs_offset / 4);
/* comp ps --------------------------------------- */
accel_state->comp_ps_offset = 2560;
cayman_comp_ps(ChipSet, shader + accel_state->comp_ps_offset / 4);
/* xv vs --------------------------------------- */
accel_state->xv_vs_offset = 3072;
cayman_xv_vs(ChipSet, shader + accel_state->xv_vs_offset / 4);
/* xv ps --------------------------------------- */
accel_state->xv_ps_offset = 3584;
cayman_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);
#endif
radeon_bo_unmap(accel_state->shaders_bo);
return true;
}
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