cstest: set bo up so same size as my screen bo.

This emits the exact same stream as my DDX, also the DDX renders fine.

same vbo same consts
wtf.

4 files changed, 108 insertions, 66 deletions

diff --git a/evergreen_accel.c b/evergreen_accel.c
index 1d66172..ce7e8c3 100644
--- a/evergreen_accel.c
+++ b/evergreen_accel.c
@@ -1102,11 +1102,7 @@ evergreen_draw_auto(struct radeon *radeon, draw_config_t *draw_conf)
     BEGIN_BATCH(10);
     EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
     PACK3(IT_INDEX_TYPE, 1);
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);
-#else
     E32(draw_conf->index_type);
-#endif
     PACK3(IT_NUM_INSTANCES, 1);
     E32(draw_conf->num_instances);
     PACK3(IT_DRAW_INDEX_AUTO, 2);
@@ -1145,9 +1141,6 @@ void evergreen_finish_op(struct radeon *radeon, int vtx_size)
     vtx_res.dst_sel_y       = SQ_SEL_Y;
     vtx_res.dst_sel_z       = SQ_SEL_Z;
     vtx_res.dst_sel_w       = SQ_SEL_W;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    vtx_res.endian          = SQ_ENDIAN_8IN32;
-#endif
     evergreen_set_vtx_resource(radeon, &vtx_res, RADEON_GEM_DOMAIN_GTT);
 
     /* Draw */
diff --git a/evergreen_ops.c b/evergreen_ops.c
index 3235dab..2bca55b 100644
--- a/evergreen_ops.c
+++ b/evergreen_ops.c
@@ -1,9 +1,10 @@
 
+#include <stdlib.h>
 #include "radeondemo.h"
 #include "evergreen_reg.h"
 #include "evergreen_state.h"
 
-void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *obj, int fg)
+void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *dst, int fg)
 {
 	struct radeon_accel_state *accel_state = &radeon->accel_state;
 	cb_config_t     cb_conf;
@@ -18,7 +19,9 @@ void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *obj,
 	CLEAR (ps_conf);
 	CLEAR (ps_const_conf);
 
-	accel_state->dst_obj = *obj;
+	accel_state->dst_obj = *dst;
+	accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
+
 	memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object));
 	memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object));
 
@@ -66,37 +69,33 @@ void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *obj,
 	cb_conf.base = accel_state->dst_obj.offset;
 	cb_conf.bo = accel_state->dst_obj.bo;
 
-    if (accel_state->dst_obj.bpp == 8) {
-	cb_conf.format = COLOR_8;
-	cb_conf.comp_swap = 3; /* A */
-    } else if (accel_state->dst_obj.bpp == 16) {
-	cb_conf.format = COLOR_5_6_5;
-	cb_conf.comp_swap = 2; /* RGB */
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-	cb_conf.endian = ENDIAN_8IN16;
-#endif
-    } else {
-	cb_conf.format = COLOR_8_8_8_8;
-	cb_conf.comp_swap = 1; /* ARGB */
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-	cb_conf.endian = ENDIAN_8IN32;
-#endif
-    }
-    cb_conf.source_format = EXPORT_4C_16BPC;
-    cb_conf.blend_clamp = 1;
-    /* Render setup */
-    cb_conf.pmask |= 4; /* B */
-    cb_conf.pmask |= 2; /* G */
-    cb_conf.pmask |= 1; /* R */
-    cb_conf.pmask |= 8; /* A */
-    cb_conf.rop = RADEON_ROP3_P;
-    if (accel_state->dst_obj.tiling_flags == 0) {
-	cb_conf.array_mode = 1;
-	cb_conf.non_disp_tiling = 1;
-    }
-    evergreen_set_render_target(radeon, &cb_conf, accel_state->dst_obj.domain);
+	if (accel_state->dst_obj.bpp == 8) {
+		cb_conf.format = COLOR_8;
+		cb_conf.comp_swap = 3; /* A */
+	} else if (accel_state->dst_obj.bpp == 16) {
+		cb_conf.format = COLOR_5_6_5;
+		cb_conf.comp_swap = 2; /* RGB */
+
+	} else {
+		cb_conf.format = COLOR_8_8_8_8;
+		cb_conf.comp_swap = 1; /* ARGB */
 
-    evergreen_set_spi(radeon, 0, 0);
+	}
+	cb_conf.source_format = EXPORT_4C_16BPC;
+	cb_conf.blend_clamp = 1;
+	/* Render setup */
+	cb_conf.pmask |= 4; /* B */
+	cb_conf.pmask |= 2; /* G */
+	cb_conf.pmask |= 1; /* R */
+	cb_conf.pmask |= 8; /* A */
+	cb_conf.rop = 3;
+	if (accel_state->dst_obj.tiling_flags == 0) {
+		cb_conf.array_mode = 1;
+		cb_conf.non_disp_tiling = 1;
+	}
+	evergreen_set_render_target(radeon, &cb_conf, accel_state->dst_obj.domain);
+	
+	evergreen_set_spi(radeon, 0, 0);
 
     /* PS alu constants */
     ps_const_conf.size_bytes = 256;
@@ -127,6 +126,12 @@ void do_solid_fill_prepare(struct radeon *radeon, struct r600_accel_object *obj,
 	ps_alu_consts[1] = (float)g / 255; /* G */
 	ps_alu_consts[2] = (float)b / 255; /* B */
 	ps_alu_consts[3] = (float)a / 255; /* A */
+	{
+    uint32_t *dbg;
+    dbg = (uint32_t *)ps_alu_consts;
+	  fprintf(stderr,"dbg %x %x %x %x\n", dbg[0],
+		  dbg[1], dbg[2], dbg[3]);
+	}
     }
     radeon_vbo_commit(radeon, &accel_state->cbuf);
     evergreen_set_alu_consts(radeon, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
@@ -137,6 +142,7 @@ void evergreen_solid(struct radeon *radeon,
 {
 	struct radeon_accel_state *accel_state = &radeon->accel_state;
 	float *vb;
+	uint32_t *vb_i;
 	vb = radeon_vbo_space(radeon, &accel_state->vbo, 8);
 
 	vb[0] = (float)x1;
@@ -148,6 +154,11 @@ void evergreen_solid(struct radeon *radeon,
 	vb[4] = (float)x2;
 	vb[5] = (float)y2;
 
+    {
+	    vb_i = (uint32_t *)vb;
+      fprintf(stderr,"solid %d %d %d %d %x %x %x %x %x %x\n", x1, y1, x2, y2, vb_i[0],
+	      vb_i[1], vb_i[2], vb_i[3], vb_i[4], vb_i[5]);
+    }
 	radeon_vbo_commit(radeon, &accel_state->vbo);
 }
 
diff --git a/radeondemo.c b/radeondemo.c
index 7c41490..6af62a5 100644
--- a/radeondemo.c
+++ b/radeondemo.c
@@ -18,26 +18,40 @@ struct radeon *radeon = &_radeon_ctx;
 
 int run_test(struct radeon *radeon)
 {
-	struct r600_accel_object test1;
-	int size;
+	struct r600_accel_object test1 = {0};
+	int size, i;
 	struct radeon_bo *vram_bo, *gtt_bo;
 
-	test1.pitch = 256;
-	test1.width = 256;
-	test1.height = 256;
+	test1.pitch = 1408;
+	test1.width = 1366;
+	test1.height = 768;
 	test1.bpp = 32;
 	test1.domain = RADEON_GEM_DOMAIN_VRAM;
 	test1.tiling_flags = 0;
 
-	size = test1.pitch*test1.height*test1.bpp;
+	size = test1.pitch*test1.height*(test1.bpp / 8);
 	test1.bo = radeon_bo_open(radeon->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 	if (!test1.bo)
 		return -1;
 
-	do_solid_fill_prepare(radeon, &test1, 0xaa55aa55);
+	do_solid_fill_prepare(radeon, &test1, 0xffff0000);
 	evergreen_solid(radeon, 0, 0, test1.width, test1.height);
 	evergreen_finish_op(radeon, 8);
-	
+
+	radeon_cs_flush_indirect(radeon);
+
+	radeon_bo_map(test1.bo, 0);
+
+	{
+		uint32_t *data = test1.bo->ptr;
+		for (i = 0; i < 32; i++) {
+			fprintf(stderr,"%08x ", data[i]);
+		}
+		fprintf(stderr,"\n");
+
+//		fprintf(stderr,"bo1 %08x %08x\n", data[0], data[1]);
+	}
+	radeon_bo_unmap(test1.bo);
 }
 
 int radeon_init(struct radeon *radeon, int fd)
@@ -107,6 +121,7 @@ int main(int argc, char **argv)
 	int drmFD;
 	int ret;
 	char *pciids = "pci:0000:00:01.0";
+	drmSetVersion sv;
 	drmFD = drmOpen(NULL, pciids);
 	if (drmFD < 0) {
 		drmError(drmFD, __func__);
@@ -115,6 +130,17 @@ int main(int argc, char **argv)
 		exit(-1);
 	}
 
+	sv.drm_di_major = 1;
+	sv.drm_di_minor = 1;
+	sv.drm_dd_major = -1;
+	sv.drm_dd_minor = -1;
+	ret = drmSetInterfaceVersion(drmFD, &sv);
+	if (ret != 0){
+		drmClose(drmFD);
+		return -1;
+	}
+	
+
 	ret = radeon_init(radeon, drmFD);
 	if (ret < 0) {
 		fprintf(stderr,"uanbel to init radeon\n");
@@ -129,13 +155,18 @@ int main(int argc, char **argv)
 
 void ErrorF(const char *f, ...)
 {
+	va_list args;
 
+	va_start(args, f);
+	vfprintf(stderr, f, args);
+	va_end(args);
 }
 
 void radeon_cs_flush_indirect(struct radeon *radeon)
 {
     struct radeon_accel_state *accel_state = &radeon->accel_state;
     int ret;
+    int i;
 
     if (!radeon->cs->cdw)
         return;
@@ -151,7 +182,12 @@ void radeon_cs_flush_indirect(struct radeon *radeon)
         radeon_vbo_put(radeon, &accel_state->cbuf);
         accel_state->cbuf.vb_start_op = -1;
     }
-   radeon_cs_emit(radeon->cs);
+
+    for (i = 0; i < radeon->cs->cdw; i++)
+	    fprintf(stderr,"%d: %08x\n", i, radeon->cs->packets[i]);
+
+
+    radeon_cs_emit(radeon->cs);
     radeon_cs_erase(radeon->cs);
 
     radeon_vbo_flush_bos(radeon);
@@ -171,7 +207,7 @@ void radeon_ddx_cs_start(struct radeon *radeon,
                          const char *func, int line)
 {
     if (radeon->cs->cdw + n > radeon->cs->ndw) {
-//        radeon_cs_flush_indirect(radeon);
+         radeon_cs_flush_indirect(radeon);
 
     }
     radeon_cs_begin(radeon->cs, n, file, func, line);
diff --git a/radeondemo.h b/radeondemo.h
index b23c58e..dbe00aa 100644
--- a/radeondemo.h
+++ b/radeondemo.h
@@ -14,6 +14,7 @@
 
 #include "radeon_bo.h"
 #include "radeon_cs.h"
+
 struct radeon_vbo_object {
 	struct radeon_bo *vb_bo;
 	unsigned verts_per_op;
@@ -48,27 +49,28 @@ struct r600_accel_object {
 struct radeon;
 
 struct radeon_accel_state {
-    bool              XInited3D; /* X itself has the 3D context */
+	bool              XInited3D; /* X itself has the 3D context */
 	struct radeon_vbo_object vbo;
 	struct radeon_vbo_object cbuf;
-    uint32_t          ib_reset_op;
+	uint32_t          ib_reset_op;
 	uint32_t          src_size[2];
 	uint32_t          dst_size;
-    struct r600_accel_object src_obj[2];
-    struct r600_accel_object dst_obj;
-
-    struct radeon_dma_bo bo_free;
-    struct radeon_dma_bo bo_wait;
-    struct radeon_dma_bo bo_reserved;
-
-    void (*finish_op)(struct radeon *, int);
-  
-    struct radeon_bo  *shaders_bo;
-    uint32_t          solid_vs_offset;
-    uint32_t          solid_ps_offset;
-    uint32_t          copy_vs_offset;
-    uint32_t          copy_ps_offset;
+	struct r600_accel_object src_obj[2];
+	struct r600_accel_object dst_obj;
+	
+	struct radeon_dma_bo bo_free;
+	struct radeon_dma_bo bo_wait;
+	struct radeon_dma_bo bo_reserved;
+	
+	void (*finish_op)(struct radeon *, int);
+	
+	struct radeon_bo  *shaders_bo;
+	uint32_t          solid_vs_offset;
+	uint32_t          solid_ps_offset;
+	uint32_t          copy_vs_offset;
+	uint32_t          copy_ps_offset;
 };
+
 typedef enum {
     CHIP_FAMILY_UNKNOW,
     CHIP_FAMILY_LEGACY,
@@ -187,12 +189,12 @@ extern void ErrorF(const char *f, ...);
 void radeon_ddx_cs_start(struct radeon *radeon,
                          int n, const char *file,
                          const char *func, int line);
+
 #define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
 #define CS_FULL(cs) ((cs)->cdw > 15 * 1024)
 
 #include "radeon_vbo.h"
 
-
 void radeon_cs_flush_indirect(struct radeon *radeon);
 int radeon_cp_start(struct radeon *radeon);
 bool EVERGREENAllocShaders(struct radeon *radeon);