drm/i915/display: move encoder power domains setup to encoders filedrm-intel-display-refactor

3 files changed, 25 insertions, 24 deletions

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 710c1b80e291..a4b5a851c5c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9667,29 +9667,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	}
 }
 
-static void
-get_encoder_power_domains(struct drm_i915_private *dev_priv)
-{
-	struct intel_encoder *encoder;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
-		struct intel_crtc_state *crtc_state;
-
-		if (!encoder->get_power_domains)
-			continue;
-
-		/*
-		 * MST-primary and inactive encoders don't have a crtc state
-		 * and neither of these require any power domain references.
-		 */
-		if (!encoder->base.crtc)
-			continue;
-
-		crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
-		encoder->get_power_domains(encoder, crtc_state);
-	}
-}
-
 static void intel_early_display_was(struct drm_i915_private *dev_priv)
 {
 	/*
@@ -9797,7 +9774,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 	intel_modeset_readout_hw_state(dev);
 
 	/* HW state is read out, now we need to sanitize this mess. */
-	get_encoder_power_domains(dev_priv);
+	intel_encoders_get_power_domains(dev_priv);
 
 	if (HAS_PCH_IBX(dev_priv))
 		ibx_sanitize_pch_ports(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_encoder.c b/drivers/gpu/drm/i915/display/intel_encoder.c
index 2c6e5dd24e54..264a7c9cc5f7 100644
--- a/drivers/gpu/drm/i915/display/intel_encoder.c
+++ b/drivers/gpu/drm/i915/display/intel_encoder.c
@@ -496,3 +496,25 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
 
 	return mode;
 }
+
+void intel_encoders_get_power_domains(struct drm_i915_private *dev_priv)
+{
+	struct intel_encoder *encoder;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder) {
+		struct intel_crtc_state *crtc_state;
+
+		if (!encoder->get_power_domains)
+			continue;
+
+		/*
+		 * MST-primary and inactive encoders don't have a crtc state
+		 * and neither of these require any power domain references.
+		 */
+		if (!encoder->base.crtc)
+			continue;
+
+		crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
+		encoder->get_power_domains(encoder, crtc_state);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_encoder.h b/drivers/gpu/drm/i915/display/intel_encoder.h
index 125361d41499..f71817b55880 100644
--- a/drivers/gpu/drm/i915/display/intel_encoder.h
+++ b/drivers/gpu/drm/i915/display/intel_encoder.h
@@ -47,4 +47,6 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
 
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
+
+void intel_encoders_get_power_domains(struct drm_i915_private *dev_priv);
 #endif