diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-17 13:25:04 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-17 13:25:04 +0200 |
| commit | 48ec7f9edd7a1bfe01a158a2a3ba85667f29030f (patch) | |
| tree | 6b3bbd5d1da63cad8f5fd264354e33d6ea474f92 | |
| parent | b38188ad97571f9145407e9bf3bd6a32a51ce87d (diff) | |
tests/gem_set_tiling_vs_blt: fix on gen4+
Oops, the new checks need correctly tiled blts to work.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | tests/gem_set_tiling_vs_blt.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/tests/gem_set_tiling_vs_blt.c b/tests/gem_set_tiling_vs_blt.c index 77f592f9..5fa90d49 100644 --- a/tests/gem_set_tiling_vs_blt.c +++ b/tests/gem_set_tiling_vs_blt.c @@ -79,6 +79,7 @@ static void do_test(uint32_t tiling, unsigned stride, int i, ret; uint32_t *ptr; uint32_t test_bo_handle; + uint32_t blt_stride, blt_bits; bool tiling_changed = false; printf("filling ring .. "); @@ -151,9 +152,17 @@ static void do_test(uint32_t tiling, unsigned stride, drm_intel_gem_bo_unmap_gtt(test_bo); } + blt_stride = stride; + blt_bits = 0; + if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) { + blt_stride /= 4; + blt_bits = XY_SRC_COPY_BLT_SRC_TILED; + } + BEGIN_BATCH(8); OUT_BATCH(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | + blt_bits | XY_SRC_COPY_BLT_WRITE_RGB); OUT_BATCH((3 << 24) | /* 32 bits */ (0xcc << 16) | /* copy ROP */ @@ -162,7 +171,7 @@ static void do_test(uint32_t tiling, unsigned stride, OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride))); OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(0 << 16 | 0); - OUT_BATCH(stride); + OUT_BATCH(blt_stride); OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0); ADVANCE_BATCH(); intel_batchbuffer_flush(batch); |