diff options
Diffstat (limited to 'include/drm/amdgpu_drm.h')
| -rw-r--r-- | include/drm/amdgpu_drm.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index d8f24976..fa0bfe22 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -50,6 +50,7 @@ extern "C" { #define DRM_AMDGPU_WAIT_CS 0x09 #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 +#define DRM_AMDGPU_SEM 0x13 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -63,6 +64,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -303,6 +305,26 @@ union drm_amdgpu_wait_cs { struct drm_amdgpu_wait_cs_out out; }; +#define AMDGPU_SEM_OP_CREATE_SEM 0 +#define AMDGPU_SEM_OP_IMPORT_SEM 1 +#define AMDGPU_SEM_OP_EXPORT_SEM 2 +#define AMDGPU_SEM_OP_DESTROY_SEM 3 + +struct drm_amdgpu_sem_in { + __u32 op; + __u32 handle; +}; + +struct drm_amdgpu_sem_out { + __u32 fd; + __u32 handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + struct drm_amdgpu_sem_out out; +}; + #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 @@ -358,6 +380,8 @@ struct drm_amdgpu_gem_va { #define AMDGPU_CHUNK_ID_IB 0x01 #define AMDGPU_CHUNK_ID_FENCE 0x02 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 +#define AMDGPU_CHUNK_ID_SEM_WAIT 0x04 +#define AMDGPU_CHUNK_ID_SEM_SIGNAL 0x05 struct drm_amdgpu_cs_chunk { uint32_t chunk_id; @@ -422,6 +446,10 @@ struct drm_amdgpu_cs_chunk_fence { uint32_t offset; }; +struct drm_amdgpu_cs_chunk_sem { + uint32_t handle; +}; + struct drm_amdgpu_cs_chunk_data { union { struct drm_amdgpu_cs_chunk_ib ib_data; |