diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-22 16:07:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-10-22 16:07:58 -0400 |
| commit | e57b54daf318ff59315a1c9ed21934f288c5c782 (patch) | |
| tree | d1556b102dae4310d202d03c164ec2fb2a0bb517 | |
| parent | 4cf06dfba617529291ce4b4c306c4fc1bba110ee (diff) | |
R7xx: program additional CUR/GRPH regs for 40 bit addresses
The *_HIGH regs are reversed. The secondary ones are in the
primary block and vice versa.
| -rw-r--r-- | src/atombios_crtc.c | 9 | ||||
| -rw-r--r-- | src/radeon_cursor.c | 6 | ||||
| -rw-r--r-- | src/radeon_reg.h | 10 |
3 files changed, 25 insertions, 0 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 62402a7..d513c13 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -536,6 +536,15 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; } + if (info->ChipFamily >= CHIP_FAMILY_RV770) { + if (radeon_crtc->crtc_id) { + OUTREG(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); + } else { + OUTREG(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); + OUTREG(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); + } + } OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c index 5ecdfad..cf5e9a0 100644 --- a/src/radeon_cursor.c +++ b/src/radeon_cursor.c @@ -106,6 +106,12 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); if (enable) { + if (info->ChipFamily >= CHIP_FAMILY_RV770) { + if (radeon_crtc->crtc_id) + OUTREG(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); + else + OUTREG(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0); + } OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset); OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 5467286..e656f5f 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3669,8 +3669,16 @@ # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) +/* the *_HIGH surface regs are backwards; the D1 regs are in the D2 + * block and vice versa. This applies to GRPH, CUR, etc. + */ + #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 +#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c +#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c #define AVIVO_D1GRPH_PITCH 0x6120 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 @@ -3690,6 +3698,8 @@ # define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) # define AVIVO_D1CURSOR_MODE_24BPP (0x2) #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 +#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c +#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 |