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authorAlex Deucher <alexdeucher@gmail.com>2009-10-27 11:18:44 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-10-27 11:18:44 -0400
commit2a6eeec72d6bb04a32225883f431c1d2e8cff123 (patch)
treef043b567840de020901e5c7ff15405fdb4c4a3c4
parentf0d9d80fee4176eaba9435a9539f29d0eefe2a87 (diff)
atom: loosen pll min output limits
Limiting the pll output range is a good thing generally as it limits the number of possible pll combinations for a given frequency presumably to the ones that work best on each card. That's why the limits are in the bios tables. However, certain duallink DVI monitors seem to like pll combinations that would be limited by this at least on pre-DCE 3.0 r6xx hardware. This might need to be adjusted per family or per clock range in the future. Fixes fdo bug 24727. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
-rw-r--r--src/radeon_atombios.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index a8eded6..1f4b9dc 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -2171,6 +2171,15 @@ RADEONGetATOMClockInfo(ScrnInfoPtr pScrn)
if (pll->pll_out_min == 0)
pll->pll_out_min = 64800;
+ /* limiting the range is a good thing in most cases
+ * as it limits the number of matching pll combinations,
+ * however, some duallink DVI monitors seem to prefer combinations that
+ * would be limited by this. This may need to be revisited
+ * per chip family.
+ */
+ if (pll->pll_out_min > 64800)
+ pll->pll_out_min = 64800;
+
return TRUE;
}