evergreen: use vbo code for constant buffersevergreen_accel

6 files changed, 129 insertions, 147 deletions

diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 31e460d..1b40aca 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -1062,6 +1062,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
 	radeon_ib_discard(pScrn);
 	radeon_cs_flush_indirect(pScrn);
 	radeon_vb_discard(pScrn, &accel_state->vbo);
+	radeon_vb_discard(pScrn, &accel_state->cbuf);
 	return;
     }
 
@@ -1093,6 +1094,7 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
 				  accel_state->dst_obj.bo, 0, accel_state->dst_obj.domain);
 
     accel_state->vbo.vb_start_op = -1;
+    accel_state->cbuf.vb_start_op = -1;
     accel_state->ib_reset_op = 0;
 
 }
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 434516b..8838a11 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -158,7 +158,6 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     cb_config_t     cb_conf;
     shader_config_t vs_conf, ps_conf;
     int pmask = 0;
-    int ret;
     uint32_t a, r, g, b;
     float *ps_alu_consts;
     const_config_t ps_const_conf;
@@ -193,53 +192,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     CLEAR (ps_conf);
     CLEAR (ps_const_conf);
 
-    ps_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (ps_const_conf.bo == NULL)
-	RADEON_FALLBACK(("ps const buffer alloc failed\n"));
-    ret = radeon_bo_map(ps_const_conf.bo, 0);
-    if (ret)
-	RADEON_FALLBACK(("ps const buffer map failed\n"));
-
-    /* PS alu constants */
-    ps_const_conf.size_bytes = 256;
-    ps_const_conf.const_addr = 0;
-    ps_const_conf.type = SHADER_TYPE_PS;
-    ps_alu_consts = (float *)ps_const_conf.bo->ptr;
-    if (accel_state->dst_obj.bpp == 16) {
-	r = (fg >> 11) & 0x1f;
-	g = (fg >> 5) & 0x3f;
-	b = (fg >> 0) & 0x1f;
-	ps_alu_consts[0] = (float)r / 31; /* R */
-	ps_alu_consts[1] = (float)g / 63; /* G */
-	ps_alu_consts[2] = (float)b / 31; /* B */
-	ps_alu_consts[3] = 1.0; /* A */
-    } else if (accel_state->dst_obj.bpp == 8) {
-	a = (fg >> 0) & 0xff;
-	ps_alu_consts[0] = 0.0; /* R */
-	ps_alu_consts[1] = 0.0; /* G */
-	ps_alu_consts[2] = 0.0; /* B */
-	ps_alu_consts[3] = (float)a / 255; /* A */
-    } else {
-	a = (fg >> 24) & 0xff;
-	r = (fg >> 16) & 0xff;
-	g = (fg >> 8) & 0xff;
-	b = (fg >> 0) & 0xff;
-	ps_alu_consts[0] = (float)r / 255; /* R */
-	ps_alu_consts[1] = (float)g / 255; /* G */
-	ps_alu_consts[2] = (float)b / 255; /* B */
-	ps_alu_consts[3] = (float)a / 255; /* A */
-    }
-    radeon_bo_unmap(ps_const_conf.bo);
-
-    radeon_cs_space_add_persistent_bo(info->cs, ps_const_conf.bo,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (radeon_cs_space_check(info->cs)) {
-	radeon_bo_unref(ps_const_conf.bo);
-	RADEON_FALLBACK(("ps const buffer size check failed\n"));
-    }
-
     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
+    radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
     radeon_cp_start(pScrn);
 
     evergreen_set_default_state(pScrn);
@@ -320,6 +274,39 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     E32(FLAT_SHADE_ENA_bit); // SPI_INTERP_CONTROL_0
     END_BATCH();
 
+
+    /* PS alu constants */
+    ps_const_conf.size_bytes = 256;
+    ps_const_conf.type = SHADER_TYPE_PS;
+    ps_const_conf.bo = accel_state->cbuf.vb_bo;
+    ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+    if (accel_state->dst_obj.bpp == 16) {
+	r = (fg >> 11) & 0x1f;
+	g = (fg >> 5) & 0x3f;
+	b = (fg >> 0) & 0x1f;
+	ps_alu_consts[0] = (float)r / 31; /* R */
+	ps_alu_consts[1] = (float)g / 63; /* G */
+	ps_alu_consts[2] = (float)b / 31; /* B */
+	ps_alu_consts[3] = 1.0; /* A */
+    } else if (accel_state->dst_obj.bpp == 8) {
+	a = (fg >> 0) & 0xff;
+	ps_alu_consts[0] = 0.0; /* R */
+	ps_alu_consts[1] = 0.0; /* G */
+	ps_alu_consts[2] = 0.0; /* B */
+	ps_alu_consts[3] = (float)a / 255; /* A */
+    } else {
+	a = (fg >> 24) & 0xff;
+	r = (fg >> 16) & 0xff;
+	g = (fg >> 8) & 0xff;
+	b = (fg >> 0) & 0xff;
+	ps_alu_consts[0] = (float)r / 255; /* R */
+	ps_alu_consts[1] = (float)g / 255; /* G */
+	ps_alu_consts[2] = (float)b / 255; /* B */
+	ps_alu_consts[3] = (float)a / 255; /* A */
+    }
+    radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+    ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
     evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
 
     if (accel_state->vsync)
@@ -1208,7 +1195,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     shader_config_t vs_conf, ps_conf;
     const_config_t vs_const_conf;
     struct r600_accel_object src_obj, mask_obj, dst_obj;
-    int ret;
+    float *cbuf;
 
     //return FALSE;
 
@@ -1284,37 +1271,13 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     CLEAR (ps_conf);
     CLEAR (vs_const_conf);
 
-    vs_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (vs_const_conf.bo == NULL)
-	RADEON_FALLBACK(("vs const buffer alloc failed\n"));
-    ret = radeon_bo_map(vs_const_conf.bo, 0);
-    if (ret)
-	RADEON_FALLBACK(("vs const buffer map failed\n"));
-
-    /* VS alu constants */
-    vs_const_conf.size_bytes = 256;
-    vs_const_conf.const_addr = 0;
-    vs_const_conf.type = SHADER_TYPE_VS;
-
-    EVERGREENXFormSetup(pSrcPicture, pSrc, 0, (float *)vs_const_conf.bo->ptr);
-    if (pMask)
-        EVERGREENXFormSetup(pMaskPicture, pMask, 1, (float *)vs_const_conf.bo->ptr);
-
-    radeon_bo_unmap(vs_const_conf.bo);
-
-    radeon_cs_space_add_persistent_bo(info->cs, vs_const_conf.bo,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (radeon_cs_space_check(info->cs)) {
-	radeon_bo_unref(vs_const_conf.bo);
-	RADEON_FALLBACK(("vs const buffer size check failed\n"));
-    }
-
     if (pMask)
         radeon_vbo_check(pScrn, &accel_state->vbo, 24);
     else
         radeon_vbo_check(pScrn, &accel_state->vbo, 16);
 
+    radeon_vbo_check(pScrn, &accel_state->cbuf, 256);
+
     radeon_cp_start(pScrn);
 
     evergreen_set_default_state(pScrn);
@@ -1327,6 +1290,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
         radeon_ib_discard(pScrn);
         radeon_cs_flush_indirect(pScrn);
         radeon_vb_discard(pScrn, &accel_state->vbo);
+        radeon_vb_discard(pScrn, &accel_state->cbuf);
         return FALSE;
     }
 
@@ -1335,6 +1299,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
 	    radeon_ib_discard(pScrn);
 	    radeon_cs_flush_indirect(pScrn);
             radeon_vb_discard(pScrn, &accel_state->vbo);
+            radeon_vb_discard(pScrn, &accel_state->cbuf);
             return FALSE;
         }
     } else
@@ -1446,6 +1411,21 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     END_BATCH();
 
     /* VS alu constants */
+    vs_const_conf.size_bytes = 256;
+    vs_const_conf.const_addr = 0;
+    vs_const_conf.type = SHADER_TYPE_VS;
+    vs_const_conf.bo = accel_state->cbuf.vb_bo;
+
+    cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+    EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf);
+    if (pMask)
+        EVERGREENXFormSetup(pMaskPicture, pMask, 1, cbuf);
+
+    radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+    /* VS alu constants */
+    vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
     evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
 
     if (accel_state->vsync)
@@ -1907,8 +1887,10 @@ EVERGREENDrawInit(ScreenPtr pScreen)
     info->accel_state->dst_obj.bo = NULL;
     info->accel_state->copy_area_bo = NULL;
     info->accel_state->vbo.vb_start_op = -1;
+    info->accel_state->cbuf.vb_start_op = -1;
     info->accel_state->finish_op = evergreen_finish_op;
     info->accel_state->vbo.verts_per_op = 3;
+    info->accel_state->cbuf.verts_per_op = 1;
     RADEONVlineHelperClear(pScrn);
 
     radeon_vbo_init_lists(pScrn);
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 6a2041b..3905b5a 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -111,7 +111,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     const_config_t ps_const_conf;
     float *vs_alu_consts;
     const_config_t vs_const_conf;
-    int ret;
 
     cont = RTFContrast(pPriv->contrast);
     bright = RTFBrightness(pPriv->brightness);
@@ -153,75 +152,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     CLEAR (vs_const_conf);
     CLEAR (ps_const_conf);
 
-    /* setup the ps consts */
-    ps_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (ps_const_conf.bo == NULL) {
-	ErrorF("ps const buffer alloc failed\n");
-	return;
-    }
-    ret = radeon_bo_map(ps_const_conf.bo, 0);
-    if (ret) {
-	ErrorF("ps const buffer map failed\n");
-	return;
-    }
-
-    /* PS alu constants */
-    ps_const_conf.size_bytes = 256;
-    ps_const_conf.const_addr = 0;
-    ps_const_conf.type = SHADER_TYPE_PS;
-    ps_alu_consts = (float *)ps_const_conf.bo->ptr;
-
-    ps_alu_consts[0] = off[0];
-    ps_alu_consts[1] = off[1];
-    ps_alu_consts[2] = off[2];
-    ps_alu_consts[3] = yco;
-
-    ps_alu_consts[4] = uco[0];
-    ps_alu_consts[5] = uco[1];
-    ps_alu_consts[6] = uco[2];
-    ps_alu_consts[7] = gamma;
-
-    ps_alu_consts[8] = vco[0];
-    ps_alu_consts[9] = vco[1];
-    ps_alu_consts[10] = vco[2];
-    ps_alu_consts[11] = 0.0;
-    radeon_bo_unmap(ps_const_conf.bo);
-
-    vs_const_conf.bo = radeon_bo_open(info->bufmgr, 0, 256, 0,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (vs_const_conf.bo == NULL) {
-	ErrorF("vs const buffer alloc failed\n");
-	return;
-    }
-    ret = radeon_bo_map(vs_const_conf.bo, 0);
-    if (ret) {
-	ErrorF("vs const buffer map failed\n");
-	return;
-    }
-
-    /* PS alu constants */
-    vs_const_conf.size_bytes = 256;
-    vs_const_conf.const_addr = 0;
-    vs_const_conf.type = SHADER_TYPE_VS;
-    vs_alu_consts = (float *)vs_const_conf.bo->ptr;
-    vs_alu_consts[0] = 1.0 / pPriv->w;
-    vs_alu_consts[1] = 1.0 / pPriv->h;
-    vs_alu_consts[2] = 0.0;
-    vs_alu_consts[3] = 0.0;
-    radeon_bo_unmap(vs_const_conf.bo);
-
-    radeon_cs_space_add_persistent_bo(info->cs, ps_const_conf.bo,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    radeon_cs_space_add_persistent_bo(info->cs, vs_const_conf.bo,
-				      RADEON_GEM_DOMAIN_GTT, 0);
-    if (radeon_cs_space_check(info->cs)) {
-	radeon_bo_unref(ps_const_conf.bo);
-	radeon_bo_unref(vs_const_conf.bo);
-	ErrorF("const buffer size check failed\n");
-	return;
-    }
-
 #if defined(XF86DRM_MODE)
     if (info->cs) {
 	dst_obj.offset = 0;
@@ -265,6 +195,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 #endif
 
     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
+    radeon_vbo_check(pScrn, &accel_state->cbuf, 512);
     radeon_cp_start(pScrn);
 
     evergreen_set_default_state(pScrn);
@@ -303,9 +234,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     ps_conf.bo                  = accel_state->shaders_bo;
     evergreen_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM);
 
-    /* PS alu constants */
-    evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
-
     /* Texture */
     switch(pPriv->id) {
     case FOURCC_YV12:
@@ -518,7 +446,51 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     E32(0); // SPI_INTERP_CONTROL_0
     END_BATCH();
 
+    /* PS alu constants */
+    ps_const_conf.size_bytes = 256;
+    ps_const_conf.const_addr = 0;
+    ps_const_conf.type = SHADER_TYPE_PS;
+    vs_const_conf.bo = accel_state->cbuf.vb_bo;
+    ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+    ps_alu_consts[0] = off[0];
+    ps_alu_consts[1] = off[1];
+    ps_alu_consts[2] = off[2];
+    ps_alu_consts[3] = yco;
+
+    ps_alu_consts[4] = uco[0];
+    ps_alu_consts[5] = uco[1];
+    ps_alu_consts[6] = uco[2];
+    ps_alu_consts[7] = gamma;
+
+    ps_alu_consts[8] = vco[0];
+    ps_alu_consts[9] = vco[1];
+    ps_alu_consts[10] = vco[2];
+    ps_alu_consts[11] = 0.0;
+
+    radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
+    /* PS alu constants */
+    ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
+    evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
+
+    /* VS alu constants */
+    vs_const_conf.size_bytes = 256;
+    vs_const_conf.const_addr = 0;
+    vs_const_conf.type = SHADER_TYPE_VS;
+    vs_const_conf.bo = accel_state->cbuf.vb_bo;
+    ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+
+    vs_alu_consts = (float *)vs_const_conf.bo->ptr;
+    vs_alu_consts[0] = 1.0 / pPriv->w;
+    vs_alu_consts[1] = 1.0 / pPriv->h;
+    vs_alu_consts[2] = 0.0;
+    vs_alu_consts[3] = 0.0;
+
+    radeon_vbo_commit(pScrn, &accel_state->cbuf);
+
     /* VS alu constants */
+    vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_start_op;
     evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
 
     if (pPriv->vsync) {
diff --git a/src/radeon.h b/src/radeon.h
index a6a9dd2..e85d941 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -740,6 +740,7 @@ struct radeon_accel_state {
     drmBufPtr         ib;
 
     struct radeon_vbo_object vbo;
+    struct radeon_vbo_object cbuf;
 
     /* where to discard IB from if we cancel operation */
     uint32_t          ib_reset_op;
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
index 9aa4f39..2ef0751 100644
--- a/src/radeon_exa_shared.c
+++ b/src/radeon_exa_shared.c
@@ -166,6 +166,7 @@ int radeon_cp_start(ScrnInfoPtr pScrn)
 	}
     }
     accel_state->vbo.vb_start_op = accel_state->vbo.vb_offset;
+    accel_state->cbuf.vb_start_op = accel_state->cbuf.vb_offset;
     return 0;
 }
 
@@ -214,6 +215,8 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
 
     info->accel_state->vbo.vb_offset = 0;
     info->accel_state->vbo.vb_start_op = -1;
+    info->accel_state->cbuf.vb_offset = 0;
+    info->accel_state->cbuf.vb_start_op = -1;
 
     if (CS_FULL(info->cs)) {
 	radeon_cs_flush_indirect(pScrn);
@@ -226,6 +229,14 @@ void radeon_ib_discard(ScrnInfoPtr pScrn)
     if (ret)
 	ErrorF("space check failed in flush\n");
 
+    if (info->accel_state->cbuf.vb_bo) {
+	ret = radeon_cs_space_check_with_bo(info->cs,
+					    info->accel_state->cbuf.vb_bo,
+					    RADEON_GEM_DOMAIN_GTT, 0);
+	if (ret)
+	    ErrorF("space check failed in flush\n");
+    }
+
  out:
     if (info->dri2.enabled) {
 	info->accel_state->XInited3D = FALSE;
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index c372661..deecdc9 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -88,6 +88,12 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
         info->accel_state->vbo.vb_start_op = -1;
     }
 
+    /* release the current VBO so we don't block on mapping it later */
+    if (info->accel_state->cbuf.vb_offset && info->accel_state->cbuf.vb_bo) {
+        radeon_vbo_put(pScrn, &info->accel_state->cbuf);
+        info->accel_state->cbuf.vb_start_op = -1;
+    }
+
     radeon_cs_emit(info->cs);
     radeon_cs_erase(info->cs);
 
@@ -100,6 +106,14 @@ void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
     if (ret)
       ErrorF("space check failed in flush\n");
 
+    if (accel_state->cbuf.vb_bo) {
+	ret = radeon_cs_space_check_with_bo(info->cs,
+					    accel_state->cbuf.vb_bo,
+					    RADEON_GEM_DOMAIN_GTT, 0);
+	if (ret)
+	    ErrorF("space check failed in flush\n");
+    }
+
     if (info->reemit_current2d && info->state_2d.op)
         info->reemit_current2d(pScrn, info->state_2d.op);