diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2020-07-24 11:41:31 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-24 14:01:55 -0400 |
| commit | 4189f4d14c112b735e58dfed6a3c15b41539faad (patch) | |
| tree | dc9dd28c89100429348974ed125e463547f69127 | |
| parent | c9729841333aebf3f3e6895f499a274d644531b4 (diff) | |
drm/amdgpu/display: Fix up PLL handling for DCE6si_dc_support
DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 261333afc936..5a5a9cb77acb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -379,7 +379,7 @@ static const struct resource_caps res_cap_61 = { .num_timing_generator = 4, .num_audio = 6, .num_stream_encoder = 6, - .num_pll = 2, + .num_pll = 3, .num_ddc = 6, }; @@ -983,9 +983,7 @@ static bool dce60_construct( dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); pool->base.clock_sources[1] = dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); - pool->base.clock_sources[2] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); - pool->base.clk_src_count = 3; + pool->base.clk_src_count = 2; } else { pool->base.dp_clock_source = @@ -993,9 +991,7 @@ static bool dce60_construct( pool->base.clock_sources[0] = dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); - pool->base.clock_sources[1] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); - pool->base.clk_src_count = 2; + pool->base.clk_src_count = 1; } if (pool->base.dp_clock_source == NULL) { |