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/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _MAIN_H
#define _MAIN_H
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#ifdef ANDROID
#include <androidio.h>
#else
#include <unistd.h> /* for libc5 */
#include <sys/io.h> /* for glibc */
#endif
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define CONFIG_CMD(bus,device_fn,where) \
(0x80000000|((bus&0xff) << 16)|((device_fn&0xff) << 8)|((where&0xff) & ~3))
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* form i915_drm.h */
#define SNB_GMCH_CTRL 0x50
#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
#define SNB_GMCH_GGMS_MASK 0x3
#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
#define SNB_GMCH_GMS_MASK 0x1f
#define BDW_GMCH_GGMS_SHIFT 6
#define BDW_GMCH_GGMS_MASK 0x3
#define BDW_GMCH_GMS_SHIFT 8
#define BDW_GMCH_GMS_MASK 0xff
#define PAGE_SIZE 4096
//#define PAGE_MASK ~(PAGE_SIZE - 1)
#define max(a,b) ((a)>(b)?(a):(b))
#define min(a,b) ((a)>(b)?(b):(a))
enum intel_ring_id {
RCS = 0x0,
VCS,
BCS,
VECS,
VCS2
};
#define FB_MMAP_MB 256
#define PCI_DEVFN(dev, fn) ((dev<<3)|fn)
/* Memory mapped register access macros */
#define INREG8(base,addr) *(volatile unsigned char *)(base + (addr))
#define INREG16(base,addr) *(volatile unsigned short *)(base + (addr))
#define INREG(base,addr) *(volatile unsigned int *)(base + (addr))
#define INREG_DISP(base,addr) *(volatile unsigned int *)(base + 0x180000 + (addr))
#define OUTREG8(base,addr, val) do { \
*(volatile unsigned char *)(base + (addr)) = (val); \
} while (0)
#define OUTREG16(base,addr, val) do { \
*(volatile unsigned short *)(base + (addr)) = (val); \
} while (0)
#define OUTREG(base,addr, val) do { \
*(volatile unsigned int *)(base + (addr)) = (val); \
} while (0)
#define PSB_WVDC32(_val, _offs) \
OUTREG(linear_mmio+PSB_VDC_OFFSET, _offs, _val)
#define PSB_RVDC32(_offs) \
INREG(linear_mmio+PSB_VDC_OFFSET, (_offs))
#define CHECK_STRICT_DEVMEM \
do { \
if (devmem_strict) { \
fprintf(stderr, "CONFIG_STRICT_DEVMEM forbids RAM dump, return\n"); \
return 1; \
} \
} while (0)
extern int devmem_fd;
extern int devmem_strict;
extern unsigned short devid, is_gen7, is_gen8;
extern uint32_t phy_mmio,phy_gtt,phy_fb, stolen_base;
extern unsigned char *linear_mmio,*linear_gtt,*linear_fb;/* linear mmio,fb,gtt */
extern unsigned int stolen_size, gtt_size, gtt_mapable_size;;
extern int verbose;
extern char *cmd_buf, *cmd_ptr,*cmd_end;
static inline uint32_t pci_get_long(int bus,int device_fn, int where)
{
outl(CONFIG_CMD(bus,device_fn,where), 0xCF8);
return inl(0xCFC);
}
static inline int pci_set_long(int bus,int device_fn, int where,uint32_t value)
{
outl(CONFIG_CMD(bus,device_fn,where), 0xCF8);
outl(value,0xCFC);
return 0;
}
static inline int pci_get_short(int bus,int device_fn, int where)
{
outl(CONFIG_CMD(bus,device_fn,where), 0xCF8);
return inw(0xCFC + (where&2));
}
static inline int pci_set_short(int bus,int device_fn, int where,unsigned short value)
{
outl(CONFIG_CMD(bus,device_fn,where), 0xCF8);
outw(value,0xCFC + (where&2));
return 0;
}
#define pci_write_config_dword(dev_fn, offset, value) pci_set_long(0,dev_fn<<3,offset, value)
#define pci_read_config_dword(dev_fn, offset, value) \
do { \
value = pci_get_long(0,dev_fn<<3,offset); \
} while (0)
#define pci_read_config_word(dev_fn, offset, value) \
do { \
value = pci_get_short(0,dev_fn<<3,offset); \
} while (0)
/**/
static inline unsigned int MSG_READ32(unsigned int port, unsigned int offset)
{
int mcr = (0x10 << 24) | (port << 16) | (offset << 8);
unsigned int ret_val = 0;
/* struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); */
unsigned int pci_root = 0;
pci_write_config_dword(pci_root, 0xD0, mcr);
pci_read_config_dword(pci_root, 0xD4, ret_val);
/* pci_dev_put(pci_root); */
return ret_val;
}
static inline void MSG_WRITE32(unsigned int port, unsigned int offset, unsigned int value)
{
int mcr = (0x11 << 24) | (port << 16) | (offset << 8) | 0xF0;
/* struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); */
unsigned int pci_root = 0;
pci_write_config_dword(pci_root, 0xD4, value);
pci_write_config_dword(pci_root, 0xD0, mcr);
/* pci_dev_put(pci_root); */
}
void print_bin_fmt(unsigned int value,int space);
int process_inl(char *cmdhdr,unsigned int reg);
int process_msgread(char *cmdhdr,unsigned int port,unsigned int reg);
int process_msgwrite(char *cmdhdr,unsigned int port, unsigned int reg, unsigned int new_value);
int process_regread(char *cmdhdr,unsigned int reg);
int process_regwrite(char *cmdhdr,unsigned int reg,unsigned int value);
int process_irq(char *cmdhdr,unsigned int seconds);
int process_estatus(char *cmdhdr,unsigned int value);
int process_cstatus(char *cmdhdr,unsigned int value);
int process_onscreen(char *cmdhdr);
int process_pipe(char *cmdhdr);
int process_plane(char *cmdhdr);
int process_port(char *cmdhdr);
int process_overlay(char *cmdhdr);
int process_fence(char *cmdhdr);
int process_dumpgtt(char *cmdhdr,unsigned int fb_mstart,unsigned int fb_msize);
int process_stolen(char *cmdhdr);
int process_dumpppgtt(char *cmdhdr,unsigned int ppgtt_pyaddr);
int process_fonscreen(char *cmdhdr,unsigned int value,
unsigned int size, unsigned int flag);
int process_fillfb(char *cmdhdr,unsigned int offset,
unsigned int size,unsigned int value);
int process_dumpfb(char *cmdhdr,unsigned int offset,
unsigned int size);
int process_fillfbl(char *cmdhdr,unsigned int offset,
unsigned int size,unsigned int value);
int process_dumpfbl(char *cmdhdr,unsigned int offset,
unsigned int size);
int process_dumpstat(char *cmdhdr,unsigned int stat_addr);
int process_dumpring(char *cmdhdr,unsigned int stat_addr, unsigned int head, unsigned int tail);
int get_ppgtt_page(uint32_t pd_phyaddr, uint32_t ppgtt_addr, unsigned char one_page[]);
uint32_t get_ring(unsigned int stat_addr);
uint32_t get_ppgtt(unsigned int stat_addr);
int forcewake_on();
int forcewake_off();
#endif
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