2D/3D: Fix Lockups on R5XX when running DRI clients with EXA/Textured Video.

Don't read out or set pipe parameters when engine is active.
Doing so might lock up the engine.
This fixes a long standing issue with 2D acceleration on R5xx.

3 files changed, 17 insertions, 38 deletions

diff --git a/src/r5xx_accel.c b/src/r5xx_accel.c
index d7b94e0..c9382cb 100644
--- a/src/r5xx_accel.c
+++ b/src/r5xx_accel.c
@@ -353,15 +353,12 @@ void
 R5xx2DStart(ScrnInfoPtr pScrn)
 {
     RHDPtr rhdPtr = RHDPTR(pScrn);
+    CARD32 pipe;
 
     RHDFUNC(pScrn);
 
-    if ((rhdPtr->ChipSet != RHD_RS690) &&
-	(rhdPtr->ChipSet != RHD_RS600) &&
-	(rhdPtr->ChipSet != RHD_RS740)) {
-	CARD8 pipe = (RHDRegRead(rhdPtr, R400_GB_PIPE_SELECT) >> 4) & 0xF0;
-	RHDWritePLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, pipe | 0x01);
-    }
+    pipe = (RHDRegRead(rhdPtr, R400_GB_PIPE_SELECT) >> 4) & 0xF0;
+    RHDWritePLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, pipe | 0x01);
 
     RHDRegMask(pScrn, R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING);
     RHDRegWrite(pScrn, R5XX_WAIT_UNTIL,
@@ -421,6 +418,15 @@ R5xx2DFBValid(RHDPtr rhdPtr, CARD16 Width, CARD16 Height, int bpp,
 }
 
 /*
+ * Map the number of GB Pipes the hardware has.
+ */
+static int
+R5xxGBPipesCount(ScrnInfoPtr pScrn)
+{
+    return ((RHDRegRead(pScrn, R400_GB_PIPE_SELECT) >> 12) & 0x03) + 1;
+}
+
+/*
  * Handlers for rhdPtr->ThreeDInfo.
  */
 void
@@ -438,6 +444,8 @@ R5xx3DInit(ScrnInfoPtr pScrn)
 
     R5xx3D = (struct R5xx3D *) xnfcalloc(1, sizeof(struct R5xx3D));
     R5xx3D->XHas3DEngineState = FALSE;
+    /* set this up here; not when the engine is running! */
+    R5xx3D->num_gb_pipes = R5xxGBPipesCount(pScrn);
     rhdPtr->ThreeDPrivate = R5xx3D;
 }
 
diff --git a/src/r5xx_accel.h b/src/r5xx_accel.h
index 3e642be..48189f7 100644
--- a/src/r5xx_accel.h
+++ b/src/r5xx_accel.h
@@ -90,6 +90,7 @@ struct R5xx3D {
     /* Size of tiles ... set to 65536x65536 if not tiling in that direction */
     Bool src_tile_width;
     Bool src_tile_height;
+    int num_gb_pipes;
 };
 
 void R5xx3DInit(ScrnInfoPtr pScrn);
diff --git a/src/radeon_3d.c b/src/radeon_3d.c
index 4fe0790..b3052e7 100644
--- a/src/radeon_3d.c
+++ b/src/radeon_3d.c
@@ -65,15 +65,7 @@
 
 # define HAS_TCL info->has_tcl
 
-# define R5XXPowerPipes(p) {}
-
-/* Map the number of GB Pipes the hardware has. */
-static int
-R5xxGBPipesCount(ScrnInfoPtr pScrn)
-{
-    return ((RHDRegRead(pScrn, R400_GB_PIPE_SELECT) >> 12) & 0x03) + 1;
-}
-#define NUM_GB_PIPES R5xxGBPipesCount(pScrn)
+#define NUM_GB_PIPES info->num_gb_pipes
 
 /* Map the number of FPUs the VPS has. */
 static int
@@ -165,13 +157,7 @@ R5xxPVSFPUCount(ScrnInfoPtr pScrn)
 
 #define HAS_TCL IS_R500_3D
 
-/* Map the number of GB Pipes the hardware has. */
-static int
-R5xxGBPipesCount(ScrnInfoPtr pScrn)
-{
-    return ((RHDRegRead(pScrn, R400_GB_PIPE_SELECT) >> 12) & 0x03) + 1;
-}
-#define NUM_GB_PIPES R5xxGBPipesCount(pScrn)
+#define NUM_GB_PIPES accel_state->num_gb_pipes
 
 /* Map the number of FPUs the VPS has. */
 static int
@@ -203,19 +189,6 @@ R5xxPVSFPUCount(ScrnInfoPtr pScrn)
 }
 #define NUM_PVS_FPUS R5xxPVSFPUCount(pScrn)
 
-/*
- *
- */
-static void
-R5XXPowerPipes(ScrnInfoPtr pScrn)
-{
-    CARD32 tmp = RHDRegRead(pScrn, R400_GB_PIPE_SELECT);
-    RHDWritePLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((tmp >> 8) & 0xf) << 4));
-}
-/* for radeon, this is done elsewhere, so use:
- * #define R5XXPowerPipes(x)
- */
-
 #endif /* IS_RADEON_DRIVER */
 
 #if defined(IS_RADEON_DRIVER) || defined(IS_QUICK_AND_DIRTY)
@@ -252,9 +225,6 @@ R5xx3DSetup(int scrnIndex)
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 	FINISH_ACCEL();
 
-	if (IS_R500_3D)
-	    R5XXPowerPipes(pScrn);
-
 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 
 	switch(num_gb_pipes) {