1 files changed, 9 insertions, 0 deletions

diff --git a/R600ToDo.mdwn b/R600ToDo.mdwn
index 3f86f6e..0febaae 100644
--- a/R600ToDo.mdwn
+++ b/R600ToDo.mdwn
@@ -44,6 +44,15 @@ And here is the R600g to do list; if you feel something is missing please add it
    * _Status:_ N/A 
    * _Description:_ 
    * One way to do this would be to stick assembly output into an ELF section, but I think the biggest challenge will be figuring out how to generate ISA and assembly together.
+* **Move FNEG/FABS/Immediate folding code to AMDGPUDAGToDAGISel::PostprocessISelDAG()
+   * _Difficulty:_ Medium 
+   * _Who's working on it:_ N/A 
+   * _Date Started:_ N/A 
+   * _Status:_ N/A 
+   * _Description:_ 
+   * R600 provides 2 inputs modifier to encode some operation: FNEG (on all ALU insts) and FABS (only on OP2 insts). It also supports inline immediate (for 0.0, +-0.5, +-1.0, 0 and 1) while others immediate can be folded to R600::Imm operand. We currently use a hook in  AMDGPUDAGToDAGISel::Select() function to parse
+inputs when a pattern is matched by llvm instruction selection pass. It has a major drawback though : it will only recursively parse the children of the top most selected instruction (intentionnaly done to avoid parsing whole ISel tree several time). This means than pattern won't be properly parsed : For instance flog ( fabs (fneg x))) will be correctly lowered to a single instruction with both NEG and ABS bit set, but fp_to_sint ( fneg (x)) won't, because fp_to_sint is lowered to FP_TO_INT (TRUNC (x)) ; we will parse FP_TO_INT input, see it's not a fneg/fabs/immediate, and returns.
+To avoid that, we can use the PostprocessISelDAG hook : all nodes are MachineNode after ISel and we can parse the use list of all nodes to optimize them when possible.
 ### Compute
 
 * **Enable constant address space **