diff options
author | Thierry Reding <treding@nvidia.com> | 2014-01-10 10:17:45 +0100 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2014-01-10 10:17:45 +0100 |
commit | 408a79af00d8e772e6aa3e4ac5a14c1280e923a5 (patch) | |
tree | cbb874897635a7644308d849b5fc5246920f78e8 | |
parent | e393227426c8f6028d29444ec5fcaaeeae812690 (diff) | |
parent | ed6cd9798c923ab784f2440f70ec611bd1376f53 (diff) |
Merge branch 'next/drm'
25 files changed, 3667 insertions, 29 deletions
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index 9e9008f8fa32..866ce4ce37d9 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt @@ -187,6 +187,48 @@ of the following host1x client modules: - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel +- sor: serial output resource + + Required properties: + - compatible: "nvidia,tegra124-sor" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - sor: clock input for the SOR hardware + - parent: input for the pixel clock + - dp: reference clock for the SOR clock + - safe: safe reference for the SOR clock during power up + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - sor + + Optional properties: + - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing + - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection + - nvidia,edid: supplies a binary EDID blob + - nvidia,panel: phandle of a display panel + + Optional properties when driving an eDP output: + - nvidia,dpaux: phandle to a DispayPort AUX interface + +- dpaux: DisplayPort AUX interface + - compatible: "nvidia,tegra124-dpaux" + - reg: Physical base address and length of the controller's registers. + - interrupts: The interrupt outputs from the controller. + - clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must include the following entries: + - dpaux: clock input for the DPAUX hardware + - parent: reference clock + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - dpaux + - vdd-supply: phandle of a supply that powers the DisplayPort link + Example: / { diff --git a/Documentation/devicetree/bindings/panel/lg,lp129qe.txt b/Documentation/devicetree/bindings/panel/lg,lp129qe.txt new file mode 100644 index 000000000000..9f262e0c5a2e --- /dev/null +++ b/Documentation/devicetree/bindings/panel/lg,lp129qe.txt @@ -0,0 +1,7 @@ +LG 12.9" (2560x1700 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lp129qe" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index ec36e7772e57..e281da17d2de 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -200,6 +200,10 @@ config DMA_SHARED_BUFFER APIs extension; the file's descriptor can then be passed on to other driver. +config DMA_BUF_TEST + tristate "DMA-BUF test module" + depends on DMA_SHARED_BUFFER + config DMA_CMA bool "DMA Contiguous Memory Allocator" depends on HAVE_DMA_CONTIGUOUS && CMA diff --git a/drivers/base/Makefile b/drivers/base/Makefile index d08c9d3b1d37..0e62022adb23 100644 --- a/drivers/base/Makefile +++ b/drivers/base/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_PINCTRL) += pinctrl.o ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG +obj-$(CONFIG_DMA_BUF_TEST) += dma-buf-test.o diff --git a/drivers/base/dma-buf-test.c b/drivers/base/dma-buf-test.c new file mode 100644 index 000000000000..f5498b74a09b --- /dev/null +++ b/drivers/base/dma-buf-test.c @@ -0,0 +1,308 @@ +#include <linux/dma-buf.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/miscdevice.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/uaccess.h> + +struct dmabuf_create { + __u32 flags; + __u32 size; +}; + +#define DMABUF_IOCTL_BASE 'D' +#define DMABUF_IOCTL_CREATE _IOWR(DMABUF_IOCTL_BASE, 0, struct dmabuf_create) +#define DMABUF_IOCTL_DELETE _IOWR(DMABUF_IOCTL_BASE, 1, int) +#define DMABUF_IOCTL_EXPORT _IOWR(DMABUF_IOCTL_BASE, 2, int) + +struct dmabuf_file { + struct dma_buf *buf; + dma_addr_t phys; + size_t size; + void *virt; +}; + +static int dmabuf_attach(struct dma_buf *buf, struct device *dev, + struct dma_buf_attachment *attach) +{ + return 0; +} + +static void dmabuf_detach(struct dma_buf *buf, + struct dma_buf_attachment *attach) +{ +} + +static struct sg_table *dmabuf_map_dma_buf(struct dma_buf_attachment *attach, + enum dma_data_direction dir) +{ + struct dmabuf_file *priv = attach->dmabuf->priv; + struct sg_table *sgt; + + sgt = kmalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) + return NULL; + + if (sg_alloc_table(sgt, 1, GFP_KERNEL)) { + kfree(sgt); + return NULL; + } + + sg_dma_address(sgt->sgl) = priv->phys; + sg_dma_len(sgt->sgl) = priv->size; + + return sgt; +} + +static void dmabuf_unmap_dma_buf(struct dma_buf_attachment *attach, + struct sg_table *sgt, + enum dma_data_direction dir) +{ + sg_free_table(sgt); + kfree(sgt); +} + +static void dmabuf_release(struct dma_buf *buf) +{ +} + +static int dmabuf_begin_cpu_access(struct dma_buf *buf, size_t size, + size_t length, + enum dma_data_direction direction) +{ + return 0; +} + +static void dmabuf_end_cpu_access(struct dma_buf *buf, size_t size, + size_t length, + enum dma_data_direction direction) +{ +} + +static void *dmabuf_kmap_atomic(struct dma_buf *buf, unsigned long page) +{ + return NULL; +} + +static void dmabuf_kunmap_atomic(struct dma_buf *buf, unsigned long page, + void *vaddr) +{ +} + +static void *dmabuf_kmap(struct dma_buf *buf, unsigned long page) +{ + return NULL; +} + +static void dmabuf_kunmap(struct dma_buf *buf, unsigned long page, void *vaddr) +{ +} + +static void dmabuf_vm_open(struct vm_area_struct *vma) +{ +} + +static void dmabuf_vm_close(struct vm_area_struct *vma) +{ +} + +static int dmabuf_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + return 0; +} + +static const struct vm_operations_struct dmabuf_vm_ops = { + .open = dmabuf_vm_open, + .close = dmabuf_vm_close, + .fault = dmabuf_vm_fault, +}; + +static int dmabuf_mmap(struct dma_buf *buf, struct vm_area_struct *vma) +{ + pgprot_t prot = vm_get_page_prot(vma->vm_flags); + struct dmabuf_file *priv = buf->priv; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_ops = &dmabuf_vm_ops; + vma->vm_private_data = priv; + vma->vm_page_prot = pgprot_writecombine(prot); + + return remap_pfn_range(vma, vma->vm_start, priv->phys >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot); +} + +static void *dmabuf_vmap(struct dma_buf *buf) +{ + return NULL; +} + +static void dmabuf_vunmap(struct dma_buf *buf, void *vaddr) +{ +} + +static const struct dma_buf_ops dmabuf_ops = { + .attach = dmabuf_attach, + .detach = dmabuf_detach, + .map_dma_buf = dmabuf_map_dma_buf, + .unmap_dma_buf = dmabuf_unmap_dma_buf, + .release = dmabuf_release, + .begin_cpu_access = dmabuf_begin_cpu_access, + .end_cpu_access = dmabuf_end_cpu_access, + .kmap_atomic = dmabuf_kmap_atomic, + .kunmap_atomic = dmabuf_kunmap_atomic, + .kmap = dmabuf_kmap, + .kunmap = dmabuf_kunmap, + .mmap = dmabuf_mmap, + .vmap = dmabuf_vmap, + .vunmap = dmabuf_vunmap, +}; + +static int dmabuf_file_open(struct inode *inode, struct file *file) +{ + struct dmabuf_file *priv; + int ret = 0; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + file->private_data = priv; + + return ret; +} + +static int dmabuf_file_release(struct inode *inode, struct file *file) +{ + struct dmabuf_file *priv = file->private_data; + int ret = 0; + + if (priv->virt) + dma_free_writecombine(NULL, priv->size, priv->virt, priv->phys); + + if (priv->buf) + dma_buf_put(priv->buf); + + kfree(priv); + + return ret; +} + +static int dmabuf_ioctl_create(struct dmabuf_file *priv, const void __user *data) +{ + struct dmabuf_create args; + int ret = 0; + + if (priv->buf || priv->virt) + return -EBUSY; + + if (copy_from_user(&args, data, sizeof(args))) + return -EFAULT; + + priv->virt = dma_alloc_writecombine(NULL, args.size, &priv->phys, + GFP_KERNEL | __GFP_NOWARN); + if (!priv->virt) + return -ENOMEM; + + priv->buf = dma_buf_export(priv, &dmabuf_ops, args.size, args.flags); + if (!priv->buf) { + ret = -ENOMEM; + goto free; + } + + if (IS_ERR(priv->buf)) { + ret = PTR_ERR(priv->buf); + goto free; + } + + priv->size = args.size; + + return 0; + +free: + dma_free_writecombine(NULL, priv->size, priv->virt, priv->phys); + priv->virt = NULL; + return ret; +} + +static int dmabuf_ioctl_delete(struct dmabuf_file *priv, unsigned long flags) +{ + dma_free_writecombine(NULL, priv->size, priv->virt, priv->phys); + priv->virt = NULL; + priv->phys = 0; + priv->size = 0; + + dma_buf_put(priv->buf); + priv->buf = NULL; + + return 0; +} + +static int dmabuf_ioctl_export(struct dmabuf_file *priv, unsigned long flags) +{ + int err; + + get_dma_buf(priv->buf); + + err = dma_buf_fd(priv->buf, flags); + if (err < 0) + dma_buf_put(priv->buf); + + return err; +} + +static long dmabuf_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct dmabuf_file *priv = file->private_data; + long ret = 0; + + switch (cmd) { + case DMABUF_IOCTL_CREATE: + ret = dmabuf_ioctl_create(priv, (const void __user *)arg); + break; + + case DMABUF_IOCTL_DELETE: + ret = dmabuf_ioctl_delete(priv, arg); + break; + + case DMABUF_IOCTL_EXPORT: + ret = dmabuf_ioctl_export(priv, arg); + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +static const struct file_operations dmabuf_fops = { + .owner = THIS_MODULE, + .open = dmabuf_file_open, + .release = dmabuf_file_release, + .unlocked_ioctl = dmabuf_file_ioctl, +}; + +static struct miscdevice dmabuf_device = { + .minor = 128, + .name = "dmabuf", + .fops = &dmabuf_fops, +}; + +static int __init dmabuf_init(void) +{ + return misc_register(&dmabuf_device); +} +module_init(dmabuf_init); + +static void __exit dmabuf_exit(void) +{ + misc_deregister(&dmabuf_device); +} +module_exit(dmabuf_exit); + +MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); +MODULE_DESCRIPTION("DMA-BUF test driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9e978aae8972..a2c99ac401ce 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -346,3 +346,389 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw) } } EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); + +/** + * DOC: dp helpers + * + * The DisplayPort AUX channel is an abstraction to allow generic, driver- + * independent access to AUX functionality. Drivers can take advantage of + * this by filling in the fields of the drm_dp_aux sturcture. + * + * The .transfer() function is the hardware-specific implementation of how + * a transaction is executed on the AUX channel. A pointer to a struct + * drm_dp_aux_msg describing the transaction is passed into this function. + * Upon success, the implementation should return the number of bytes that + * were transferred, or a negative error-code on failure. Helpers propagate + * errors from the .transfer() function, with the exception of the -EBUSY + * error, which causes a transaction to be retried. + * + * The .dev field should be set to a pointer to the device that implements + * the AUX channel. + * + * An AUX channel can also be used to transport I2C messages to a sink. A + * typical application of that is to access an EDID that's present in the + * sink device. The .transfer() function can also be used to execute such + * transactions. The drm_dp_aux_register_i2c_bus() function registers an + * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers + * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter. + */ + +static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, + unsigned int offset, void *buffer, size_t size) +{ + struct drm_dp_aux_msg msg; + unsigned int retry; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.address = offset; + msg.request = request; + msg.buffer = buffer; + msg.size = size; + + /* + * The specification doesn't give any recommendation on how often to + * retry native transactions, so retry 7 times like for I2C-over-AUX + * transactions. + */ + for (retry = 0; retry < 7; retry++) { + err = aux->transfer(aux, &msg); + if (err < 0) { + if (err == -EBUSY) + continue; + + return err; + } + + if (err == 0) + return -EPROTO; + + switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) { + case DP_AUX_NATIVE_REPLY_ACK: + return err; + + case DP_AUX_NATIVE_REPLY_NACK: + return -EIO; + + case DP_AUX_NATIVE_REPLY_DEFER: + usleep_range(400, 500); + break; + } + } + + DRM_ERROR("too many retries, giving up\n"); + return -EIO; +} + +/** + * drm_dp_dpcd_read() - read a series of bytes from the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the (first) register to read + * @buffer: buffer to store the register values + * @size: number of bytes in @buffer + * + * Returns the number of bytes transferred on success, or a negative error + * code on failure. -EIO is returned if the request was NAKed by the sink or + * if the retry count was exceeded. If no bytes were transferred, -EPROTO is + * returned. Errors from the underlying AUX channel transfer function, with + * the exception of -EBUSY (upon which the transaction will be retried), are + * propagated to the caller. + */ +ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size) +{ + return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer, + size); +} +EXPORT_SYMBOL(drm_dp_dpcd_read); + +/** + * drm_dp_dpcd_write() - write a series of bytes to the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the (first) register to write + * @buffer: buffer containing the values to write + * @size: number of bytes in @buffer + * + * Returns the number of bytes transferred on success, or a negative error + * code on failure. -EIO is returned if the request was NAKed by the sink or + * if the retry count was exceeded. If no bytes were transferred, -EPROTO is + * returned. Errors from the underlying AUX channel transfer function, with + * the exception of -EBUSY (upon which the transaction will be retried), are + * propagated to the caller. + */ +ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size) +{ + return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, + size); +} +EXPORT_SYMBOL(drm_dp_dpcd_write); + +/** + * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) + * @aux: DisplayPort AUX channel + * @status: buffer to store the link status in (must be at least 6 bytes) + * + * Returns the number of bytes transferred on success or a negative error + * code on failure. + */ +int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, + u8 status[DP_LINK_STATUS_SIZE]) +{ + return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, + DP_LINK_STATUS_SIZE); +} +EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); + +/** + * drm_dp_link_probe() - probe a DisplayPort link for capabilities + * @aux: DisplayPort AUX channel + * @link: pointer to structure in which to return link capabilities + * + * The structure filled in by this function can usually be passed directly + * into drm_dp_link_power_up() configure the link based on the link's + * capabilities. + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) +{ + u8 value; + int err; + + memset(link, 0, sizeof(*link)); + + err = drm_dp_dpcd_readb(aux, DP_MAX_LINK_RATE, &value); + if (err < 0) + return err; + + link->rate = drm_dp_bw_code_to_link_rate(value); + + err = drm_dp_dpcd_readb(aux, DP_MAX_LANE_COUNT, &value); + if (err < 0) + return err; + + link->num_lanes = value & DP_MAX_LANE_COUNT_MASK; + + if (value & DP_ENHANCED_FRAME_CAP) + link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; + + return 0; +} + +/** + * drm_dp_link_power_up() - power up and configure a DisplayPort link + * @aux: DisplayPort AUX channel + * @link: pointer to a structure containing the link configuration + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link) +{ + u8 value; + int err; + + err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); + if (err < 0) + return err; + + value &= ~DP_SET_POWER_MASK; + value |= DP_SET_POWER_D0; + + err = drm_dp_dpcd_writeb(aux, value, DP_SET_POWER); + if (err < 0) + return err; + + value = drm_dp_link_rate_to_bw_code(link->rate); + + err = drm_dp_dpcd_writeb(aux, value, DP_LINK_BW_SET); + if (err < 0) + return err; + + value = link->num_lanes; + + if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + value |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + + err = drm_dp_dpcd_writeb(aux, value, DP_LANE_COUNT_SET); + if (err < 0) + return err; + + return 0; +} + +/* + * I2C-over-AUX implementation + */ + +static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | + I2C_FUNC_SMBUS_READ_BLOCK_DATA | + I2C_FUNC_SMBUS_BLOCK_PROC_CALL | + I2C_FUNC_10BIT_ADDR; +} + +/* + * Transfer a single I2C-over-AUX message and handle various error conditions, + * retrying the transaction as appropriate. + */ +static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) +{ + unsigned int retry; + int err; + + /* + * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device + * is required to retry at least seven times upon receiving AUX_DEFER + * before giving up the AUX transaction. + */ + for (retry = 0; retry < 7; retry++) { + err = aux->transfer(aux, msg); + if (err < 0) { + if (err == -EBUSY) + continue; + + DRM_DEBUG_KMS("transaction failed: %d\n", err); + return err; + } + + switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { + case DP_AUX_NATIVE_REPLY_ACK: + /* + * For I2C-over-AUX transactions this isn't enough, we + * need to check for the I2C ACK reply. + */ + break; + + case DP_AUX_NATIVE_REPLY_NACK: + DRM_DEBUG_KMS("native nack\n"); + return -EREMOTEIO; + + case DP_AUX_NATIVE_REPLY_DEFER: + DRM_DEBUG_KMS("native defer"); + /* + * We could check for I2C bitrate capabilities and if + * available adjust this interval. We could also be + * more careful with DP-to-legacy adapters where a + * long legacy cable may force very low I2C bit rates. + * + * For now just defer for long enough to hopefully be + * safe for all use-cases. + */ + usleep_range(500, 600); + continue; + + default: + DRM_ERROR("invalid native reply %#04x\n", msg->reply); + return -EREMOTEIO; + } + + switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { + case DP_AUX_I2C_REPLY_ACK: + /* + * Both native ACK and I2C ACK replies received. We + * can assume the transfer was successful. + */ + return 0; + + case DP_AUX_I2C_REPLY_NACK: + DRM_DEBUG_KMS("I2C nack\n"); + return -EREMOTEIO; + + case DP_AUX_I2C_REPLY_DEFER: + DRM_DEBUG_KMS("I2C defer\n"); + usleep_range(400, 500); + continue; + + default: + DRM_ERROR("invalid I2C reply %#04x\n", msg->reply); + return -EREMOTEIO; + } + } + + DRM_ERROR("too many retries, giving up\n"); + return -EREMOTEIO; +} + +static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, + int num) +{ + struct drm_dp_aux *aux = adapter->algo_data; + unsigned int i, j; + + for (i = 0; i < num; i++) { + struct drm_dp_aux_msg msg; + int err; + + /* + * Many hardware implementations support FIFOs larger than a + * single byte, but it has been empirically determined that + * transferring data in larger chunks can actually lead to + * decreased performance. Therefore each message is simply + * transferred byte-by-byte. + */ + for (j = 0; j < msgs[i].len; j++) { + memset(&msg, 0, sizeof(msg)); + msg.address = msgs[i].addr; + + msg.request = (msgs[i].flags & I2C_M_RD) ? + DP_AUX_I2C_READ : + DP_AUX_I2C_WRITE; + + /* + * All messages except the last one are middle-of- + * transfer messages. + */ + if (j < msgs[i].len - 1) + msg.request |= DP_AUX_I2C_MOT; + + msg.buffer = msgs[i].buf + j; + msg.size = 1; + + err = drm_dp_i2c_do_msg(aux, &msg); + if (err < 0) + return err; + } + } + + return num; +} + +static const struct i2c_algorithm drm_dp_i2c_algo = { + .functionality = drm_dp_i2c_functionality, + .master_xfer = drm_dp_i2c_xfer, +}; + +/** + * drm_dp_aux_register_i2c_bus() - register an I2C adapter for I2C-over-AUX + * @aux: DisplayPort AUX channel + * + * Returns 0 on success or a negative error code on failure. + */ +int drm_dp_aux_register_i2c_bus(struct drm_dp_aux *aux) +{ + aux->ddc.algo = &drm_dp_i2c_algo; + aux->ddc.algo_data = aux; + aux->ddc.retries = 3; + + aux->ddc.class = I2C_CLASS_DDC; + aux->ddc.owner = THIS_MODULE; + aux->ddc.dev.parent = aux->dev; + aux->ddc.dev.of_node = aux->dev->of_node; + + strncpy(aux->ddc.name, dev_name(aux->dev), sizeof(aux->ddc.name)); + + return i2c_add_adapter(&aux->ddc); +} +EXPORT_SYMBOL(drm_dp_aux_register_i2c_bus); + +/** + * drm_dp_aux_unregister_i2c_bus() - unregister an I2C-over-AUX adapter + * @aux: DisplayPort AUX channel + */ +void drm_dp_aux_unregister_i2c_bus(struct drm_dp_aux *aux) +{ + i2c_del_adapter(&aux->ddc); +} +EXPORT_SYMBOL(drm_dp_aux_unregister_i2c_bus); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 8835dcddfac3..6a9dab99bef4 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1096,14 +1096,15 @@ EXPORT_SYMBOL(drm_edid_is_valid); #define DDC_SEGMENT_ADDR 0x30 /** - * Get EDID information via I2C. + * drm_do_probe_ddc_edid() - get EDID information via I2C + * @adapter: I2C adapter to use for DDC + * @buf: EDID data buffer to be filled + * @block: EDID block to read + * @len: EDID data buffer length * - * \param adapter : i2c device adaptor - * \param buf : EDID data buffer to be filled - * \param len : EDID data buffer length - * \return 0 on success or -1 on failure. + * Try to fetch EDID information using the specified I2C adapter. * - * Try to fetch EDID information by calling i2c driver function. + * Returns 0 on success or -1 on failure. */ static int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, @@ -1242,10 +1243,10 @@ out: } /** - * Probe DDC presence. + * drm_probe_ddc() - probe DDC presence + * @adapter: I2C adapter to use for DDC * - * \param adapter : i2c device adaptor - * \return 1 on success + * Returns true on success or false on failure. */ bool drm_probe_ddc(struct i2c_adapter *adapter) @@ -1586,15 +1587,16 @@ bad_std_timing(u8 a, u8 b) /** * drm_mode_std - convert standard mode info (width, height, refresh) into mode + * @connector: connector to probe + * @edid: EDID block * @t: standard timing params - * @timing_level: standard timing level * * Take the standard timing params (in this case width, aspect, and refresh) * and convert them into a real mode using CVT/GTF/DMT. */ static struct drm_display_mode * drm_mode_std(struct drm_connector *connector, struct edid *edid, - struct std_timing *t, int revision) + struct std_timing *t) { struct drm_device *dev = connector->dev; struct drm_display_mode *m, *mode = NULL; @@ -1615,7 +1617,7 @@ drm_mode_std(struct drm_connector *connector, struct edid *edid, vrefresh_rate = vfreq + 60; /* the vdisplay is calculated based on the aspect ratio */ if (aspect_ratio == 0) { - if (revision < 3) + if (edid->revision < 3) vsize = hsize; else vsize = (hsize * 10) / 16; @@ -2132,6 +2134,7 @@ do_established_modes(struct detailed_timing *timing, void *c) /** * add_established_modes - get est. modes from EDID and add them + * @connector: connector to add mode(s) to * @edid: EDID block to scan * * Each EDID block contains a bitmap of the supported "established modes" list @@ -2182,8 +2185,7 @@ do_standard_modes(struct detailed_timing *timing, void *c) struct drm_display_mode *newmode; std = &data->data.timings[i]; - newmode = drm_mode_std(connector, edid, std, - edid->revision); + newmode = drm_mode_std(connector, edid, std); if (newmode) { drm_mode_probed_add(connector, newmode); closure->modes++; @@ -2194,6 +2196,7 @@ do_standard_modes(struct detailed_timing *timing, void *c) /** * add_standard_modes - get std. modes from EDID and add them + * @connector: connector to add mode(s) to * @edid: EDID block to scan * * Standard modes can be calculated using the appropriate standard (DMT, @@ -2211,8 +2214,7 @@ add_standard_modes(struct drm_connector *connector, struct edid *edid) struct drm_display_mode *newmode; newmode = drm_mode_std(connector, edid, - &edid->standard_timings[i], - edid->revision); + &edid->standard_timings[i]); if (newmode) { drm_mode_probed_add(connector, newmode); modes++; @@ -3237,13 +3239,13 @@ EXPORT_SYMBOL(drm_detect_hdmi_monitor); /** * drm_detect_monitor_audio - check monitor audio capability + * @edid: EDID block to scan * * Monitor should have CEA extension block. * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic * audio' only. If there is any audio extension block and supported * audio format, assume at least 'basic audio' support, even if 'basic * audio' is not defined in EDID. - * */ bool drm_detect_monitor_audio(struct edid *edid) { @@ -3282,6 +3284,7 @@ EXPORT_SYMBOL(drm_detect_monitor_audio); /** * drm_rgb_quant_range_selectable - is RGB quantization range selectable? + * @edid: EDID block to scan * * Check whether the monitor reports the RGB quantization range selection * as supported. The AVI infoframe can then be used to inform the monitor diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 3e611afc93f4..cdddad3c80e1 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -174,10 +174,54 @@ static int panel_simple_get_modes(struct drm_panel *panel) return num; } +static int panel_simple_get_brightness_range(struct drm_panel *panel, + uint64_t *min, uint64_t *max) +{ + struct panel_simple *p = to_panel_simple(panel); + + if (!p->backlight) + return -ENODEV; + + *max = p->backlight->props.max_brightness; + *min = 0; + + return 0; +} + +static int panel_simple_get_brightness(struct drm_panel *panel, + uint64_t *value) +{ + struct panel_simple *p = to_panel_simple(panel); + + if (!p->backlight) + return -ENODEV; + + *value = p->backlight->props.brightness; + + return 0; +} + +static int panel_simple_set_brightness(struct drm_panel *panel, + uint64_t value) +{ + struct panel_simple *p = to_panel_simple(panel); + + if (!p->backlight) + return -ENODEV; + + p->backlight->props.brightness = value; + backlight_update_status(p->backlight); + + return 0; +} + static const struct drm_panel_funcs panel_simple_funcs = { .disable = panel_simple_disable, .enable = panel_simple_enable, .get_modes = panel_simple_get_modes, + .get_brightness_range = panel_simple_get_brightness_range, + .get_brightness = panel_simple_get_brightness, + .set_brightness = panel_simple_set_brightness, }; static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 8d220afbd85f..95f4eb605ca8 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -11,7 +11,11 @@ tegra-drm-y := \ hdmi.o \ mipi-phy.o \ dsi.o \ + sor.o \ + dpaux.o \ gr2d.o \ gr3d.o +tegra-drm-y += gk20a.o + obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 386f3b4b0094..9684109de6cc 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -225,6 +225,79 @@ void tegra_dc_disable_vblank(struct tegra_dc *dc) spin_unlock_irqrestore(&dc->lock, flags); } +static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file, + uint32_t handle, uint32_t width, + uint32_t height, int32_t hot_x, int32_t hot_y) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + struct drm_gem_object *gem; + struct tegra_bo *bo = NULL; + unsigned long value; + int ret = 0; + + dev_dbg(dc->dev, "> %s(crtc=%p, file=%p, handle=%x, width=%u, height=%u, hot_x=%d, hot_y=%d)\n", + __func__, crtc, file, handle, width, height, hot_x, hot_y); + + if (handle) { + gem = drm_gem_object_lookup(crtc->dev, file, handle); + if (!gem) { + ret = -ENOENT; + goto out; + } + + bo = to_tegra_bo(gem); + } + + if (bo) { + value = (0 << 28) | (1 << 24) | bo->paddr >> 10; + tegra_dc_writel(dc, bo->paddr, DC_DISP_CURSOR_START_ADDR); + + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value |= CURSOR_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + + value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); + value |= (1 << 24); + value &= ~(3 << 16); + value &= ~(3 << 8); + value &= ~0xff; + tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); + } else { + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value &= ~CURSOR_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + } + + tegra_dc_writel(dc, 1 << 15, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, 1 << 7, DC_CMD_STATE_CONTROL); + + tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + +out: + dev_dbg(dc->dev, "< %s() = %d\n", __func__, ret); + return ret; +} + +static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y) +{ + struct tegra_dc *dc = to_tegra_dc(crtc); + int ret = 0; + + dev_dbg(dc->dev, "> %s(crtc=%p, x=%d, y=%d)\n", __func__, crtc, x, y); + + tegra_dc_writel(dc, (x << 16) | y, DC_DISP_CURSOR_POSITION); + + tegra_dc_writel(dc, 1 << 15, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, 1 << 7, DC_CMD_STATE_CONTROL); + + tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + + dev_dbg(dc->dev, "< %s() = %d\n", __func__, ret); + return ret; +} + static void tegra_dc_finish_page_flip(struct tegra_dc *dc) { struct drm_device *drm = dc->base.dev; @@ -301,6 +374,8 @@ static void tegra_dc_destroy(struct drm_crtc *crtc) } static const struct drm_crtc_funcs tegra_crtc_funcs = { + .cursor_set2 = tegra_dc_cursor_set2, + .cursor_move = tegra_dc_cursor_move, .page_flip = tegra_dc_page_flip, .set_config = drm_crtc_helper_set_config, .destroy = tegra_dc_destroy, @@ -1100,8 +1175,6 @@ static int tegra_dc_init(struct host1x_client *client) struct tegra_dc *dc = host1x_client_to_dc(client); int err; - dc->pipe = tegra->drm->mode_config.num_crtc; - drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs); drm_mode_crtc_set_gamma_size(&dc->base, 256); drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); @@ -1228,6 +1301,11 @@ static int tegra_dc_probe(struct platform_device *pdev) if (IS_ERR(dc->regs)) return PTR_ERR(dc->regs); + if (regs->start == 0x54200000) + dc->pipe = 0; + else + dc->pipe = 1; + dc->irq = platform_get_irq(pdev, 0); if (dc->irq < 0) { dev_err(&pdev->dev, "failed to get IRQ\n"); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 3c2c0ea1cd87..e531f1e5addd 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -116,8 +116,10 @@ #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 #define DC_DISP_DISP_WIN_OPTIONS 0x402 -#define HDMI_ENABLE (1 << 30) -#define DSI_ENABLE (1 << 29) +#define HDMI_ENABLE (1 << 30) +#define DSI_ENABLE (1 << 29) +#define SOR_ENABLE (1 << 25) +#define CURSOR_ENABLE (1 << 16) #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) @@ -301,6 +303,8 @@ #define INTERLACE_START (1 << 1) #define INTERLACE_ENABLE (1 << 0) +#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 + #define DC_WIN_CSC_YOF 0x611 #define DC_WIN_CSC_KYRGB 0x612 #define DC_WIN_CSC_KUR 0x613 diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c new file mode 100644 index 000000000000..02585b34c875 --- /dev/null +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -0,0 +1,561 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_dp_helper.h> +#include <drm/drm_panel.h> + +#include "dpaux.h" +#include "drm.h" + +static DEFINE_MUTEX(dpaux_lock); +static LIST_HEAD(dpaux_list); + +struct tegra_dpaux { + struct drm_dp_aux aux; + struct device *dev; + + void __iomem *regs; + int irq; + + struct tegra_output *output; + + struct reset_control *rst; + struct clk *clk_parent; + struct clk *clk; + + struct regulator *vdd; + + struct completion complete; + struct list_head list; +}; + +static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) +{ + return container_of(aux, struct tegra_dpaux, aux); +} + +static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux, + unsigned long offset) +{ + return readl(dpaux->regs + (offset << 2)); +} + +static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, + unsigned long value, + unsigned long offset) +{ + writel(value, dpaux->regs + (offset << 2)); +} + +static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, + size_t size) +{ + unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0); + size_t i, j; + + for (i = 0; i < size; i += 4) { + size_t num = min_t(size_t, size - i, 4); + unsigned long value = 0; + + for (j = 0; j < num; j++) + value |= buffer[i + j] << (j * 8); + + tegra_dpaux_writel(dpaux, value, offset++); + } +} + +static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, + size_t size) +{ + unsigned long offset = DPAUX_DP_AUXDATA_READ(0); + size_t i, j; + + for (i = 0; i < size; i += 4) { + size_t num = min_t(size_t, size - i, 4); + unsigned long value; + + value = tegra_dpaux_readl(dpaux, offset++); + + for (j = 0; j < num; j++) + buffer[i + j] = value >> (j * 8); + } +} + +static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + unsigned long value = DPAUX_DP_AUXCTL_TRANSACTREQ; + unsigned long timeout = msecs_to_jiffies(250); + struct tegra_dpaux *dpaux = to_dpaux(aux); + unsigned long status; + ssize_t ret = 0; + + if (msg->size < 1 || msg->size > 16) + return -EINVAL; + + tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); + + switch (msg->request & ~DP_AUX_I2C_MOT) { + case DP_AUX_I2C_WRITE: + if (msg->request & DP_AUX_I2C_MOT) + value = DPAUX_DP_AUXCTL_CMD_MOT_WR; + else + value = DPAUX_DP_AUXCTL_CMD_I2C_WR; + + break; + + case DP_AUX_I2C_READ: + if (msg->request & DP_AUX_I2C_MOT) + value = DPAUX_DP_AUXCTL_CMD_MOT_RD; + else + value = DPAUX_DP_AUXCTL_CMD_I2C_RD; + + break; + + case DP_AUX_I2C_STATUS: + if (msg->request & DP_AUX_I2C_MOT) + value = DPAUX_DP_AUXCTL_CMD_MOT_RQ; + else + value = DPAUX_DP_AUXCTL_CMD_I2C_RQ; + + break; + + case DP_AUX_NATIVE_WRITE: + value = DPAUX_DP_AUXCTL_CMD_AUX_WR; + break; + + case DP_AUX_NATIVE_READ: + value = DPAUX_DP_AUXCTL_CMD_AUX_RD; + break; + + default: + return -EINVAL; + } + + value |= DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); + tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); + + if ((msg->request & DP_AUX_I2C_READ) == 0) { + tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); + ret = msg->size; + } + + /* start transaction */ + value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); + value |= DPAUX_DP_AUXCTL_TRANSACTREQ; + tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); + + status = wait_for_completion_timeout(&dpaux->complete, timeout); + if (!status) + return -ETIMEDOUT; + + /* read status and clear errors */ + value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); + tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); + + if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) + return -ETIMEDOUT; + + if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) || + (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) || + (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) + return -EIO; + + switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) { + case 0x00: + msg->reply = DP_AUX_NATIVE_REPLY_ACK; + break; + + case 0x01: + msg->reply = DP_AUX_NATIVE_REPLY_NACK; + break; + + case 0x02: + msg->reply = DP_AUX_NATIVE_REPLY_DEFER; + break; + + case 0x04: + msg->reply = DP_AUX_I2C_REPLY_NACK; + break; + + case 0x08: + msg->reply = DP_AUX_I2C_REPLY_DEFER; + break; + } + + if (msg->reply == DP_AUX_NATIVE_REPLY_ACK) { + if (msg->request & DP_AUX_I2C_READ) { + size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK; + + if (WARN_ON(count != msg->size)) + count = min_t(size_t, count, msg->size); + + tegra_dpaux_read_fifo(dpaux, msg->buffer, count); + ret = count; + } + } + + return ret; +} + +static irqreturn_t tegra_dpaux_irq(int irq, void *data) +{ + struct tegra_dpaux *dpaux = data; + irqreturn_t ret = IRQ_HANDLED; + unsigned long value; + + /* clear interrupts */ + value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); + tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); + + if (value & DPAUX_INTR_PLUG_EVENT) { + if (dpaux->output) { + drm_helper_hpd_irq_event(dpaux->output->connector.dev); + } + } + + if (value & DPAUX_INTR_UNPLUG_EVENT) { + if (dpaux->output) + drm_helper_hpd_irq_event(dpaux->output->connector.dev); + } + + if (value & DPAUX_INTR_IRQ_EVENT) { + /* TODO: handle this */ + } + + if (value & DPAUX_INTR_AUX_DONE) + complete(&dpaux->complete); + + return ret; +} + +static int tegra_dpaux_probe(struct platform_device *pdev) +{ + struct tegra_dpaux *dpaux; + struct resource *regs; + unsigned long value; + int err; + + dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); + if (!dpaux) + return -ENOMEM; + + init_completion(&dpaux->complete); + INIT_LIST_HEAD(&dpaux->list); + dpaux->dev = &pdev->dev; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(dpaux->regs)) + return PTR_ERR(dpaux->regs); + + dpaux->irq = platform_get_irq(pdev, 0); + if (dpaux->irq < 0) { + dev_err(&pdev->dev, "failed to get IRQ\n"); + return -ENXIO; + } + + dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); + if (IS_ERR(dpaux->rst)) + return PTR_ERR(dpaux->rst); + + dpaux->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(dpaux->clk)) + return PTR_ERR(dpaux->clk); + + err = clk_prepare_enable(dpaux->clk); + if (err < 0) + return err; + + reset_control_deassert(dpaux->rst); + + dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); + if (IS_ERR(dpaux->clk_parent)) + return PTR_ERR(dpaux->clk_parent); + + err = clk_prepare_enable(dpaux->clk_parent); + if (err < 0) + return err; + + err = clk_set_rate(dpaux->clk_parent, 270000000); + if (err < 0) { + dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", + err); + return err; + } + + dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); + if (IS_ERR(dpaux->vdd)) + return PTR_ERR(dpaux->vdd); + + err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, + dev_name(dpaux->dev), dpaux); + if (err < 0) { + dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", + dpaux->irq, err); + return err; + } + + dpaux->aux.transfer = tegra_dpaux_transfer; + dpaux->aux.dev = &pdev->dev; + + err = drm_dp_aux_register_i2c_bus(&dpaux->aux); + if (err < 0) + return err; + + /* enable and clear all interrupts */ + value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT | + DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT; + tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); + tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); + + mutex_lock(&dpaux_lock); + list_add_tail(&dpaux->list, &dpaux_list); + mutex_unlock(&dpaux_lock); + + platform_set_drvdata(pdev, dpaux); + + return 0; +} + +static int tegra_dpaux_remove(struct platform_device *pdev) +{ + struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); + + drm_dp_aux_unregister_i2c_bus(&dpaux->aux); + + mutex_lock(&dpaux_lock); + list_del(&dpaux->list); + mutex_unlock(&dpaux_lock); + + clk_disable_unprepare(dpaux->clk_parent); + reset_control_assert(dpaux->rst); + clk_disable_unprepare(dpaux->clk); + + return 0; +} + +static const struct of_device_id tegra_dpaux_of_match[] = { + { .compatible = "nvidia,tegra124-dpaux", }, + { }, +}; + +struct platform_driver tegra_dpaux_driver = { + .driver = { + .name = "tegra-dpaux", + .of_match_table = tegra_dpaux_of_match, + }, + .probe = tegra_dpaux_probe, + .remove = tegra_dpaux_remove, +}; + +struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np) +{ + struct tegra_dpaux *dpaux; + + mutex_lock(&dpaux_lock); + + list_for_each_entry(dpaux, &dpaux_list, list) + if (np == dpaux->dev->of_node) { + mutex_unlock(&dpaux_lock); + return dpaux; + } + + mutex_unlock(&dpaux_lock); + + return NULL; +} + +int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output) +{ + unsigned long timeout; + int err; + + dpaux->output = output; + + err = regulator_enable(dpaux->vdd); + if (err < 0) + return err; + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + enum drm_connector_status status; + + status = tegra_dpaux_detect(dpaux); + if (status == connector_status_connected) + return 0; + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +int tegra_dpaux_detach(struct tegra_dpaux *dpaux) +{ + unsigned long timeout; + int err; + + err = regulator_disable(dpaux->vdd); + if (err < 0) + return err; + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + enum drm_connector_status status; + + status = tegra_dpaux_detect(dpaux); + if (status == connector_status_disconnected) { + dpaux->output = NULL; + return 0; + } + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux) +{ + unsigned long value; + + value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); + + if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) + return connector_status_connected; + + return connector_status_disconnected; +} + +int tegra_dpaux_enable(struct tegra_dpaux *dpaux) +{ + unsigned long value; + + value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) | + DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) | + DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) | + DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV | + DPAUX_HYBRID_PADCTL_MODE_AUX; + tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); + + value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); + value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; + tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); + + return 0; +} + +int tegra_dpaux_disable(struct tegra_dpaux *dpaux) +{ + unsigned long value; + + value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); + value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; + tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); + + return 0; +} + +int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding) +{ + int err; + + err = drm_dp_dpcd_writeb(&dpaux->aux, encoding, + DP_MAIN_LINK_CHANNEL_CODING_SET); + if (err < 0) + return err; + + return 0; +} + +int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, + u8 pattern) +{ + u8 tp = pattern & DP_TRAINING_PATTERN_MASK; + u8 status[DP_LINK_STATUS_SIZE]; + unsigned int i; + u8 value; + int err; + + err = drm_dp_dpcd_writeb(&dpaux->aux, pattern, DP_TRAINING_PATTERN_SET); + if (err < 0) + return err; + + if (tp == DP_TRAINING_PATTERN_DISABLE) + return 0; + + for (i = 0; i < link->num_lanes; i++) { + unsigned int offset = DP_TRAINING_LANE0_SET + i; + + value = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | + DP_TRAIN_PRE_EMPHASIS_0 | + DP_TRAIN_MAX_SWING_REACHED | + DP_TRAIN_VOLTAGE_SWING_400; + + err = drm_dp_dpcd_writeb(&dpaux->aux, value, offset); + if (err < 0) + return err; + } + + usleep_range(500, 1000); + + err = drm_dp_dpcd_read_link_status(&dpaux->aux, status); + if (err < 0) + return err; + + switch (tp) { + case DP_TRAINING_PATTERN_1: + if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) + return -EAGAIN; + + break; + + case DP_TRAINING_PATTERN_2: + if (!drm_dp_channel_eq_ok(status, link->num_lanes)) + return -EAGAIN; + + break; + + default: + dev_err(dpaux->dev, "unsupported training pattern %u\n", tp); + return -EINVAL; + } + + err = drm_dp_dpcd_writeb(&dpaux->aux, 0x00, DP_EDP_CONFIGURATION_SET); + if (err < 0) + return err; + + return 0; +} diff --git a/drivers/gpu/drm/tegra/dpaux.h b/drivers/gpu/drm/tegra/dpaux.h new file mode 100644 index 000000000000..ba179be4f6fd --- /dev/null +++ b/drivers/gpu/drm/tegra/dpaux.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef DRM_TEGRA_DPAUX_H +#define DRM_TEGRA_DPAUX_H + +#define DPAUX_CTXSW 0x00 + +#define DPAUX_INTR_EN_AUX 0x01 +#define DPAUX_INTR_AUX 0x05 +#define DPAUX_INTR_AUX_DONE (1 << 3) +#define DPAUX_INTR_IRQ_EVENT (1 << 2) +#define DPAUX_INTR_UNPLUG_EVENT (1 << 1) +#define DPAUX_INTR_PLUG_EVENT (1 << 0) + +#define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2)) +#define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2)) +#define DPAUX_DP_AUXADDR 0x29 + +#define DPAUX_DP_AUXCTL 0x2d +#define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16) +#define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12) +#define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12) +#define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff) + +#define DPAUX_DP_AUXSTAT 0x31 +#define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28) +#define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10) +#define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8) +#define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff) + +#define DPAUX_DP_AUX_SINKSTAT_LO 0x35 +#define DPAUX_DP_AUX_SINKSTAT_HI 0x39 + +#define DPAUX_HPD_CONFIG 0x3d +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff) + +#define DPAUX_HPD_IRQ_CONFIG 0x41 +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff) + +#define DPAUX_DP_AUX_CONFIG 0x45 + +#define DPAUX_HYBRID_PADCTL 0x49 +#define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1) +#define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0) +#define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0) + +#define DPAUX_HYBRID_SPARE 0x4d +#define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0) + +#define DPAUX_SCRATCH_REG0 0x51 +#define DPAUX_SCRATCH_REG1 0x55 +#define DPAUX_SCRATCH_REG2 0x59 + +#endif diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 88a529008ce0..1d4821169d3c 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -665,6 +665,8 @@ static const struct of_device_id host1x_drm_subdevs[] = { { .compatible = "nvidia,tegra114-hdmi", }, { .compatible = "nvidia,tegra114-gr3d", }, { .compatible = "nvidia,tegra124-dc", }, + { .compatible = "nvidia,tegra124-sor", }, + { .compatible = "nvidia,tegra124-hdmi", }, { /* sentinel */ } }; @@ -691,14 +693,22 @@ static int __init host1x_drm_init(void) if (err < 0) goto unregister_dc; - err = platform_driver_register(&tegra_hdmi_driver); + err = platform_driver_register(&tegra_sor_driver); if (err < 0) goto unregister_dsi; - err = platform_driver_register(&tegra_gr2d_driver); + err = platform_driver_register(&tegra_hdmi_driver); + if (err < 0) + goto unregister_sor; + + err = platform_driver_register(&tegra_dpaux_driver); if (err < 0) goto unregister_hdmi; + err = platform_driver_register(&tegra_gr2d_driver); + if (err < 0) + goto unregister_dpaux; + err = platform_driver_register(&tegra_gr3d_driver); if (err < 0) goto unregister_gr2d; @@ -707,8 +717,12 @@ static int __init host1x_drm_init(void) unregister_gr2d: platform_driver_unregister(&tegra_gr2d_driver); +unregister_dpaux: + platform_driver_unregister(&tegra_dpaux_driver); unregister_hdmi: platform_driver_unregister(&tegra_hdmi_driver); +unregister_sor: + platform_driver_unregister(&tegra_sor_driver); unregister_dsi: platform_driver_unregister(&tegra_dsi_driver); unregister_dc: @@ -723,7 +737,9 @@ static void __exit host1x_drm_exit(void) { platform_driver_unregister(&tegra_gr3d_driver); platform_driver_unregister(&tegra_gr2d_driver); + platform_driver_unregister(&tegra_dpaux_driver); platform_driver_unregister(&tegra_hdmi_driver); + platform_driver_unregister(&tegra_sor_driver); platform_driver_unregister(&tegra_dsi_driver); platform_driver_unregister(&tegra_dc_driver); host1x_driver_unregister(&host1x_drm_driver); diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index bf1cac7658f8..3a13ae90bc9a 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -179,12 +179,15 @@ struct tegra_output_ops { int (*check_mode)(struct tegra_output *output, struct drm_display_mode *mode, enum drm_mode_status *status); + enum drm_connector_status (*detect)(struct tegra_output *output); }; enum tegra_output_type { TEGRA_OUTPUT_RGB, TEGRA_OUTPUT_HDMI, TEGRA_OUTPUT_DSI, + TEGRA_OUTPUT_EDP, + TEGRA_OUTPUT_LVDS, }; struct tegra_output { @@ -202,6 +205,8 @@ struct tegra_output { struct drm_encoder encoder; struct drm_connector connector; + + struct drm_property *brightness; }; static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) @@ -265,6 +270,22 @@ extern int tegra_output_remove(struct tegra_output *output); extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); extern int tegra_output_exit(struct tegra_output *output); +/* from dpaux.c */ + +struct tegra_dpaux; +struct drm_dp_link; +struct drm_dp_aux; + +struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np); +enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux); +int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output); +int tegra_dpaux_detach(struct tegra_dpaux *dpaux); +int tegra_dpaux_enable(struct tegra_dpaux *dpaux); +int tegra_dpaux_disable(struct tegra_dpaux *dpaux); +int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding); +int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, + u8 pattern); + /* from fb.c */ struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, unsigned int index); @@ -278,7 +299,9 @@ extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); extern struct platform_driver tegra_dc_driver; extern struct platform_driver tegra_dsi_driver; +extern struct platform_driver tegra_sor_driver; extern struct platform_driver tegra_hdmi_driver; +extern struct platform_driver tegra_dpaux_driver; extern struct platform_driver tegra_gr2d_driver; extern struct platform_driver tegra_gr3d_driver; diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index d452faab0235..bdca68651612 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -783,6 +783,131 @@ static void tegra_dsi_initialize(struct tegra_dsi *dsi) tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); } +static int tegra_dsi_set_lp_clk(struct tegra_dsi *dsi, unsigned long pclk) +{ + unsigned long bclk, timeout, value; + struct clk *clk, *parent, *base; + unsigned int mul, div; + int err; + + err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); + if (err < 0) + return err; + + bclk = pclk * 8; + + clk = clk_get_parent(dsi->clk); + parent = clk_get_parent(clk); + base = clk_get_parent(parent); + + err = clk_set_rate(base, pclk * 2); + if (err < 0) + return err; + + /* one frame high-speed transmission timeout */ + timeout = bclk / 512; + value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); + tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); + + /* 2 ms peripheral timeout for panel */ + timeout = 2 * bclk / 512 * 1000; + value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); + tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); + + value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); + tegra_dsi_writel(dsi, value, DSI_TO_TALLY); + + return 0; +} + +static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, + struct mipi_dsi_msg *msg) +{ + struct tegra_dsi *dsi = host_to_tegra(host); + unsigned long value, timeout; + const u8 *tx = msg->tx_buf; + unsigned int count = 0, i; + int err; + + dev_info(dsi->dev, "> %s(host=%p, msg=%p)\n", __func__, host, msg); + + /* XXX */ + drm_panel_enable(dsi->output.panel); + + value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); + value |= DSI_POWER_CONTROL_ENABLE; + tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); + usleep_range(300, 1000); + + err = tegra_dsi_set_lp_clk(dsi, 10000000); + if (err < 0) { + dev_err(dsi->dev, "failed to setup low-power clock: %d\n", err); + return err; + } + + tegra_dsi_writel(dsi, DSI_HOST_FIFO_DEPTH, DSI_MAX_THRESHOLD); + + value = tegra_dsi_readl(dsi, DSI_CONTROL); + value = 0x00003031; + tegra_dsi_writel(dsi, value, DSI_CONTROL); + + value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); + value = 0x00102003; + tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); + + if (msg->rx_buf && msg->rx_len > 0) { + value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); + value |= DSI_HOST_CONTROL_BTA; + tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); + } + + value = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); + + value |= tx[0] << 8; + value |= tx[1] << 16; + + tegra_dsi_writel(dsi, value, DSI_WR_DATA); + + tegra_dsi_writel(dsi, 0x00000002, DSI_TRIGGER); + + timeout = jiffies + msecs_to_jiffies(250); + + while (true) { + value = tegra_dsi_readl(dsi, DSI_TRIGGER); + if ((value & 0x00000002) == 0) + break; + + if (time_after(jiffies, timeout)) + return -ETIMEDOUT; + + usleep_range(25, 100); + } + + timeout = jiffies + msecs_to_jiffies(250); + + while (true) { + usleep_range(1000, 2000); + + value = tegra_dsi_readl(dsi, DSI_STATUS); + count = value & 0x1f; + + if (count > 0) + break; + + if (time_after(jiffies, timeout)) + return -ETIMEDOUT; + } + + for (i = 0; i < count; i++) + tegra_dsi_readl(dsi, DSI_RD_DATA); + + /* XXX */ + drm_panel_disable(dsi->output.panel); + + dev_info(dsi->dev, "< %s()\n", __func__); + return 0; +} + static int tegra_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { @@ -796,6 +921,27 @@ static int tegra_dsi_host_attach(struct mipi_dsi_host *host, if (output->panel) { if (output->connector.dev) drm_helper_hpd_irq_event(output->connector.dev); + + if (0) { + struct mipi_dsi_msg msg; + u8 tx[2], rx[2]; + ssize_t err; + + rx[0] = rx[1] = 0; + tx[0] = tx[1] = 0; + + memset(&msg, 0, sizeof(msg)); + msg.channel = 0; + msg.type = 0x05; + msg.tx_buf = tx; + msg.tx_len = 2; + msg.rx_buf = rx; + msg.rx_len = 2; + + err = host->ops->transfer(&dsi->host, &msg); + if (err < 0) + dev_err(dsi->dev, "dsi_host_transfer() failed: %zd\n", err); + } } return 0; @@ -820,6 +966,7 @@ static int tegra_dsi_host_detach(struct mipi_dsi_host *host, static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { .attach = tegra_dsi_host_attach, .detach = tegra_dsi_host_detach, + .transfer = tegra_dsi_host_transfer, }; static int tegra_dsi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/tegra/gk20a.c b/drivers/gpu/drm/tegra/gk20a.c new file mode 100644 index 000000000000..4b9ce4f6e606 --- /dev/null +++ b/drivers/gpu/drm/tegra/gk20a.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/regulator/consumer.h> +#include <linux/tegra-powergate.h> + +struct gk20a { + struct device *dev; + void __iomem *regs; + void __iomem *bar1; + + struct reset_control *rst; + struct clk *clk; + struct clk *clk_pll; + + struct regulator *vdd; + + int irq; + int irq_nostall; +}; + +static inline unsigned long gk20a_readl(struct gk20a *gpu, unsigned long offset) +{ + unsigned long value = readl(gpu->regs + offset); + dev_dbg(gpu->dev, "%08lx > %08lx\n", offset, value); + return value; +} + +static inline void gk20a_writel(struct gk20a *gpu, unsigned long value, + unsigned long offset) +{ + dev_dbg(gpu->dev, "%08lx < %08lx\n", offset, value); + writel(value, gpu->regs + offset); +} + +static irqreturn_t gk20a_irq(int irq, void *data) +{ + struct gk20a *gpu = data; + + dev_dbg(gpu->dev, "> %s(irq=%d, data=%p)\n", __func__, irq, data); + + dev_dbg(gpu->dev, "< %s()\n", __func__); + return IRQ_HANDLED; +} + +static int gk20a_power_up(struct gk20a *gpu) +{ + int err; + + reset_control_assert(gpu->rst); + + err = clk_enable(gpu->clk); + if (err < 0) + return err; + + err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); + if (err < 0) + return err; + + reset_control_deassert(gpu->rst); + + return 0; +} + +static int gk20a_init(struct gk20a *gpu) +{ + unsigned long value; + int err; + + err = gk20a_power_up(gpu); + if (err < 0) + return err; + + value = gk20a_readl(gpu, 0x000000); + dev_dbg(gpu->dev, "NV_PMC_BOOT_0: %08lx\n", value); + dev_dbg(gpu->dev, " Revision: %lu.%lu\n", (value >> 4) & 0xf, + value & 0xf); + dev_dbg(gpu->dev, " Device ID: %lx\n", (value >> 12) & 0x3f); + dev_dbg(gpu->dev, " Implementation: %lx\n", (value >> 20) & 0xf); + dev_dbg(gpu->dev, " Architecture: %lx\n", (value >> 24) & 0x1f); + dev_dbg(gpu->dev, " Foundry: %lx\n", (value >> 29) & 0x7); + + value = gk20a_readl(gpu, 0x000004); + dev_dbg(gpu->dev, "NV_PMC_BOOT_1: %08lx\n", value); + + value = gk20a_readl(gpu, 0x000008); + dev_dbg(gpu->dev, "NV_PMC_BOOT_2: %08lx\n", value); + + value = gk20a_readl(gpu, 0x137250); + dev_dbg(gpu->dev, "0x00137250: %08lx\n", value); + + return 0; +} + +static int tegra_gk20a_probe(struct platform_device *pdev) +{ + struct resource *res; + struct gk20a *gpu; + int err; + + dev_dbg(&pdev->dev, "> %s(pdev=%p)\n", __func__, pdev); + + if (dev_get_drvdata(pdev->dev.parent) == NULL) { + err = -EPROBE_DEFER; + goto out; + } + + gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL); + if (!gpu) { + err = -ENOMEM; + goto out; + } + + gpu->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + gpu->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpu->regs)) { + err = PTR_ERR(gpu->regs); + goto out; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + gpu->bar1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpu->bar1)) { + err = PTR_ERR(gpu->bar1); + goto out; + } + + gpu->vdd = devm_regulator_get(&pdev->dev, "vdd"); + if (IS_ERR(gpu->vdd)) { + err = PTR_ERR(gpu->vdd); + goto out; + } + + gpu->rst = devm_reset_control_get(&pdev->dev, "gpu"); + if (IS_ERR(gpu->rst)) { + err = PTR_ERR(gpu->rst); + goto out; + } + + gpu->clk = devm_clk_get(&pdev->dev, "gpu"); + if (IS_ERR(gpu->clk)) { + err = PTR_ERR(gpu->clk); + goto out; + } + + err = clk_prepare(gpu->clk); + if (err < 0) + goto out; + + gpu->clk_pll = devm_clk_get(&pdev->dev, "pll"); + if (IS_ERR(gpu->clk_pll)) { + err = PTR_ERR(gpu->clk_pll); + goto out; + } + + err = platform_get_irq(pdev, 0); + if (err < 0) + goto out; + + gpu->irq = err; + + err = platform_get_irq(pdev, 1); + if (err < 0) + goto out; + + gpu->irq_nostall = err; + + err = devm_request_irq(&pdev->dev, gpu->irq, gk20a_irq, 0, "stall", + gpu); + if (err < 0) + goto out; + + err = devm_request_irq(&pdev->dev, gpu->irq_nostall, gk20a_irq, 0, + "non-stall", gpu); + if (err < 0) + goto out; + + err = clk_prepare(gpu->clk_pll); + if (err < 0) + goto out; + + err = gk20a_init(gpu); + if (err < 0) + goto out; + + platform_set_drvdata(pdev, gpu); + +out: + dev_dbg(&pdev->dev, "< %s() = %d\n", __func__, err); + return err; +} + +static int tegra_gk20a_remove(struct platform_device *pdev) +{ + struct gk20a *gpu = platform_get_drvdata(pdev); + int err = 0; + + dev_dbg(&pdev->dev, "> %s(pdev=%p)\n", __func__, pdev); + + clk_disable_unprepare(gpu->clk_pll); + clk_disable_unprepare(gpu->clk); + + dev_dbg(&pdev->dev, "< %s() = %d\n", __func__, err); + return err; +} + +static const struct of_device_id tegra_gk20a_match[] = { + { .compatible = "nvidia,tegra124-gk20a" }, + { } +}; + +static struct platform_driver tegra_gk20a_driver = { + .driver = { + .name = "tegra-gk20a", + .of_match_table = tegra_gk20a_match, + }, + .probe = tegra_gk20a_probe, + .remove = tegra_gk20a_remove, +}; +module_platform_driver(tegra_gk20a_driver); diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index bc9cb1ac709b..afe254482380 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -317,6 +317,85 @@ static const struct tmds_config tegra114_tmds_config[] = { }, }; +static const struct tmds_config tegra124_tmds_config[] = { + { /* 480p/576p / 25.2MHz/27MHz modes */ + .pclk = 27000000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 720p / 74.25MHz modes */ + .pclk = 74250000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | + PE_CURRENT1(PE_CURRENT_15_mA_T114) | + PE_CURRENT2(PE_CURRENT_15_mA_T114) | + PE_CURRENT3(PE_CURRENT_15_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 1080p / 148.5MHz modes */ + .pclk = 148500000, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | + SOR_PLL_TMDS_TERMADJ(0), + .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | + PE_CURRENT1(PE_CURRENT_10_mA_T114) | + PE_CURRENT2(PE_CURRENT_10_mA_T114) | + PE_CURRENT3(PE_CURRENT_10_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), + }, { /* 225/297MHz modes */ + .pclk = UINT_MAX, + .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | + SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, + .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) + | SOR_PLL_TMDS_TERM_ENABLE, + .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | + PE_CURRENT1(PE_CURRENT_0_mA_T114) | + PE_CURRENT2(PE_CURRENT_0_mA_T114) | + PE_CURRENT3(PE_CURRENT_0_mA_T114), + .drive_current = + DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | + DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), + .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | + PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), + }, +}; + static const struct tegra_hdmi_audio_config * tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) { @@ -1340,7 +1419,16 @@ static const struct tegra_hdmi_config tegra114_hdmi_config = { .has_sor_io_peak_current = true, }; +static const struct tegra_hdmi_config tegra124_hdmi_config = { + .tmds = tegra124_tmds_config, + .num_tmds = ARRAY_SIZE(tegra124_tmds_config), + .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, + .fuse_override_value = 1 << 31, + .has_sor_io_peak_current = true, +}; + static const struct of_device_id tegra_hdmi_of_match[] = { + { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, diff --git a/drivers/gpu/drm/tegra/output.c b/drivers/gpu/drm/tegra/output.c index f1b5030f55e3..4128308e55fa 100644 --- a/drivers/gpu/drm/tegra/output.c +++ b/drivers/gpu/drm/tegra/output.c @@ -67,22 +67,61 @@ static const struct drm_connector_helper_funcs connector_helper_funcs = { .best_encoder = tegra_connector_best_encoder, }; +static void tegra_output_add_panel_properties(struct tegra_output *output) +{ + struct drm_device *drm = output->connector.dev; + uint64_t min, max, value; + int err; + + if (output->brightness) + return; + + err = drm_panel_get_brightness_range(output->panel, &min, &max); + if (err < 0) + return; + + err = drm_panel_get_brightness(output->panel, &value); + if (err < 0) + return; + + output->brightness = drm_property_create_range(drm, 0, "brightness", + min, max); + drm_object_attach_property(&output->connector.base, output->brightness, + value); +} + +static void tegra_output_remove_panel_properties(struct tegra_output *output) +{ + struct drm_device *drm = output->connector.dev; + + if (output->brightness) { + drm_property_destroy(drm, output->brightness); + output->brightness = NULL; + } +} + static enum drm_connector_status tegra_connector_detect(struct drm_connector *connector, bool force) { struct tegra_output *output = connector_to_output(connector); enum drm_connector_status status = connector_status_unknown; + if (output->ops->detect) + return output->ops->detect(output); + if (gpio_is_valid(output->hpd_gpio)) { if (gpio_get_value(output->hpd_gpio) == 0) status = connector_status_disconnected; else status = connector_status_connected; } else { - if (!output->panel) + if (!output->panel) { + tegra_output_remove_panel_properties(output); status = connector_status_disconnected; - else + } else { + tegra_output_add_panel_properties(output); status = connector_status_connected; + } if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) status = connector_status_connected; @@ -91,6 +130,24 @@ tegra_connector_detect(struct drm_connector *connector, bool force) return status; } +static int tegra_connector_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t value) +{ + struct tegra_output *output = connector_to_output(connector); + int err; + + if (output->panel) { + if (property == output->brightness) { + err = drm_panel_set_brightness(output->panel, value); + if (err < 0) + return err; + } + } + + return 0; +} + static void drm_connector_clear(struct drm_connector *connector) { memset(connector, 0, sizeof(*connector)); @@ -107,6 +164,7 @@ static const struct drm_connector_funcs connector_funcs = { .dpms = drm_helper_connector_dpms, .detect = tegra_connector_detect, .fill_modes = drm_helper_probe_single_connector_modes, + .set_property = tegra_connector_set_property, .destroy = tegra_connector_destroy, }; @@ -289,6 +347,16 @@ int tegra_output_init(struct drm_device *drm, struct tegra_output *output) encoder = DRM_MODE_ENCODER_DSI; break; + case TEGRA_OUTPUT_EDP: + connector = DRM_MODE_CONNECTOR_eDP; + encoder = DRM_MODE_ENCODER_TMDS; + break; + + case TEGRA_OUTPUT_LVDS: + connector = DRM_MODE_CONNECTOR_LVDS; + encoder = DRM_MODE_ENCODER_LVDS; + break; + default: connector = DRM_MODE_CONNECTOR_Unknown; encoder = DRM_MODE_ENCODER_NONE; diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c new file mode 100644 index 000000000000..70d0299201e7 --- /dev/null +++ b/drivers/gpu/drm/tegra/sor.c @@ -0,0 +1,1099 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/reset.h> +#include <linux/tegra-powergate.h> + +#include <drm/drm_dp_helper.h> + +#include "dc.h" +#include "drm.h" +#include "sor.h" + +struct tegra_sor { + struct host1x_client client; + struct tegra_output output; + struct device *dev; + + void __iomem *regs; + + struct reset_control *rst; + struct clk *clk_parent; + struct clk *clk_safe; + struct clk *clk_dp; + struct clk *clk; + + struct tegra_dpaux *dpaux; + + bool enabled; +}; + +static inline struct tegra_sor * +host1x_client_to_sor(struct host1x_client *client) +{ + return container_of(client, struct tegra_sor, client); +} + +static inline struct tegra_sor *to_sor(struct tegra_output *output) +{ + return container_of(output, struct tegra_sor, output); +} + +static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, + unsigned long offset) +{ + return readl(sor->regs + (offset << 2)); +} + +static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, + unsigned long offset) +{ + writel(value, sor->regs + (offset << 2)); +} + +static int tegra_sor_dp_train_fast(struct tegra_sor *sor, + struct drm_dp_link *link) +{ + unsigned long value; + unsigned int i; + u8 pattern; + int err; + + /* setup lane parameters */ + value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | + SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | + SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | + SOR_LANE_DRIVE_CURRENT_LANE0(0x40); + tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); + + value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | + SOR_LANE_PREEMPHASIS_LANE2(0x0f) | + SOR_LANE_PREEMPHASIS_LANE1(0x0f) | + SOR_LANE_PREEMPHASIS_LANE0(0x0f); + tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); + + value = SOR_LANE_POST_CURSOR_LANE3(0x00) | + SOR_LANE_POST_CURSOR_LANE2(0x00) | + SOR_LANE_POST_CURSOR_LANE1(0x00) | + SOR_LANE_POST_CURSOR_LANE0(0x00); + tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); + + /* disable LVDS mode */ + tegra_sor_writel(sor, 0, SOR_LVDS); + + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value |= SOR_DP_PADCTL_TX_PU_ENABLE; + value &= ~SOR_DP_PADCTL_TX_PU_MASK; + value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | + SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + usleep_range(10, 100); + + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | + SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); + if (err < 0) + return err; + + for (i = 0, value = 0; i < link->num_lanes; i++) { + unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | + SOR_DP_TPG_SCRAMBLER_NONE | + SOR_DP_TPG_PATTERN_TRAIN1; + value = (value << 8) | lane; + } + + tegra_sor_writel(sor, value, SOR_DP_TPG); + + pattern = DP_TRAINING_PATTERN_1; + + err = tegra_dpaux_train(sor->dpaux, link, pattern); + if (err < 0) + return err; + + value = tegra_sor_readl(sor, SOR_DP_SPARE_0); + value |= SOR_DP_SPARE_SEQ_ENABLE; + value &= ~SOR_DP_SPARE_PANEL_INTERNAL; + value |= SOR_DP_SPARE_MACRO_SOR_CLK; + tegra_sor_writel(sor, value, SOR_DP_SPARE_0); + + for (i = 0, value = 0; i < link->num_lanes; i++) { + unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | + SOR_DP_TPG_SCRAMBLER_NONE | + SOR_DP_TPG_PATTERN_TRAIN2; + value = (value << 8) | lane; + } + + tegra_sor_writel(sor, value, SOR_DP_TPG); + + pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; + + err = tegra_dpaux_train(sor->dpaux, link, pattern); + if (err < 0) + return err; + + for (i = 0, value = 0; i < link->num_lanes; i++) { + unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | + SOR_DP_TPG_SCRAMBLER_GALIOS | + SOR_DP_TPG_PATTERN_NONE; + value = (value << 8) | lane; + } + + tegra_sor_writel(sor, value, SOR_DP_TPG); + + pattern = DP_TRAINING_PATTERN_DISABLE; + + err = tegra_dpaux_train(sor->dpaux, link, pattern); + if (err < 0) + return err; + + return 0; +} + +static void tegra_sor_super_update(struct tegra_sor *sor) +{ + tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); + tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); + tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); +} + +static void tegra_sor_update(struct tegra_sor *sor) +{ + tegra_sor_writel(sor, 0, SOR_STATE_0); + tegra_sor_writel(sor, 1, SOR_STATE_0); + tegra_sor_writel(sor, 0, SOR_STATE_0); +} + +static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) +{ + unsigned long value; + + value = tegra_sor_readl(sor, SOR_PWM_DIV); + value &= ~SOR_PWM_DIV_MASK; + value |= 0x400; /* period */ + tegra_sor_writel(sor, value, SOR_PWM_DIV); + + value = tegra_sor_readl(sor, SOR_PWM_CTL); + value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; + value |= 0x400; /* duty cycle */ + value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ + value |= SOR_PWM_CTL_TRIGGER; + tegra_sor_writel(sor, value, SOR_PWM_CTL); + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_PWM_CTL); + if ((value & SOR_PWM_CTL_TRIGGER) == 0) + return 0; + + usleep_range(25, 100); + } + + return -ETIMEDOUT; +} + +static int tegra_sor_attach(struct tegra_sor *sor) +{ + unsigned long value, timeout; + + /* wake up in normal mode */ + value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); + value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; + value |= SOR_SUPER_STATE_MODE_NORMAL; + tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); + tegra_sor_super_update(sor); + + /* attach */ + value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); + value |= SOR_SUPER_STATE_ATTACHED; + tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); + tegra_sor_super_update(sor); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_TEST); + if ((value & SOR_TEST_ATTACHED) != 0) + return 0; + + usleep_range(25, 100); + } + + return -ETIMEDOUT; +} + +static int tegra_sor_wakeup(struct tegra_sor *sor) +{ + struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); + unsigned long value, timeout; + + /* enable display controller outputs */ + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); + value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); + + tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + + timeout = jiffies + msecs_to_jiffies(250); + + /* wait for head to wake up */ + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_TEST); + value &= SOR_TEST_HEAD_MODE_MASK; + + if (value == SOR_TEST_HEAD_MODE_AWAKE) + return 0; + + usleep_range(25, 100); + } + + return -ETIMEDOUT; +} + +static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) +{ + unsigned long value; + + value = tegra_sor_readl(sor, SOR_PWR); + value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; + tegra_sor_writel(sor, value, SOR_PWR); + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_PWR); + if ((value & SOR_PWR_TRIGGER) == 0) + return 0; + + usleep_range(25, 100); + } + + return -ETIMEDOUT; +} + +static int tegra_output_sor_enable(struct tegra_output *output) +{ + struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); + struct drm_display_mode *mode = &dc->base.mode; + unsigned int vbe, vse, hbe, hse, vbs, hbs, i; + struct tegra_sor *sor = to_sor(output); + unsigned long value; + int err; + + if (sor->enabled) + return 0; + + err = clk_prepare_enable(sor->clk); + if (err < 0) + return err; + + reset_control_deassert(sor->rst); + + if (sor->dpaux) { + err = tegra_dpaux_enable(sor->dpaux); + if (err < 0) + dev_err(sor->dev, "failed to enable DP: %d\n", err); + } + + err = clk_set_parent(sor->clk, sor->clk_safe); + if (err < 0) + dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; + value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + value = tegra_sor_readl(sor, SOR_PLL_2); + value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + usleep_range(20, 100); + + value = tegra_sor_readl(sor, SOR_PLL_3); + value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; + tegra_sor_writel(sor, value, SOR_PLL_3); + + value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | + SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; + tegra_sor_writel(sor, value, SOR_PLL_0); + + value = tegra_sor_readl(sor, SOR_PLL_2); + value |= SOR_PLL_2_SEQ_PLLCAPPD; + value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; + value |= SOR_PLL_2_LVDS_ENABLE; + tegra_sor_writel(sor, value, SOR_PLL_2); + + value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; + tegra_sor_writel(sor, value, SOR_PLL_1); + + while (true) { + value = tegra_sor_readl(sor, SOR_PLL_2); + if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) + break; + + usleep_range(250, 1000); + } + + value = tegra_sor_readl(sor, SOR_PLL_2); + value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; + value &= ~SOR_PLL_2_PORT_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + + /* + * power up + */ + + /* set safe link bandwidth (1.62 Gbps) */ + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; + value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + /* step 1 */ + value = tegra_sor_readl(sor, SOR_PLL_2); + value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | + SOR_PLL_2_BANDGAP_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + + value = tegra_sor_readl(sor, SOR_PLL_0); + value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; + tegra_sor_writel(sor, value, SOR_PLL_0); + + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value &= ~SOR_DP_PADCTL_PAD_CAL_PD; + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + /* step 2 */ + err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); + if (err < 0) { + dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); + return err; + } + + usleep_range(5, 100); + + /* step 3 */ + value = tegra_sor_readl(sor, SOR_PLL_2); + value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + + usleep_range(20, 100); + + /* step 4 */ + value = tegra_sor_readl(sor, SOR_PLL_0); + value &= ~SOR_PLL_0_POWER_OFF; + value &= ~SOR_PLL_0_VCOPD; + tegra_sor_writel(sor, value, SOR_PLL_0); + + value = tegra_sor_readl(sor, SOR_PLL_2); + value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; + tegra_sor_writel(sor, value, SOR_PLL_2); + + usleep_range(200, 1000); + + /* step 5 */ + value = tegra_sor_readl(sor, SOR_PLL_2); + value &= ~SOR_PLL_2_PORT_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + + /* switch to DP clock */ + err = clk_set_parent(sor->clk, sor->clk_dp); + if (err < 0) + dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); + + /* power dplanes (XXX parameterize based on link?) */ + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | + SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); + value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; + value |= SOR_DP_LINKCTL_LANE_COUNT(4); + tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); + + /* start lane sequencer */ + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | + SOR_LANE_SEQ_CTL_POWER_STATE_UP; + tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); + + while (true) { + value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) + break; + + usleep_range(250, 1000); + } + + /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; + value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + /* set linkctl */ + value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); + value |= SOR_DP_LINKCTL_ENABLE; + + value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; + value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */ + + value |= SOR_DP_LINKCTL_ENHANCED_FRAME; + tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); + + for (i = 0, value = 0; i < 4; i++) { + unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | + SOR_DP_TPG_SCRAMBLER_GALIOS | + SOR_DP_TPG_PATTERN_NONE; + value = (value << 8) | lane; + } + + tegra_sor_writel(sor, value, SOR_DP_TPG); + + value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); + value &= ~SOR_DP_CONFIG_WATERMARK_MASK; + value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */ + + value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; + value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */ + + value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; + value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */ + + value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */ + + value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; + value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */ + tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); + + value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); + value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; + value |= 137; /* XXX: don't hardcode? */ + tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); + + value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); + value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; + value |= 2368; /* XXX: don't hardcode? */ + tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); + + /* enable pad calibration logic */ + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value |= SOR_DP_PADCTL_PAD_CAL_PD; + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + if (sor->dpaux) { + /* FIXME: properly convert to struct drm_dp_aux */ + struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux; + struct drm_dp_link link; + u8 rate, lanes; + + err = drm_dp_link_probe(aux, &link); + if (err < 0) { + dev_err(sor->dev, "failed to probe eDP link: %d\n", + err); + return err; + } + + err = drm_dp_link_power_up(aux, &link); + if (err < 0) { + dev_err(sor->dev, "failed to power up eDP link: %d\n", + err); + return err; + } + + rate = drm_dp_link_rate_to_bw_code(link.rate); + lanes = link.num_lanes; + + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; + value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); + value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; + value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); + + if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + value |= SOR_DP_LINKCTL_ENHANCED_FRAME; + + tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); + + /* disable training pattern generator */ + + for (i = 0; i < link.num_lanes; i++) { + unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | + SOR_DP_TPG_SCRAMBLER_GALIOS | + SOR_DP_TPG_PATTERN_NONE; + value = (value << 8) | lane; + } + + tegra_sor_writel(sor, value, SOR_DP_TPG); + + err = tegra_sor_dp_train_fast(sor, &link); + if (err < 0) { + dev_err(sor->dev, "DP fast link training failed: %d\n", + err); + return err; + } + + dev_dbg(sor->dev, "fast link training succeeded\n"); + } + + err = tegra_sor_power_up(sor, 250); + if (err < 0) { + dev_err(sor->dev, "failed to power up SOR: %d\n", err); + return err; + } + + /* start display controller in continuous mode */ + value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); + value |= WRITE_MUX; + tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); + + tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); + tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); + + value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); + value &= ~WRITE_MUX; + tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); + + /* + * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete + * raster, associate with display controller) + */ + value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 | + SOR_STATE_ASY_VSYNCPOL | + SOR_STATE_ASY_HSYNCPOL | + SOR_STATE_ASY_PROTOCOL_DP_A | + SOR_STATE_ASY_CRC_MODE_COMPLETE | + SOR_STATE_ASY_OWNER(dc->pipe + 1); + tegra_sor_writel(sor, value, SOR_STATE_1); + + /* + * TODO: The video timing programming below doesn't seem to match the + * register definitions. + */ + + value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); + tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); + + vse = mode->vsync_end - mode->vsync_start - 1; + hse = mode->hsync_end - mode->hsync_start - 1; + + value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); + tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); + + vbe = vse + (mode->vsync_start - mode->vdisplay); + hbe = hse + (mode->hsync_start - mode->hdisplay); + + value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); + tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); + + vbs = vbe + mode->vdisplay; + hbs = hbe + mode->hdisplay; + + value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); + tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); + + /* XXX interlaced mode */ + tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0)); + + /* CSTM (LVDS, link A/B, upper) */ + value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_B | SOR_CSTM_LINK_ACT_B | + SOR_CSTM_UPPER; + tegra_sor_writel(sor, value, SOR_CSTM); + + /* PWM setup */ + err = tegra_sor_setup_pwm(sor, 250); + if (err < 0) { + dev_err(sor->dev, "failed to setup PWM: %d\n", err); + return err; + } + + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value |= SOR_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + + tegra_sor_update(sor); + + err = tegra_sor_attach(sor); + if (err < 0) { + dev_err(sor->dev, "failed to attach SOR: %d\n", err); + return err; + } + + err = tegra_sor_wakeup(sor); + if (err < 0) { + dev_err(sor->dev, "failed to enable DC: %d\n", err); + return err; + } + + sor->enabled = true; + + return 0; +} + +static int tegra_sor_detach(struct tegra_sor *sor) +{ + unsigned long value, timeout; + + /* switch to safe mode */ + value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); + value &= ~SOR_SUPER_STATE_MODE_NORMAL; + tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); + tegra_sor_super_update(sor); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_PWR); + if (value & SOR_PWR_MODE_SAFE) + break; + } + + if ((value & SOR_PWR_MODE_SAFE) == 0) + return -ETIMEDOUT; + + /* go to sleep */ + value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); + value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; + tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); + tegra_sor_super_update(sor); + + /* detach */ + value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); + value &= ~SOR_SUPER_STATE_ATTACHED; + tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); + tegra_sor_super_update(sor); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_TEST); + if ((value & SOR_TEST_ATTACHED) == 0) + break; + + usleep_range(25, 100); + } + + if ((value & SOR_TEST_ATTACHED) != 0) + return -ETIMEDOUT; + + return 0; +} + +static int tegra_sor_power_down(struct tegra_sor *sor) +{ + unsigned long value, timeout; + int err; + + value = tegra_sor_readl(sor, SOR_PWR); + value &= ~SOR_PWR_NORMAL_STATE_PU; + value |= SOR_PWR_TRIGGER; + tegra_sor_writel(sor, value, SOR_PWR); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_PWR); + if ((value & SOR_PWR_TRIGGER) == 0) + return 0; + + usleep_range(25, 100); + } + + if ((value & SOR_PWR_TRIGGER) != 0) + return -ETIMEDOUT; + + err = clk_set_parent(sor->clk, sor->clk_safe); + if (err < 0) + dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + + value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); + value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | + SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); + tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); + + /* stop lane sequencer */ + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | + SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; + tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) + break; + + usleep_range(25, 100); + } + + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) + return -ETIMEDOUT; + + value = tegra_sor_readl(sor, SOR_PLL_2); + value |= SOR_PLL_2_PORT_POWERDOWN; + tegra_sor_writel(sor, value, SOR_PLL_2); + + usleep_range(20, 100); + + value = tegra_sor_readl(sor, SOR_PLL_0); + value |= SOR_PLL_0_POWER_OFF; + value |= SOR_PLL_0_VCOPD; + tegra_sor_writel(sor, value, SOR_PLL_0); + + value = tegra_sor_readl(sor, SOR_PLL_2); + value |= SOR_PLL_2_SEQ_PLLCAPPD; + value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; + tegra_sor_writel(sor, value, SOR_PLL_2); + + usleep_range(20, 100); + + return 0; +} + +static int tegra_output_sor_disable(struct tegra_output *output) +{ + struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); + struct tegra_sor *sor = to_sor(output); + unsigned long value; + int err; + + if (!sor->enabled) + return 0; + + err = tegra_sor_detach(sor); + if (err < 0) { + dev_err(sor->dev, "failed to detach SOR: %d\n", err); + return err; + } + + tegra_sor_writel(sor, 0, SOR_STATE_1); + tegra_sor_update(sor); + + /* + * The following accesses registers of the display controller, so make + * sure it's only executed when the output is attached to one. + */ + if (dc) { + /* + * XXX: We can't do this here because it causes the SOR to go + * into an erroneous state and the output will look scrambled + * the next time it is enabled. Presumably this is because we + * should be doing this only on the next VBLANK. A possible + * solution would be to queue a "power-off" event to trigger + * this code to be run during the next VBLANK. + */ + /* + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); + value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | + PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); + */ + + value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); + value &= ~DISP_CTRL_MODE_MASK; + tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); + + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value &= ~SOR_ENABLE; + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + + tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + } + + err = tegra_sor_power_down(sor); + if (err < 0) { + dev_err(sor->dev, "failed to power down SOR: %d\n", err); + return err; + } + + if (sor->dpaux) { + err = tegra_dpaux_disable(sor->dpaux); + if (err < 0) { + dev_err(sor->dev, "failed to disable DP: %d\n", err); + return err; + } + } + + err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); + if (err < 0) { + dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); + return err; + } + + reset_control_assert(sor->rst); + clk_disable_unprepare(sor->clk); + + sor->enabled = false; + + return 0; +} + +static int tegra_output_sor_setup_clock(struct tegra_output *output, + struct clk *clk, unsigned long pclk) +{ + struct tegra_sor *sor = to_sor(output); + int err; + + /* round to next MHz */ + pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000; + + err = clk_set_parent(clk, sor->clk_parent); + if (err < 0) { + dev_err(sor->dev, "failed to set parent clock: %d\n", err); + return err; + } + + err = clk_set_rate(sor->clk_parent, pclk); + if (err < 0) { + dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n", + pclk * 2); + return err; + } + + return 0; +} + +static int tegra_output_sor_check_mode(struct tegra_output *output, + struct drm_display_mode *mode, + enum drm_mode_status *status) +{ + /* + * FIXME: For now, always assume that the mode is okay. + */ + + *status = MODE_OK; + + return 0; +} + +static enum drm_connector_status +tegra_output_sor_detect(struct tegra_output *output) +{ + struct tegra_sor *sor = to_sor(output); + + if (sor->dpaux) + return tegra_dpaux_detect(sor->dpaux); + + return connector_status_unknown; +} + +static const struct tegra_output_ops sor_ops = { + .enable = tegra_output_sor_enable, + .disable = tegra_output_sor_disable, + .setup_clock = tegra_output_sor_setup_clock, + .check_mode = tegra_output_sor_check_mode, + .detect = tegra_output_sor_detect, +}; + +static int tegra_sor_init(struct host1x_client *client) +{ + struct tegra_drm *tegra = dev_get_drvdata(client->parent); + struct tegra_sor *sor = host1x_client_to_sor(client); + int err; + + if (!sor->dpaux) + sor->output.type = TEGRA_OUTPUT_LVDS; + else + sor->output.type = TEGRA_OUTPUT_EDP; + + sor->output.dev = sor->dev; + sor->output.ops = &sor_ops; + + err = tegra_output_init(tegra->drm, &sor->output); + if (err < 0) { + dev_err(sor->dev, "output setup failed: %d\n", err); + return err; + } + + if (sor->dpaux) { + err = tegra_dpaux_attach(sor->dpaux, &sor->output); + if (err < 0) { + dev_err(sor->dev, "failed to attach DP: %d\n", err); + return err; + } + } + + return 0; +} + +static int tegra_sor_exit(struct host1x_client *client) +{ + struct tegra_sor *sor = host1x_client_to_sor(client); + int err; + + err = tegra_output_disable(&sor->output); + if (err < 0) { + dev_err(sor->dev, "output failed to disable: %d\n", err); + return err; + } + + if (sor->dpaux) { + err = tegra_dpaux_detach(sor->dpaux); + if (err < 0) { + dev_err(sor->dev, "failed to detach DP: %d\n", err); + return err; + } + } + + err = tegra_output_exit(&sor->output); + if (err < 0) { + dev_err(sor->dev, "output cleanup failed: %d\n", err); + return err; + } + + return 0; +} + +static const struct host1x_client_ops sor_client_ops = { + .init = tegra_sor_init, + .exit = tegra_sor_exit, +}; + +static int tegra_sor_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct tegra_sor *sor; + struct resource *regs; + int err; + + sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); + if (!sor) + return -ENOMEM; + + sor->output.dev = sor->dev = &pdev->dev; + + np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); + if (np) { + sor->dpaux = tegra_dpaux_find_by_of_node(np); + of_node_put(np); + + if (!sor->dpaux) + return -EPROBE_DEFER; + } + + err = tegra_output_probe(&sor->output); + if (err < 0) + return err; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sor->regs = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(sor->regs)) + return PTR_ERR(sor->regs); + + sor->rst = devm_reset_control_get(&pdev->dev, "sor"); + if (IS_ERR(sor->rst)) + return PTR_ERR(sor->rst); + + sor->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sor->clk)) + return PTR_ERR(sor->clk); + + sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); + if (IS_ERR(sor->clk_parent)) + return PTR_ERR(sor->clk_parent); + + err = clk_prepare_enable(sor->clk_parent); + if (err < 0) + return err; + + sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); + if (IS_ERR(sor->clk_safe)) + return PTR_ERR(sor->clk_safe); + + err = clk_prepare_enable(sor->clk_safe); + if (err < 0) + return err; + + sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); + if (IS_ERR(sor->clk_dp)) + return PTR_ERR(sor->clk_dp); + + err = clk_prepare_enable(sor->clk_dp); + if (err < 0) + return err; + + INIT_LIST_HEAD(&sor->client.list); + sor->client.ops = &sor_client_ops; + sor->client.dev = &pdev->dev; + + err = host1x_client_register(&sor->client); + if (err < 0) { + dev_err(&pdev->dev, "failed to register host1x client: %d\n", + err); + return err; + } + + platform_set_drvdata(pdev, sor); + + return 0; +} + +static int tegra_sor_remove(struct platform_device *pdev) +{ + struct tegra_sor *sor = platform_get_drvdata(pdev); + int err; + + err = host1x_client_unregister(&sor->client); + if (err < 0) { + dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", + err); + return err; + } + + clk_disable_unprepare(sor->clk_parent); + clk_disable_unprepare(sor->clk_safe); + clk_disable_unprepare(sor->clk_dp); + clk_disable_unprepare(sor->clk); + + return 0; +} + +static const struct of_device_id tegra_sor_of_match[] = { + { .compatible = "nvidia,tegra124-sor", }, + { }, +}; + +struct platform_driver tegra_sor_driver = { + .driver = { + .name = "tegra-sor", + .of_match_table = tegra_sor_of_match, + }, + .probe = tegra_sor_probe, + .remove = tegra_sor_remove, +}; diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h new file mode 100644 index 000000000000..b57d5ea058c4 --- /dev/null +++ b/drivers/gpu/drm/tegra/sor.h @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2013 NVIDIA Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef DRM_TEGRA_SOR_H +#define DRM_TEGRA_SOR_H + +#define SOR_CTXSW 0x00 + +#define SOR_SUPER_STATE_0 0x01 + +#define SOR_SUPER_STATE_1 0x02 +#define SOR_SUPER_STATE_ATTACHED (1 << 3) +#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2) +#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0) +#define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0) +#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0) +#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0) + +#define SOR_STATE_0 0x03 + +#define SOR_STATE_1 0x04 +#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17) +#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17) +#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17) +#define SOR_STATE_ASY_VSYNCPOL (1 << 13) +#define SOR_STATE_ASY_HSYNCPOL (1 << 12) +#define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8) +#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8) +#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8) +#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8) +#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8) +#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6) +#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6) +#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6) +#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6) +#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0) + +#define SOR_HEAD_STATE_0(x) (0x05 + (x)) +#define SOR_HEAD_STATE_1(x) (0x07 + (x)) +#define SOR_HEAD_STATE_2(x) (0x09 + (x)) +#define SOR_HEAD_STATE_3(x) (0x0b + (x)) +#define SOR_HEAD_STATE_4(x) (0x0d + (x)) +#define SOR_HEAD_STATE_5(x) (0x0f + (x)) +#define SOR_CRC_CNTRL 0x11 +#define SOR_DP_DEBUG_MVID 0x12 + +#define SOR_CLK_CNTRL 0x13 +#define SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) +#define SOR_CLK_CNTRL_DP_LINK_SPEED(x) (((x) & 0x1f) << 2) +#define SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (0x06 << 2) +#define SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70 (0x0a << 2) +#define SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40 (0x14 << 2) +#define SOR_CLK_CNTRL_DP_CLK_SEL_MASK (3 << 0) +#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0 << 0) +#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1 << 0) +#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2 << 0) +#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3 << 0) + +#define SOR_CAP 0x14 + +#define SOR_PWR 0x15 +#define SOR_PWR_TRIGGER (1 << 31) +#define SOR_PWR_MODE_SAFE (1 << 28) +#define SOR_PWR_NORMAL_STATE_PU (1 << 0) + +#define SOR_TEST 0x16 +#define SOR_TEST_ATTACHED (1 << 10) +#define SOR_TEST_HEAD_MODE_MASK (3 << 8) +#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8) + +#define SOR_PLL_0 0x17 +#define SOR_PLL_0_ICHPMP_MASK (0xf << 24) +#define SOR_PLL_0_ICHPMP(x) (((x) & 0xf) << 24) +#define SOR_PLL_0_VCOCAP_MASK (0xf << 8) +#define SOR_PLL_0_VCOCAP(x) (((x) & 0xf) << 8) +#define SOR_PLL_0_VCOCAP_RST SOR_PLL_0_VCOCAP(3) +#define SOR_PLL_0_PLLREG_MASK (0x3 << 6) +#define SOR_PLL_0_PLLREG_LEVEL(x) (((x) & 0x3) << 6) +#define SOR_PLL_0_PLLREG_LEVEL_V25 SOR_PLL_0_PLLREG_LEVEL(0) +#define SOR_PLL_0_PLLREG_LEVEL_V15 SOR_PLL_0_PLLREG_LEVEL(1) +#define SOR_PLL_0_PLLREG_LEVEL_V35 SOR_PLL_0_PLLREG_LEVEL(2) +#define SOR_PLL_0_PLLREG_LEVEL_V45 SOR_PLL_0_PLLREG_LEVEL(3) +#define SOR_PLL_0_PULLDOWN (1 << 5) +#define SOR_PLL_0_RESISTOR_EXT (1 << 4) +#define SOR_PLL_0_VCOPD (1 << 2) +#define SOR_PLL_0_POWER_OFF (1 << 0) + +#define SOR_PLL_1 0x18 +/* XXX: read-only bit? */ +#define SOR_PLL_1_TERM_COMPOUT (1 << 15) +#define SOR_PLL_1_TMDS_TERM (1 << 8) + +#define SOR_PLL_2 0x19 +#define SOR_PLL_2_LVDS_ENABLE (1 << 25) +#define SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE (1 << 24) +#define SOR_PLL_2_PORT_POWERDOWN (1 << 23) +#define SOR_PLL_2_BANDGAP_POWERDOWN (1 << 22) +#define SOR_PLL_2_POWERDOWN_OVERRIDE (1 << 18) +#define SOR_PLL_2_SEQ_PLLCAPPD (1 << 17) + +#define SOR_PLL_3 0x1a +#define SOR_PLL_3_PLL_VDD_MODE_V1_8 (0 << 13) +#define SOR_PLL_3_PLL_VDD_MODE_V3_3 (1 << 13) + +#define SOR_CSTM 0x1b +#define SOR_CSTM_LVDS (1 << 16) +#define SOR_CSTM_LINK_ACT_B (1 << 15) +#define SOR_CSTM_LINK_ACT_A (1 << 14) +#define SOR_CSTM_UPPER (1 << 11) + +#define SOR_LVDS 0x1c +#define SOR_CRC_A 0x1d +#define SOR_CRC_B 0x1e +#define SOR_BLANK 0x1f +#define SOR_SEQ_CTL 0x20 + +#define SOR_LANE_SEQ_CTL 0x21 +#define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31) +#define SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) +#define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) +#define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16) +#define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16) + +#define SOR_SEQ_INST(x) (0x22 + (x)) + +#define SOR_PWM_DIV 0x32 +#define SOR_PWM_DIV_MASK 0xffffff + +#define SOR_PWM_CTL 0x33 +#define SOR_PWM_CTL_TRIGGER (1 << 31) +#define SOR_PWM_CTL_CLK_SEL (1 << 30) +#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff + +#define SOR_VCRC_A_0 0x34 +#define SOR_VCRC_A_1 0x35 +#define SOR_VCRC_B_0 0x36 +#define SOR_VCRC_B_1 0x37 +#define SOR_CCRC_A_0 0x38 +#define SOR_CCRC_A_1 0x39 +#define SOR_CCRC_B_0 0x3a +#define SOR_CCRC_B_1 0x3b +#define SOR_EDATA_A_0 0x3c +#define SOR_EDATA_A_1 0x3d +#define SOR_EDATA_B_0 0x3e +#define SOR_EDATA_B_1 0x3f +#define SOR_COUNT_A_0 0x40 +#define SOR_COUNT_A_1 0x41 +#define SOR_COUNT_B_0 0x42 +#define SOR_COUNT_B_1 0x43 +#define SOR_DEBUG_A_0 0x44 +#define SOR_DEBUG_A_1 0x45 +#define SOR_DEBUG_B_0 0x46 +#define SOR_DEBUG_B_1 0x47 +#define SOR_TRIG 0x48 +#define SOR_MSCHECK 0x49 +#define SOR_XBAR_CTRL 0x4a +#define SOR_XBAR_POL 0x4b + +#define SOR_DP_LINKCTL_0 0x4c +#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16) +#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16) +#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14) +#define SOR_DP_LINKCTL_TU_SIZE_MASK (0x7f << 2) +#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2) +#define SOR_DP_LINKCTL_ENABLE (1 << 0) + +#define SOR_DP_LINKCTL_1 0x4d + +#define SOR_LANE_DRIVE_CURRENT_0 0x4e +#define SOR_LANE_DRIVE_CURRENT_1 0x4f +#define SOR_LANE4_DRIVE_CURRENT_0 0x50 +#define SOR_LANE4_DRIVE_CURRENT_1 0x51 +#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24) +#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16) +#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8) +#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0) + +#define SOR_LANE_PREEMPHASIS_0 0x52 +#define SOR_LANE_PREEMPHASIS_1 0x53 +#define SOR_LANE4_PREEMPHASIS_0 0x54 +#define SOR_LANE4_PREEMPHASIS_1 0x55 +#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24) +#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16) +#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8) +#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0) + +#define SOR_LANE_POST_CURSOR_0 0x56 +#define SOR_LANE_POST_CURSOR_1 0x57 +#define SOR_LANE_POST_CURSOR_LANE3(x) (((x) & 0xff) << 24) +#define SOR_LANE_POST_CURSOR_LANE2(x) (((x) & 0xff) << 16) +#define SOR_LANE_POST_CURSOR_LANE1(x) (((x) & 0xff) << 8) +#define SOR_LANE_POST_CURSOR_LANE0(x) (((x) & 0xff) << 0) + +#define SOR_DP_CONFIG_0 0x58 +#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31) +#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26) +#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24) +#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK (0xf << 16) +#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x) (((x) & 0xf) << 16) +#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK (0x7f << 8) +#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x) (((x) & 0x7f) << 8) +#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0) +#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0) + +#define SOR_DP_CONFIG_1 0x59 +#define SOR_DP_MN_0 0x5a +#define SOR_DP_MN_1 0x5b + +#define SOR_DP_PADCTL_0 0x5c +#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23) +#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8) +#define SOR_DP_PADCTL_TX_PU(x) (((x) & 0xff) << 8) +#define SOR_DP_PADCTL_CM_TXD_3 (1 << 7) +#define SOR_DP_PADCTL_CM_TXD_2 (1 << 6) +#define SOR_DP_PADCTL_CM_TXD_1 (1 << 5) +#define SOR_DP_PADCTL_CM_TXD_0 (1 << 4) +#define SOR_DP_PADCTL_PD_TXD_3 (1 << 3) +#define SOR_DP_PADCTL_PD_TXD_0 (1 << 2) +#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1) +#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0) + +#define SOR_DP_PADCTL_1 0x5d + +#define SOR_DP_DEBUG_0 0x5e +#define SOR_DP_DEBUG_1 0x5f + +#define SOR_DP_SPARE_0 0x60 +#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2) +#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) +#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0) + +#define SOR_DP_SPARE_1 0x61 +#define SOR_DP_AUDIO_CTRL 0x62 + +#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63 +#define SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x01ffff << 0) + +#define SOR_DP_AUDIO_VBLANK_SYMBOLS 0x64 +#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0) + +#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65 +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_0 0x66 +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_1 0x67 +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_2 0x68 +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_3 0x69 +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_4 0x6a +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_5 0x6b +#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_6 0x6c + +#define SOR_DP_TPG 0x6d +#define SOR_DP_TPG_CHANNEL_CODING (1 << 6) +#define SOR_DP_TPG_SCRAMBLER_MASK (3 << 4) +#define SOR_DP_TPG_SCRAMBLER_FIBONACCI (2 << 4) +#define SOR_DP_TPG_SCRAMBLER_GALIOS (1 << 4) +#define SOR_DP_TPG_SCRAMBLER_NONE (0 << 4) +#define SOR_DP_TPG_PATTERN_MASK (0xf << 0) +#define SOR_DP_TPG_PATTERN_HBR2 (0x8 << 0) +#define SOR_DP_TPG_PATTERN_CSTM (0x7 << 0) +#define SOR_DP_TPG_PATTERN_PRBS7 (0x6 << 0) +#define SOR_DP_TPG_PATTERN_SBLERRRATE (0x5 << 0) +#define SOR_DP_TPG_PATTERN_D102 (0x4 << 0) +#define SOR_DP_TPG_PATTERN_TRAIN3 (0x3 << 0) +#define SOR_DP_TPG_PATTERN_TRAIN2 (0x2 << 0) +#define SOR_DP_TPG_PATTERN_TRAIN1 (0x1 << 0) +#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0) + +#define SOR_DP_TPG_CONFIG 0x6e +#define SOR_DP_LQ_CSTM_0 0x6f +#define SOR_DP_LQ_CSTM_1 0x70 +#define SOR_DP_LQ_CSTM_2 0x71 + +#endif diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c index 1146e3bba6e1..85be2f7b95f0 100644 --- a/drivers/gpu/host1x/job.c +++ b/drivers/gpu/host1x/job.c @@ -507,12 +507,16 @@ static inline int copy_gathers(struct host1x_job *job, struct device *dev) int host1x_job_pin(struct host1x_job *job, struct device *dev) { - int err; - unsigned int i, j; struct host1x *host = dev_get_drvdata(dev->parent); - DECLARE_BITMAP(waitchk_mask, host1x_syncpt_nb_pts(host)); + unsigned int num = host1x_syncpt_nb_pts(host); + unsigned long *waitchk_mask; + unsigned int i, j; + int err; + + waitchk_mask = kcalloc(sizeof(*waitchk_mask), num, GFP_KERNEL); + if (!waitchk_mask) + return -ENOMEM; - bitmap_zero(waitchk_mask, host1x_syncpt_nb_pts(host)); for (i = 0; i < job->num_waitchk; i++) { u32 syncpt_id = job->waitchk[i].syncpt_id; if (syncpt_id < host1x_syncpt_nb_pts(host)) @@ -523,6 +527,8 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev) for_each_set_bit(i, waitchk_mask, host1x_syncpt_nb_pts(host)) host1x_syncpt_load(host->syncpt + i); + kfree(waitchk_mask); + /* pin memory */ err = pin_job(job); if (!err) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d09050a8c00..179c91a7f7f5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -291,6 +291,7 @@ #define DP_SET_POWER 0x600 # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ # define DP_PSR_LINK_CRC_ERROR (1 << 0) @@ -398,4 +399,93 @@ drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); } +/* + * DisplayPort AUX channel + */ + +/** + * struct drm_dp_aux_msg - DisplayPort AUX channel transaction + * @address: address of the (first) register to access + * @request: contains the type of transaction (see DP_AUX_* macros) + * @reply: upon completion, contains the reply type of the transaction + * @buffer: pointer to a transmission or reception buffer + * @size: size of @buffer + */ +struct drm_dp_aux_msg { + unsigned int address; + u8 request; + u8 reply; + void *buffer; + size_t size; +}; + +/** + * struct drm_dp_aux - DisplayPort AUX channel + * @ddc: I2C adapter that can be used for I2C-over-AUX communication + * @dev: pointer to struct device that is the parent for this AUX channel + * @transfer: transfers a message representing a single AUX transaction + */ +struct drm_dp_aux { + struct i2c_adapter ddc; + struct device *dev; + + ssize_t (*transfer)(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg); +}; + +ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); +ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); + +/** + * drm_dp_dpcd_readb() - read a single byte from the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the register to read + * @valuep: location where the value of the register will be stored + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, + unsigned int offset, u8 *valuep) +{ + return drm_dp_dpcd_read(aux, offset, valuep, 1); +} + +/** + * drm_dp_dpcd_writeb() - write a single byte to the DPCD + * @aux: DisplayPort AUX channel + * @value: value to write to the register + * @offset: address of the register to write + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, u8 value, + unsigned int offset) +{ + return drm_dp_dpcd_write(aux, offset, &value, 1); +} + +int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, + u8 status[DP_LINK_STATUS_SIZE]); + +/* + * DisplayPort link + */ +#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) + +struct drm_dp_link { + unsigned int rate; + unsigned int num_lanes; + unsigned long capabilities; +}; + +int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); +int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); + +int drm_dp_aux_register_i2c_bus(struct drm_dp_aux *aux); +void drm_dp_aux_unregister_i2c_bus(struct drm_dp_aux *aux); + #endif /* _DRM_DP_HELPER_H_ */ diff --git a/include/drm/drm_flip_work.h b/include/drm/drm_flip_work.h index 35c776ae7d3b..9eed34dcd6af 100644 --- a/include/drm/drm_flip_work.h +++ b/include/drm/drm_flip_work.h @@ -57,6 +57,7 @@ typedef void (*drm_flip_func_t)(struct drm_flip_work *work, void *val); * @count: number of committed items * @func: callback fxn called for each committed item * @worker: worker which calls @func + * @fifo: queue of committed items */ struct drm_flip_work { const char *name; diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index c2ab77add67c..898c4c4da552 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -34,6 +34,11 @@ struct drm_panel_funcs { int (*disable)(struct drm_panel *panel); int (*enable)(struct drm_panel *panel); int (*get_modes)(struct drm_panel *panel); + + int (*get_brightness_range)(struct drm_panel *panel, uint64_t *min, + uint64_t *max); + int (*get_brightness)(struct drm_panel *panel, uint64_t *value); + int (*set_brightness)(struct drm_panel *panel, uint64_t value); }; struct drm_panel { @@ -62,6 +67,33 @@ static inline int drm_panel_enable(struct drm_panel *panel) return panel ? -ENOSYS : -EINVAL; } +static inline int drm_panel_get_brightness_range(struct drm_panel *panel, + uint64_t *min, uint64_t *max) +{ + if (panel && panel->funcs && panel->funcs->get_brightness_range) + return panel->funcs->get_brightness_range(panel, min, max); + + return panel ? -ENOSYS : -EINVAL; +} + +static inline int drm_panel_get_brightness(struct drm_panel *panel, + uint64_t *value) +{ + if (panel && panel->funcs && panel->funcs->get_brightness) + return panel->funcs->get_brightness(panel, value); + + return panel ? -ENOSYS : -EINVAL; +} + +static inline int drm_panel_set_brightness(struct drm_panel *panel, + uint64_t value) +{ + if (panel && panel->funcs && panel->funcs->set_brightness) + return panel->funcs->set_brightness(panel, value); + + return panel ? -ENOSYS : -EINVAL; +} + void drm_panel_init(struct drm_panel *panel); int drm_panel_add(struct drm_panel *panel); |