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/*
* QEMU ATI SVGA emulation
*
* Copyright (c) 2019 BALATON Zoltan
*
* This work is licensed under the GNU GPL license version 2 or later.
*/
#ifndef ATI_INT_H
#define ATI_INT_H
#include "hw/pci/pci.h"
#include "vga_int.h"
/*#define DEBUG_ATI*/
#ifdef DEBUG_ATI
#define DPRINTF(fmt, ...) printf("%s: " fmt, __func__, ## __VA_ARGS__)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define PCI_VENDOR_ID_ATI 0x1002
/* Rage128 Pro GL */
#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
/* Radeon RV100 (VE) */
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#define TYPE_ATI_VGA "ati-vga"
#define ATI_VGA(obj) OBJECT_CHECK(ATIVGAState, (obj), TYPE_ATI_VGA)
typedef struct ATIVGARegs {
uint32_t mm_index;
uint32_t bios_scratch[8];
uint32_t crtc_gen_cntl;
uint32_t crtc_ext_cntl;
uint32_t dac_cntl;
uint32_t crtc_h_total_disp;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_offset;
uint32_t crtc_offset_cntl;
uint32_t crtc_pitch;
uint32_t cur_offset;
uint32_t cur_hv_pos;
uint32_t cur_hv_offs;
uint32_t cur_color0;
uint32_t cur_color1;
uint32_t dst_offset;
uint32_t dst_pitch;
uint32_t dst_tile;
uint32_t dst_width;
uint32_t dst_height;
uint32_t src_offset;
uint32_t src_pitch;
uint32_t src_tile;
uint32_t src_x;
uint32_t src_y;
uint32_t dst_x;
uint32_t dst_y;
uint32_t dp_gui_master_cntl;
uint32_t dp_brush_bkgd_clr;
uint32_t dp_brush_frgd_clr;
uint32_t dp_src_frgd_clr;
uint32_t dp_src_bkgd_clr;
uint32_t dp_cntl;
uint32_t dp_datatype;
uint32_t dp_mix;
uint32_t dp_write_mask;
uint32_t default_offset;
uint32_t default_pitch;
uint32_t default_sc_bottom_right;
} ATIVGARegs;
typedef struct ATIVGAState {
PCIDevice dev;
VGACommonState vga;
char *model;
uint16_t dev_id;
uint8_t mode;
bool cursor_guest_mode;
uint16_t cursor_size;
uint32_t cursor_offset;
QEMUCursor *cursor;
MemoryRegion io;
MemoryRegion mm;
ATIVGARegs regs;
} ATIVGAState;
const char *ati_reg_name(int num);
void ati_2d_blt(ATIVGAState *s);
#endif /* ATI_INT_H */
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