diff options
| author | Kevin Brace <kevinbrace@gmx.com> | 2017-07-04 13:06:12 -0500 |
|---|---|---|
| committer | Kevin Brace <kevinbrace@gmx.com> | 2017-07-04 13:06:12 -0500 |
| commit | 5331a19fda4ee75ff3699d53921d85d3bc950ba7 (patch) | |
| tree | d7a08f1cfdde61d748787b911369ccb324ec8379 | |
| parent | d1d0f475b1e1326df299bdd162e782b9378ecfff (diff) | |
Added via_dvp0_set_clock_drive_strength
This is an inline function.
Signed-off-by: Kevin Brace <kevinbrace@gmx.com>
| -rw-r--r-- | drivers/gpu/drm/via/crtc_hw.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h index 9885f5ce5235..f9a7588f57a1 100644 --- a/drivers/gpu/drm/via/crtc_hw.h +++ b/drivers/gpu/drm/via/crtc_hw.h @@ -113,6 +113,25 @@ via_dvp0_set_io_pad_state(void __iomem *regs, u8 io_pad_state) } /* + * Sets DVP0 (Digital Video Port 0) clock I/O pad drive strength. + */ +static inline void +via_dvp0_set_clock_drive_strength(void __iomem *regs, + u8 clock_drive_strength) +{ + /* 3C5.1E[2] - DVP0 Clock Drive Strength Bit [0] */ + svga_wseq_mask(regs, 0x1E, + clock_drive_strength << 2, BIT(2)); + + /* 3C5.2A[4] - DVP0 Clock Drive Strength Bit [1] */ + svga_wseq_mask(regs, 0x2A, + clock_drive_strength << 3, BIT(4)); + + DRM_DEBUG_KMS("DVP0 Clock I/O Pad Drive Strength: %lu\n", + clock_drive_strength & (BIT(1) | BIT(0))); +} + +/* * Sets the display source of DVP0 (Digital Video Port 0) interface. */ static inline void |