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<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="tasks.xsl"?>
<tasks name="NIR Optimization and Implementation Checklist">
  <category name="General">
    <task name="MemoryCleanup" mesa="done">
      Clean up the way we use ralloc contexts so that we can more easiliy
      clean up memory as we optimize.  This may involve changing the way we
      allocate things or it may mean that we just write a mark-and-sweep
      memory clean-up pass.
    </task>
    <task name="Copying" mesa="done">
      Add functions for copying a NIR instruction, function, or shader.
    </task>
    <task name="64-bit" mesa="done">
      Figure out how to represent/validate non-32-bit instructions.  This
      will be needed for ARB_gpu_shader_fp64 as well as fp16 and the
      variably sized integer extensions.
    </task>
  </category>
  <category name="Back-end/Front-end Support">
    <task name="ScalarVS" mesa="done">
      Add support for scalar vertex shaders.
    </task>
    <task name="ScalarGS" mesa="done">
      Add support for scalar geometry shaders.
    </task>
    <task name="Gen5" mesa="done">
      Add support for Gen 4/5 hardware.  This is mostly a matter of adding
      the code to properly resolve booleans.
    </task>
    <task name="vec4" mesa="done">
      Add a vec4 backend for i965.
    </task>
    <task name="ARBfp" mesa="done">
      Add support for ARB fragment programs.
    </task>
    <task name="ARBvp" mesa="done">
      Add support for ARB vertex programs.
    </task>
    <task name="fs-indirect" mesa="no">
      Add support for indirect local variable accesses to the i965 FS
      back-end.  We already do this in vec4 by using our spill
      scratch-space.  We could do the same for the FS back-end.
    </task>
    <task name="PushConstants" mesa="no">
      Add an analysis pass to sort uniforms by "cost" and add proper push
      constant support in the i965 NIR backend.
    </task>
  </category>
  <category name="Optimization and Analysis Passes">
    <task name="GCM" mesa="done">
      Implement a Global Code Motion pass.
    </task>
    <task name="GVN" mesa="done">
      Implement a Global Value Numbering pass.
    </task>
    <task name="uniform" mesa="no">
      Implement a uniform analysis pass.
    </task>
    <task name="DCF" mesa="done">
      Implement a dead/constant control-flow pass.
    </task>
    <task name="range" mesa="no">
      Implement a control-flow and range analysis pass.
    </task>
    <task name="indirect" mesa="done">
      Port the indirect local variable lowering pass to NIR.  We have a
      pass right now that lowers indirect local variable accesses to
      binary-search if-ladders.  It would be nice to be able to do that in
      NIR so that NIR's superior alias analysis can be put to good use.
    </task>
    <task name="phiCSE" mesa="done">
      Add phi nodes to the CSE pass.
    </task>
    <task name="RemovePhi" mesa="done">
      Implement a pass that removes pointless phi nodes.  After copy
      propagation and other optimization passes happen, it's easy to end up
      with phi nodes with all sources the same.  In this case, we can just
      remove the phi node entirely and replace every use of its definition
      with the common source.
    </task>
  </category>
  <category name="Wishlist">
    <task name="i965-FS-SSA" mesa="no">
      Convert the i965 FS backend to use SSA
    </task>
  </category>
</tasks>