Adapt to actually released register specs.

2 files changed, 8 insertions, 79 deletions

diff --git a/r600_init.c b/r600_init.c
index cf3ab05..0927e19 100644
--- a/r600_init.c
+++ b/r600_init.c
@@ -601,8 +601,11 @@ void set_default_state(adapter_t *adapt)
     // ASIC specific setup, see drm
     CMD_BUFFER_ALLOC (5*2);
     if (adapt->chipset <= CHIPSET_RV670) {
+/*
+ * This should either be TA_CNTL, or nuked, or the argument adapted.
 	EREG  (TA_CNTL_AUX,                     (( 3 << GRADIENT_CREDIT_shift)		|
 						 (28 << TD_FIFO_CREDIT_shift)));
+ */
 	EREG  (VC_ENHANCE,                      0);
 	EREG  (R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
 	EREG  (DB_DEBUG,                        0x82000000); /* ? */
@@ -613,8 +616,11 @@ void set_default_state(adapter_t *adapt)
 						 (16 << DEPTH_CACHELINE_FREE_shift)	|
 						 0));
     } else {
+/*
+ * This should either be TA_CNTL, or nuked, or the argument adapted.
 	EREG (TA_CNTL_AUX,                      (( 2 << GRADIENT_CREDIT_shift)		|
 						 (28 << TD_FIFO_CREDIT_shift)));
+ */
 	EREG (VC_ENHANCE,                       0);
 	EREG (R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
 	EREG (DB_DEBUG,                         0);
diff --git a/r600_reg_auto_r6xx.h b/r600_reg_auto_r6xx.h
index 9d5aa3c..714ea48 100644
--- a/r600_reg_auto_r6xx.h
+++ b/r600_reg_auto_r6xx.h
@@ -217,9 +217,6 @@ enum {
 	ALU_MAX_ONE_WATERFALL_bit                         = 1 << 6,
 	CLAUSE_SEQ_PRIO_mask                              = 0x03 << 8,
 	CLAUSE_SEQ_PRIO_shift                             = 8,
-	    SQ_CL_PRIO_RND_ROBIN                          = 0x00,
-	    SQ_CL_PRIO_MACRO_SEQ                          = 0x01,
-	    SQ_CL_PRIO_NONE                               = 0x02,
 	PS_PRIO_mask                                      = 0x03 << 24,
 	PS_PRIO_shift                                     = 24,
 	VS_PRIO_mask                                      = 0x03 << 26,
@@ -1070,15 +1067,6 @@ enum {
     TD0_STATUS                                            = 0x000094a4,
 	TD0_STATUS_num                                    = 4,
 	BUSY_bit                                          = 1 << 31,
-    TA_CNTL                                               = 0x00009504,
-	GRADIENT_CREDIT_mask                              = 0x1f << 0,
-	GRADIENT_CREDIT_shift                             = 0,
-	WALKER_CREDIT_mask                                = 0x1f << 8,
-	WALKER_CREDIT_shift                               = 8,
-	ALIGNER_CREDIT_mask                               = 0x1f << 16,
-	ALIGNER_CREDIT_shift                              = 16,
-	TD_FIFO_CREDIT_mask                               = 0x3ff << 22,
-	TD_FIFO_CREDIT_shift                              = 22,
     TA_CNTL_AUX                                           = 0x00009508,
 	DISABLE_CUBE_WRAP_bit                             = 1 << 0,
 	SYNC_GRADIENT_bit                                 = 1 << 24,
@@ -1193,71 +1181,11 @@ enum {
 	HIT_ARB_MODE_bit                                  = 1 << 16,
 	DISABLE_WRITE_DELAY_bit                           = 1 << 17,
 	HIT_FIFO_DEPTH_bit                                = 1 << 18,
-    VC_CNTL                                               = 0x00009700,
-	L2_INVALIDATE_bit                                 = 1 << 0,
-	RESERVED_bit                                      = 1 << 1,
-	CC_FORCE_MISS_bit                                 = 1 << 2,
-	MI_CHAN_SEL_mask                                  = 0x03 << 3,
-	MI_CHAN_SEL_shift                                 = 3,
-	    X_MC0_USES_CH_0_1                             = 0x00,
-	    X_MC0_USES_CH_0_3                             = 0x01,
-	    X_VC_MC0_IS_ACTIVE                            = 0x02,
-	    X_VC_MC1_IS_DISABLED                          = 0x03,
-	MI_STEER_DISABLE_bit                              = 1 << 5,
-	MI_CREDIT_CTR_mask                                = 0x0f << 6,
-	MI_CREDIT_CTR_shift                               = 6,
-	MI_CREDIT_WE_bit                                  = 1 << 10,
-	MI_REQ_STALL_THLD_mask                            = 0x07 << 11,
-	MI_REQ_STALL_THLD_shift                           = 11,
-	    X_LATENCY_EXCEEDS_399_CLOCKS                  = 0x00,
-	    X_LATENCY_EXCEEDS_415_CLOCKS                  = 0x01,
-	    X_LATENCY_EXCEEDS_431_CLOCKS                  = 0x02,
-	    X_LATENCY_EXCEEDS_447_CLOCKS                  = 0x03,
-	    X_LATENCY_EXCEEDS_463_CLOCKS                  = 0x04,
-	    X_LATENCY_EXCEEDS_479_CLOCKS                  = 0x05,
-	    X_LATENCY_EXCEEDS_495_CLOCKS                  = 0x06,
-	    X_LATENCY_EXCEEDS_511_CLOCKS                  = 0x07,
-	VC_CNTL__MI_TIMESTAMP_RES_mask                    = 0x1f << 14,
-	VC_CNTL__MI_TIMESTAMP_RES_shift                   = 14,
-	    X_1X_SYSTEM_CLOCK                             = 0x00,
-	    X_2X_SYSTEM_CLOCK                             = 0x01,
-	    X_4X_SYSTEM_CLOCK                             = 0x02,
-	    X_8X_SYSTEM_CLOCK                             = 0x03,
-	    X_16X_SYSTEM_CLOCK                            = 0x04,
-	    X_32X_SYSTEM_CLOCK                            = 0x05,
-	    X_64X_SYSTEM_CLOCK                            = 0x06,
-	    X_128X_SYSTEM_CLOCK                           = 0x07,
-	    X_256X_SYSTEM_CLOCK                           = 0x08,
-	    X_512X_SYSTEM_CLOCK                           = 0x09,
-	    X_1024X_SYSTEM_CLOCK                          = 0x0a,
-	    X_2048X_SYSTEM_CLOCK                          = 0x0b,
-	    X_4092X_SYSTEM_CLOCK                          = 0x0c,
-	    X_8192X_SYSTEM_CLOCK                          = 0x0d,
-	    X_16384X_SYSTEM_CLOCK                         = 0x0e,
-	    X_32768X_SYSTEM_CLOCK                         = 0x0f,
     VC_CNTL_STATUS                                        = 0x00009704,
 	RP_BUSY_bit                                       = 1 << 0,
 	RG_BUSY_bit                                       = 1 << 1,
 	VC_BUSY_bit                                       = 1 << 2,
 	CLAMP_DETECT_bit                                  = 1 << 3,
-    VC_CONFIG                                             = 0x00009718,
-	WRITE_DIS_bit                                     = 1 << 0,
-	GPR_DATA_PHASE_ADJ_mask                           = 0x07 << 1,
-	GPR_DATA_PHASE_ADJ_shift                          = 1,
-	    X_LATENCY_BASE_0_CYCLES                       = 0x00,
-	    X_LATENCY_BASE_1_CYCLES                       = 0x01,
-	    X_LATENCY_BASE_2_CYCLES                       = 0x02,
-	    X_LATENCY_BASE_3_CYCLES                       = 0x03,
-	TD_SIMD_SYNC_ADJ_mask                             = 0x07 << 4,
-	TD_SIMD_SYNC_ADJ_shift                            = 4,
-	    X_0_CYCLES_DELAY                              = 0x00,
-	    X_1_CYCLES_DELAY                              = 0x01,
-	    X_2_CYCLES_DELAY                              = 0x02,
-	    X_3_CYCLES_DELAY                              = 0x03,
-	    X_4_CYCLES_DELAY                              = 0x04,
-	    X_5_CYCLES_DELAY                              = 0x05,
-	    X_6_CYCLES_DELAY                              = 0x06,
-	    X_7_CYCLES_DELAY                              = 0x07,
     SMX_DC_CTL0                                           = 0x0000a020,
 	WR_GATHER_STREAM0_bit                             = 1 << 0,
 	WR_GATHER_STREAM1_bit                             = 1 << 1,
@@ -1294,11 +1222,6 @@ enum {
 	FLUSH_ALL_bit                                     = 1 << 4,
 	FLUSH_GS_THREADS_bit                              = 1 << 8,
 	FLUSH_ES_THREADS_bit                              = 1 << 9,
-    SMX_DC_MC_INTF_CTL                                    = 0x0000a02c,
-	MC_RD_REQ_CRED_mask                               = 0xff << 0,
-	MC_RD_REQ_CRED_shift                              = 0,
-	MC_WR_REQ_CRED_mask                               = 0xff << 16,
-	MC_WR_REQ_CRED_shift                              = 16,
     TD_PS_SAMPLER0_BORDER_RED                             = 0x0000a400,
 	TD_PS_SAMPLER0_BORDER_RED_num                     = 18,
 	TD_PS_SAMPLER0_BORDER_RED_offset                  = 16,
@@ -2489,8 +2412,8 @@ enum {
 	FORCE_EOV_REZ_ENABLE_bit                          = 1 << 16,
 	PS_ITER_SAMPLE_bit                                = 1 << 17,
     VGT_ENHANCE                                           = 0x00028a50,
-	VGT_ENHANCE__MI_TIMESTAMP_RES_mask                = 0x03 << 0,
-	VGT_ENHANCE__MI_TIMESTAMP_RES_shift               = 0,
+	MI_TIMESTAMP_RES_mask                             = 0x03 << 0,
+	MI_TIMESTAMP_RES_shift                            = 0,
 	    X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32   = 0x00,
 	    X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16   = 0x01,
 	    X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8    = 0x02,