Proper flush_gpu_source_cache().

Also called on upload(), no need for extra syncs.
Remove cp_set_surface_sync(), except for _pm4.c

6 files changed, 58 insertions, 36 deletions

diff --git a/r600_exa.c b/r600_exa.c
index 16bf714..e6d860c 100644
--- a/r600_exa.c
+++ b/r600_exa.c
@@ -251,9 +251,6 @@ R600PrepareSolid(adapter_t *adapt, int alu, uint32_t pm, uint32_t fg)
 
     /* Init */
     start_3d(adapt);
-
-    cp_set_surface_sync();
-
     set_default_state(adapt);
 
     /* Scissor / viewport */
@@ -748,9 +745,6 @@ R600PrepareCopy(adapter_t *adapt,
 
     /* Init */
     start_3d(adapt);
-
-    cp_set_surface_sync();
-
     set_default_state(adapt);
 
     /* Scissor / viewport */
diff --git a/r600_init.c b/r600_init.c
index 0927e19..24e2e51 100644
--- a/r600_init.c
+++ b/r600_init.c
@@ -294,26 +294,6 @@ void set_depth_target(adapter_t *adapt, db_config_t *db_conf)
 			   (0 << SLICE_MAX_shift)));
 }
 
-void cp_set_surface_sync()
-{
-    CMD_BUFFER_PREAMBLE (4*2 + 7 + 2 + 2);
-
-    EREG  (CP_COHER_CNTL,                       0x19800000);
-    EREG  (CP_COHER_SIZE,                       0xFFFFFFFF);
-    EREG  (CP_COHER_BASE,                       0x00000000);
-    PACK3 (IT_WAIT_REG_MEM, 6);
-    E32   (0x00000003);						// ME, Register, EqualTo
-    E32   (CP_COHER_STATUS >> 2);
-    E32   (0);
-    E32   (0);							// Ref value
-    E32   (STATUS_bit);						// Ref mask
-    E32   (10);							// Wait interval
-    PACK3 (IT_EVENT_WRITE, 1);
-    E32   (PIPELINESTAT_STOP);
-    PACK3 (IT_EVENT_WRITE, 1);
-    E32   (PERFCOUNTER_STOP);
-}
-
 void fs_setup(adapter_t *adapt, shader_config_t *fs_conf)
 {
     uint32_t sq_pgm_resources;
diff --git a/r600_init.h b/r600_init.h
index e65a346..4fe1474 100644
--- a/r600_init.h
+++ b/r600_init.h
@@ -38,7 +38,6 @@ void reset_bool_loop_const (adapter_t *adapt);
 void sq_setup (adapter_t *adapt, sq_config_t *sq_conf);
 void set_render_target (adapter_t *adapt, cb_config_t *cb_conf);
 void set_depth_target (adapter_t *adapt, db_config_t *db_conf);
-void cp_set_surface_sync (void);
 void fs_setup (adapter_t *adapt, shader_config_t *fs_conf);
 void vs_setup (adapter_t *adapt, shader_config_t *vs_conf);
 void ps_setup (adapter_t *adapt, shader_config_t *ps_conf);
diff --git a/r600_lib.c b/r600_lib.c
index 7e59a7f..946238c 100644
--- a/r600_lib.c
+++ b/r600_lib.c
@@ -205,19 +205,46 @@ void flush_cmds (void)
 }
 
 
-void flush_gpu_input_cache (void)
+void flush_gpu_source_cache (adapter_t *adapt, uint64_t lower, uint64_t upper)
 {
     /* To be used after texture uploads etc. */
-    pack3 (IT_SURFACE_SYNC, 4);
-    e32   (TC_ACTION_ENA_bit | VC_ACTION_ENA_bit | SH_ACTION_ENA_bit | CR0_ACTION_ENA_bit);
-    e32   (0xffffffff);			/* SIZE */
-    e32   (0);				/* BASE */
-    e32   (1);				/* POLL_INTERVAL useful value? */
+#if 0
+    CMD_BUFFER_PREAMBLE (3*2 + 7);
+    lower = lower & ~0xffULL;
+    upper = (upper + 0xff) & ~0xffULL;
+
+    EREG  (CP_COHER_CNTL,                       TC_ACTION_ENA_bit | VC_ACTION_ENA_bit |
+						CB_ACTION_ENA_bit | DB_ACTION_ENA_bit |
+						SH_ACTION_ENA_bit | SMX_ACTION_ENA_bit);
+    EREG  (CP_COHER_SIZE,			(upper - lower) >> 8);
+    EREG  (CP_COHER_BASE,			lower >> 8);
+    PACK3 (IT_WAIT_REG_MEM, 6);
+    E32   (0x00000003);						// ME, Register, EqualTo
+    E32   (CP_COHER_STATUS >> 2);
+    E32   (0);
+    E32   (0);							// Ref value
+    E32   (STATUS_bit);						// Ref mask
+    E32   (10);							// Wait interval
+#endif
+    CMD_BUFFER_PREAMBLE (5);
+    lower = lower & ~0xffULL;
+    upper = (upper + 0xff) & ~0xffULL;
+    if (verbose >= 1)
+	printf ("  GPU source cache clear %08x00 - %08x00\n",
+		(uint32_t) (lower >> 8), (uint32_t)(upper >> 8));
+
+    PACK3 (IT_SURFACE_SYNC, 4);
+    E32   (TC_ACTION_ENA_bit | VC_ACTION_ENA_bit | CB_ACTION_ENA_bit | DB_ACTION_ENA_bit |
+	   SH_ACTION_ENA_bit | SMX_ACTION_ENA_bit);	/* CNTL */
+    E32   ((upper-lower) >> 8);		/* SIZE */
+    E32   (lower >> 8);			/* BASE */
+    E32   (10);				/* POLL_INTERVAL */
 }
 
 
-void flush_gpu_output_cache (void)
+void flush_gpu_dest_cache (adapter_t *adapt, uint64_t lower, uint64_t upper)
 {
+    // TODO: not correct at all yet
     /* To be used before readpixels, copy-to-texture etc. */
     pack3 (IT_SURFACE_SYNC, 4);
     e32   (TC_ACTION_ENA_bit | VC_ACTION_ENA_bit | SH_ACTION_ENA_bit | CR0_ACTION_ENA_bit);
@@ -255,6 +282,7 @@ uint64_t upload (adapter_t *adapt, void *shader, int size, int offset)
 	if ((i & 7) != 0)
 	    printf ("\n");
     }
+    flush_gpu_source_cache (adapt, addr, addr + size);
     return addr;
 }
 
diff --git a/r600_lib.h b/r600_lib.h
index ea8eaa9..c28f406 100644
--- a/r600_lib.h
+++ b/r600_lib.h
@@ -98,8 +98,9 @@ extern uint32_t  *vtx, *tex;
 extern uint64_t  vtx_gpu, tex_gpu;
 
 
-void flush_gpu_input_cache (void);
-void flush_gpu_output_cache (void);
+void flush_gpu_source_cache (adapter_t *adapt, uint64_t lower, uint64_t upper);
+void flush_gpu_dest_cache   (adapter_t *adapt, uint64_t lower, uint64_t upper);
+#define FLUSH_GPU_ALL_SOURCE_CACHE(adapt) flush_gpu_source_cache (adapt, 0, 0xffffffff00ULL)
 
 uint64_t upload (adapter_t *adapt, void *shader, int size, int offset);
 void dump_shader (adapter_t *adapt, uint32_t *shader, int size, char *what);
diff --git a/r600_pm4.c b/r600_pm4.c
index 3799786..deb849e 100644
--- a/r600_pm4.c
+++ b/r600_pm4.c
@@ -38,6 +38,26 @@
 #include "r600_shader.h"
 
 
+void cp_set_surface_sync()
+{
+    CMD_BUFFER_PREAMBLE (4*2 + 7 + 2 + 2);
+
+    EREG  (CP_COHER_CNTL,			0x19800000);
+    EREG  (CP_COHER_SIZE,			0xFFFFFFFF);
+    EREG  (CP_COHER_BASE,			0x00000000);
+    PACK3 (IT_WAIT_REG_MEM, 6);
+    E32   (0x00000003);						// ME, Register, EqualTo
+    E32   (CP_COHER_STATUS >> 2);
+    E32   (0);
+    E32   (0);							// Ref value
+    E32   (STATUS_bit);						// Ref mask
+    E32   (10);							// Wait interval
+    PACK3 (IT_EVENT_WRITE, 1);
+    E32   (PIPELINESTAT_STOP);
+    PACK3 (IT_EVENT_WRITE, 1);
+    E32   (PERFCOUNTER_STOP);
+}
+
 /*
  * Simple triangle test
  */