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71 min.v3dv: support 2712D0HEADmainIago Toral Quiroga2-41/+130
2712D0 has V3D 7.1.10 which included draw index and base vertex in the shader state record packet, shuffling the locations of most of its fields. Handle this at run time by emitting the appropriate packet based on the V3D version since our current versioning framework doesn't support changes based on revision number alone. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
71 min.v3d: support 2712D0Iago Toral Quiroga2-108/+214
2710D0 has V3D 7.1.10 which included draw index and base vertex in the shader state record packet, shuffling the locations of most of its fields. Handle this at run time by emitting the appropriate packet based on the V3D version since our current versoning framework doesn't support changes based on revision number alone. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
71 min.broadcom/cle: fix up shader record for V3D 7.1.10 / 2712D0Iago Toral Quiroga1-0/+63
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29189>
114 min.anv: shader printf exampleLionel Landwerlin1-0/+67
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
114 min.intel/clc: enable printfs supportLionel Landwerlin2-0/+33
Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
114 min.anv: add debug shader printf supportLionel Landwerlin6-4/+193
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
114 min.intel/nir: add printf loweringLionel Landwerlin9-1/+83
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
114 min.intel/compiler: store u_printf_info in prog_dataLionel Landwerlin3-0/+41
So that the driver can decode the printf buffer. We're not going to use the NIR data directly from the driver (Iris/Anv) because the late compile steps might want to add more printfs. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
114 min.intel/nir: add reloc delta to load_reloc_const_intel intrinsicLionel Landwerlin5-7/+10
We'll use the delta for an upcoming internal printf mechanism, where the PARAM_IDX will be the base printf reloc identifier and the BASE will be the string id. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.intel/nir: remove unused prototypesLionel Landwerlin1-4/+0
Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.nir: add a low level printf emission helperLionel Landwerlin2-0/+101
Uses the same memory layout as the print intrinsic lowering. This one just let's you do the emission without having to deal with variables. This useful for debug traces. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.nir: add ptr_bit_size parameter to nir_lower_printfLionel Landwerlin3-1/+4
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.nir: add a base offset for printf indexingLionel Landwerlin5-1/+15
This will allow a driver to use a single table of printf strings across all shaders. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.nir/divergence: add missing load_printf_buffer_addressLionel Landwerlin1-0/+1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
115 min.anv: fix push constant subgroup_id locationLionel Landwerlin1-6/+8
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 7c76125db2 ("anv: use 2 different buffers for surfaces/samplers in descriptor sets") Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
2 hoursfreedreno/devices: Add support for Adreno A32 (G3x Gen 2)Danylo Piliaiev1-0/+93
It is based on Adreno 740, with difference in SP_UNKNOWN_AE09 and TPL1_DBG_ECO_CNTL1. We also enable cmdbuf_start_a725_quirk since blob does the same. Values taken from blob v744.19 Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29087>
3 hoursintel/brw: update Xe2 max SIMD message sizesRohan Garg1-1/+1
All the non-transpose messages are SIMD 1,2,4,8,16,32 capable (BSpec 57330) Signed-off-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29212>
4 hoursradv: rename radeon perfctr uconfig helpersSamuel Pitoiset5-17/+17
To match other helpers. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
4 hoursradv: remove redundant radeon_set_perfctr_reg() helperSamuel Pitoiset4-29/+20
It's exactly the same as radeon_set_uconfig_reg_perfctr(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
4 hoursradv: introduce radeon_set_reg_seq()Samuel Pitoiset1-32/+19
This is the base helper for emitting packets, it will be much more closer to the new command buffer recording mecanishm if we decide to use the same helpers as RadeonSI. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
4 hoursradv: stop using radv_physical_device for radeon helpersSamuel Pitoiset3-20/+20
It will be easier to share helpers between RadeonSI and RADV. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29192>
4 hoursrusticl/device: properly handle devices with no support for imagesKarol Herbst1-26/+54
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29205>
4 hoursrusticl/device/caps: move enough for has_imagesKarol Herbst3-40/+43
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29205>
4 hoursrusticl/device: add DeviceCaps and move timestamp stuff into itKarol Herbst3-13/+24
We do query caps quite a lot and this struct should be used to cache results and to make it easier to express more complex dependencies between features (e.g. images being supported or not). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29205>
7 hoursanv/sparse: assert a format can't be standard and non-standardPaulo Zanoni1-0/+1
A format can't be standard and non-standard at the same time. If we ever hit this assertion, it's because something behind the scenes has evolved (such as the tiling formats) so something that was marked as non-standard became standard. Add an assertion so we can quickly catch these issues in the future and adjust the code. I don't want to mix this assertion with the one in the line above since that one is the most useful assertion we have in all the sparse code, so it's good to know which one we're hitting. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv+zink/ci: add failures related to multi-sampled sparse bindingPaulo Zanoni2-1/+22
After enabling multi-sampled sparse binding in Anv, we get these failures. I've investigated them and none are trivial, it's not clear if they're Anv's fault or not, especially considering how many other texture-related failures we already have in this fails.txt file. Since both deqp-vk and Vulkan native apps seem to be working with pure Anv (no Zink), I don't think it's worth blocking multi-sampled sparse on Anv just because of Zink. From what I have investigated, the problems seem related to the following: - glcts is expecting 1D images to have 2D block shapes (this is definitely the case for StandardPageSizesTestCase, we get rid of the failure by either removing sparse support for 1D images or telling their block shapes are the same as the 2D images) - glcts/zink may be trying to use formats that are unsupported by Anv as if they were supported - there's probably something funny going on with the GL_R8 format v2: Adjust test results after merging merging MR 29118. v3: Zink test results are a moving target... Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv: check for VK_RENDERING_SUSPENDING_BIT once at CmdEndRenderingPaulo Zanoni1-92/+94
Most of what we do in this function is conditional to not have VK_RENDERING_SUSPENDING_BIT, so check for it once. Suggested-by: Iván Briano <ivan.briano@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: enable MSAA for Sparse when applicablePaulo Zanoni1-4/+6
The newer platforms can't support 8x and 16x since Tile64's shape for them is not a standard block shape (and claiming standard block shapes is higher priority than supporting things without it). The TileYs platforms are fine. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: flush the tile cache when resolving sparse imagesPaulo Zanoni1-8/+29
Consider the following program: - Uses a multi-sampled image as the color attachment. - Draws simple geometry at the color attachment. - Uses the (non-multi-sampled) swapchain image as the resolve image. - Presents the result. If the color attachment image (the multi-sampled one) is a sparse image and it's fully bound, everything works and this patch is not required. If the image is partially bound (or just completely unbound), without this patch the unbound area of the image that ends up being displayed on the screen is not completely black, and it should be completely black due to the fact that we claim to support residencyNonResidentStrict (which is required by vkd3d for DX12). On DG2, what ends up being displayed in the swapchain image is actually the whole image as if it was completely bound. On TGL the unbound area partially displays the geometry that was supposed to be drawn, but the background is a different color: it's a weird corrupted image. On both platforms the unbound areas should all be fully black. This patch applies the proper flushing so that we get the results we should have. The bug fixed by this patch is not caught by dEQP or anything our CI runs (dEQP does have some checks for residencynonResidentStrict correctness, but none that catch this issue in particular). I was able to catch this with my own sample program. Using INTEL_DEBUG=stall also makes the problem go away. If we had a way to track which images are fully bound we would be able to avoid this flush. I had code for that in the earliest versions of sparse before xe.ko had support for gpuva, but it requires maintaining a bunch of lists, so I'm not sure that's actually worth it. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: exclude Xe2's Tile64's non-standard block shapesPaulo Zanoni1-0/+22
The Tile64 format from Xe2 is weird and some of its MSAA shapes are non-standard. Reject them. Otherwise, we'll get dEQP failures such as: deqp-vk: ../../src/intel/vulkan/anv_sparse.c:829: anv_sparse_calc_image_format_properties: Assertion `is_standard || is_known_nonstandard_format' failed. Many tests can reproduce this issue, including: dEQP-VK.memory.requirements.extended.image.sparse_tiling_optimal Testcase: dEQP-VK.memory.requirements.extended.image.sparse_tiling_optimal Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: fix block_size_B when the image is multi-sampledPaulo Zanoni1-1/+4
This is all that's needed to make anv_sparse_bind_image_memory() work with multi-sampled images. The assert() we just added would have been really helpful when debugging this. All the dEQP tests with "sparse" in their names are passing *even* without this patch. Real-world applications show very clear visual corruption for sparse MSAA images bound through non-opaque binds since only a fraction of the the actual image ends up being bound. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: reject all sample flags that non-sparse doesn't supportPaulo Zanoni1-0/+4
We call anv_get_image_format_properties() from anv_GetPhysicalDeviceSparseImageFormatProperties2() because we want to reject all images that we don't support for the non-sparse case. That function does not take sample counts as its input, it outputs a list of possible sample counts. In this patch we check the sample counts it outputs: if what the user is querying isn't even supported by non-sparse, reject it right away. That saves us from having to code in anv_sparse_image_check_support() cases that are coded elsewhere. Examples include: 1D images and compressed formats. This change affects a number of dEQP tests, including: - dEQP-VK.api.info.sparse_image_format_properties2.1d.optimal.r4g4b4a4_unorm_pack16 - dEQP-VK.api.info.sparse_image_format_properties2.2d.optimal.bc2_srgb_block Without this patch, and with sparse multi-sampling enabled, this would hit the following assertion: anv_formats.c:1903: anv_GetPhysicalDeviceSparseImageFormatProperties2: Assertion `false' failed. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: properly reject sample counts we don't supportPaulo Zanoni1-2/+10
Yes, I understand that this looks like the kind of check that the applications should be doing instead of us, but if we don't that, dEQP will have failures. If we claim support for any multi-sampled sparse feature, dEQP will try to create multi-sampled sparse images with all possible sample counts, including the ones supported by non-sparse but not supported by sparse (x8 and x16 on Tile64 platforms) and also the ones not supported at all, like x32 and x64. This change affects a number of dEQP tests, including: - dEQP-VK.api.info.sparse_image_format_properties2.2d.optimal.r32g32_sfloat Without this patch, and with sparse multi-sampling enabled, this would hit the following assertion: anv_sparse.c:866: anv_sparse_calc_image_format_properties: Assertion `is_standard || is_known_nonstandard_format' failed. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: we can't do multi-sampled depth/stencil sparse imagesPaulo Zanoni1-0/+7
Our hardware has more than one layout for multi-sampled images that use the tiling formats that give us the sparse standard block shapes: see enum isl_msaa_layout. Only the layout we use for colored images is compatible with the standard block shapes, so it's the only one we can expose for multi-sampled sparse. This change affects a number of dEQP tests, including: - dEQP-VK.memory.requirements.create_info.image.sparse_residency_aliased_tiling_optimal Without this patch, and with sparse multi-sampling enabled, this test would hit the following assertion: anv_sparse.c:866: anv_sparse_calc_image_format_properties: Assertion `is_standard || is_known_nonstandard_format' failed. Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursanv/sparse: add the MSAA block shape tablesPaulo Zanoni4-44/+76
We're not enabling sparse on multi-sampled images yet, but having the table here is a first step. The current approach should make the code a little more compact. These tables are in section 33.4.3: Standard Sparse Image Block Shapes of the Vulkan 1.3 spec. PS: I know we've questioned the need for us to have these tables here as they are something dEQP should check, but I've hit the "this shape is not standard" assertion multiple times during development of the various sparse features, and that really helps narrowing down the problems. For example, see the next 2 patches in this MR. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
7 hoursisl: add ISL_TILING_64_XE2 to isl_tiling_to_name()Paulo Zanoni1-0/+1
Fixes: c69650a95e26 ("isl,blorp,anv: introduce ISL_TILING_64_XE2 for Xe2+ platforms") Reviewed-by: Rohan Garg <rohan.garg@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27306>
8 hoursradeonsi: constify struct pipe_vertex_buffer *Marek Olšák3-6/+6
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi/ci: remove some gfx11 flakesMarek Olšák1-2/+0
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi/ci: update failures for all generationsMarek Olšák8-801/+246
This also removes ASTC failures fixed by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28917 Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi/ci: fix caselists for vk-gl-cts/mainMarek Olšák1-8/+8
The files were moved in the repo. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: remove slow code from si_msaa_resolve_blit_via_CBMarek Olšák3-90/+10
This is mainly a cleanup. It wasn't faster. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: replace the clear_12bytes_buffer shader with the DMA compute shaderMarek Olšák3-53/+5
It can handle 12-byte clear values with these trivial changes. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: use set_work_size for all internal compute dispatchesMarek Olšák1-75/+26
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: simplify the complex clear/copy_buffer shaderMarek Olšák4-104/+39
Remove the logic that we don't need. In a future commit, it will be extended to optimize aspects of buffer clears and copies that need to be optimized. Changes: - remove the logic that generated multiple loads/stores per thread, only 1 load and store can occur in the shader now, allowing clearing/ copying max 4 dwords per thread - put the src buffer in SSBO slot 0, and the dst buffer in SSBO slot 1 Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: minor simplifications of clear/copy_buffer shadersMarek Olšák4-45/+21
- always use L2_LRU (never use ACCESS_NON_TEMPORAL) - for better perf - never use ACCESS_COHERENT because the address might not be aligned to a cache line - assume the wave size is always 64 Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: get NIR options from si_screen instead of calling get_compiler_optionsMarek Olšák1-59/+23
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi/gfx11: use a lighter workaround for Navi31 dEQP failuresMarek Olšák1-1/+1
This passes tests. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: set flags directly instead of having needs_db_flushMarek Olšák1-6/+3
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: remove GDS testsMarek Olšák3-100/+0
They were useful in the past. Not anymore. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
8 hoursradeonsi: validate the buffer range in si_set_shader_bufferMarek Olšák1-0/+5
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29053>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-15 15:08:08 +0000