diff options
| author | Connor Abbott <cwabbott0@gmail.com> | 2023-10-31 18:38:01 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-04-26 12:55:13 +0000 |
| commit | c00e06bc62718aa97d9bfb24cfe4e680cbad05c8 (patch) | |
| tree | 2c5ab56da92e37d3b07cbb395dcb8e72786ee709 | |
| parent | b2cf2dfd78db607b2966239afba3a96145a59142 (diff) | |
ir3: Use INVALID_REG in array store
We now use INVALID_REG to mean that a source or destination does not
have a preassigned register. We ignore this for anything but inputs and
outputs for now, but don't make it look like we're preassigning the
array to r0.x. This also will allow us to assert that preassigned
registers are in the correct range.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
| -rw-r--r-- | src/freedreno/ir3/ir3_context.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index 776082076b2..13059d8d6af 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -616,14 +616,14 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n, mov->barrier_class = IR3_BARRIER_ARRAY_W; mov->barrier_conflict = IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W; dst = ir3_dst_create( - mov, 0, + mov, INVALID_REG, IR3_REG_SSA | IR3_REG_ARRAY | flags | COND(address, IR3_REG_RELATIV)); dst->instr = mov; dst->size = arr->length; dst->array.id = arr->id; dst->array.offset = n; dst->array.base = INVALID_REG; - ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->dsts[0]; + ir3_src_create(mov, INVALID_REG, IR3_REG_SSA | flags)->def = src->dsts[0]; if (arr->last_write && arr->last_write->instr->block == block) ir3_reg_set_last_array(mov, dst, arr->last_write); |