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| author | Marek Olšák <marek.olsak@amd.com> | 2016-08-19 16:07:50 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-09-05 15:43:22 +0200 |
| commit | 39fff5996227692cf8b6a75771a28a8d624f16ef (patch) | |
| tree | 1c21ecba11282641d28492b57bb60a0566c152f0 /radeon | |
| parent | 4462303700fd982eb5fdd266ee04d0543f4f6bf0 (diff) | |
radeon: sync radeon_drm.h with the kernel
the CIK tile mode definitions are moved out,
userspace doesn't use them
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Diffstat (limited to 'radeon')
| -rw-r--r-- | radeon/radeon_surface.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 1424660d..16a8b00b 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -42,6 +42,14 @@ #include "radeon_drm.h" #include "radeon_surface.h" +#define CIK_TILE_MODE_COLOR_2D 14 +#define CIK_TILE_MODE_COLOR_2D_SCANOUT 10 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64 0 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128 1 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256 2 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512 3 +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4 + #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1)) #define MAX2(A, B) ((A) > (B) ? (A) : (B)) #define MIN2(A, B) ((A) < (B) ? (A) : (B)) |