diff options
| author | Rex Zhu <Rex.Zhu@amd.com> | 2017-09-20 17:24:58 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 15:14:34 -0400 |
| commit | 95175869bd309c77f8391c6ea2c2ba440d7f9af7 (patch) | |
| tree | a8b38b3ca68bdcbaad4c4a2957ffe705d4372ceb | |
| parent | f0f6e3752a8138342038c89d25856ce28a36160b (diff) | |
drm/amd/powerplay: delete SMUM_SET_FIELD
repeated defining in hwmgr.h
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 12 |
2 files changed, 6 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h index 0bd4476106bf..b742c22bb69b 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h @@ -170,11 +170,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); #define SMUM_READ_FIELD(device, reg, field) \ SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) -#define SMUM_SET_FIELD(value, reg, field, field_val) \ - (((value) & ~SMUM_FIELD_MASK(reg, field)) | \ - (SMUM_FIELD_MASK(reg, field) & ((field_val) << \ - SMUM_FIELD_SHIFT(reg, field)))) - #define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \ SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ reg, field) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c index 9628e0379fd8..efdc1cb7ab63 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c @@ -191,17 +191,17 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr) /* Disable MEC parsing/prefetching */ tmp = cgs_read_register(hwmgr->device, mmCP_MEC_CNTL); - tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); - tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); + tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); + tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); tmp = cgs_read_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); - tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1); cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); reg_data = smu_lower_32_bits(info.mc_addr) & |