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2024-04-23drm/i915/dsi: pass display to register macros instead of implicit variabledrm-intel-next-2024-04-24Jani Nikula4-342/+349
2024-04-23drm/i915/dsi: unify connector/encoder type and name usageJani Nikula1-74/+60
2024-04-23drm/i915/dsi: add VLV_ prefix to VLV only register macrosJani Nikula2-5/+5
2024-04-23drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definitionJani Nikula1-3/+0
2024-04-22drm/i915/display: move dmc_firmware_path to display paramsJani Nikula6-9/+6
2024-04-22drm/i915/dmc: change how to disable DMC firmware using module paramJani Nikula2-10/+24
2024-04-22drm/i915/dmc: split out per-platform firmware path selectionJani Nikula1-42/+54
2024-04-22drm/i915/dmc: improve firmware parse failure propagationJani Nikula1-17/+24
2024-04-22drm/i915/dmc: handle request_firmware() errors separatelyJani Nikula1-2/+9
2024-04-19drm/i915: Enable per-lane DP drive settings for bxt/glkVille Syrjälä1-1/+1
2024-04-19drm/i915/dpio: Program bxt/glk PHY TX registers per-laneVille Syrjälä1-13/+22
2024-04-19drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuffVille Syrjälä5-102/+102
2024-04-19drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setupVille Syrjälä1-9/+3
2024-04-19drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp()Ville Syrjälä1-22/+39
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä8-262/+279
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä5-35/+35
2024-04-19drm/i915/dpio: Clean up bxt/glk PHY registersVille Syrjälä2-59/+59
2024-04-19drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR ratesImre Deak2-4/+20
2024-04-19drm/i915/dp_mst: Make HBLANK expansion quirk work for logical portsImre Deak1-6/+16
2024-04-19drm/dp_mst: Add drm_dp_mst_aux_for_parent()Imre Deak2-0/+17
2024-04-19drm/dp_mst: Factor out drm_dp_mst_port_is_logical()Imre Deak2-3/+9
2024-04-19drm/dp: Add drm_dp_128b132b_supported()Imre Deak2-1/+7
2024-04-19drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limitImre Deak1-39/+39
2024-04-19drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTLImre Deak1-1/+1
2024-04-19drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limitImre Deak1-2/+21
2024-04-19drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bppImre Deak1-1/+1
2024-04-19drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limitImre Deak1-2/+1
2024-04-19drm/i915/dp: Fix DSC line buffer depth programmingImre Deak2-13/+6
2024-04-19drm/i915/display: force qgv check after the hw state readoutVinod Govindapillai2-2/+12
2024-04-19drm/i915/display: handle systems with duplicate psf gv pointsStanislav Lisovskiy1-0/+2
2024-04-19drm/i915/display: Disable SAGV on bw init, to force QGV point recalculationStanislav Lisovskiy3-4/+49
2024-04-19drm/i915/display: extract code to prepare qgv points maskVinod Govindapillai1-5/+11
2024-04-19drm/i915/display: Extract code required to calculate max qgv/psf gv pointStanislav Lisovskiy1-30/+50
2024-04-19drm/i915/display: Add meaningful traces for QGV point info error handlingStanislav Lisovskiy2-1/+5
2024-04-18drm/i915/dmc: use struct intel_display moreJani Nikula1-14/+10
2024-04-18drm/i915/de: allow intel_display and drm_i915_private for de functionsJani Nikula1-64/+93
2024-04-18drm/i915/dmc: convert dmc wakelock interface to struct intel_displayJani Nikula6-53/+59
2024-04-18drm/i915/display: rename __intel_wait_for_register_nowl() to indicate intel_de_Jani Nikula2-10/+10
2024-04-18drm/i915/quirks: convert struct drm_i915_private to struct intel_displayJani Nikula7-62/+65
2024-04-18drm/i915/display: accept either i915 or display for feature testsJani Nikula1-2/+3
2024-04-18drm/i915: add generic __to_intel_display()Jani Nikula1-0/+22
2024-04-18drm/i915/display: add generic to_intel_display() macroJani Nikula1-0/+37
2024-04-18drm/i915/display: add intel_display -> drm_device backpointerJani Nikula2-0/+6
2024-04-18drm/i915: use system include for drm headersJani Nikula1-1/+1
2024-04-18drm/i915: limit eDP MSO pipe only for display version 20 and belowLuca Coelho1-2/+7
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä6-60/+58
2024-04-17drm/i915: Unionize dpll_hw_stateVille Syrjälä1-5/+7
2024-04-17drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä6-95/+160
2024-04-17drm/i915: Add local DPLL 'hw_state' variablesVille Syrjälä1-46/+56
2024-04-17drm/i915: s/pipe_config/crtc_state/ in legacy PLL codeVille Syrjälä2-18/+18
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-10 04:20:02 +0000