diff options
| author | Jerome Glisse <glisse@freedesktop.org> | 2007-06-28 01:12:23 +0200 |
|---|---|---|
| committer | Jerome Glisse <glisse@freedesktop.org> | 2007-06-28 01:12:23 +0200 |
| commit | 4bae344da3ebdc1952962ecacd5a80a7dde1dd0b (patch) | |
| tree | 8a263c3e2fec731d354616bfe9f02d1bbbfabb2f /include | |
| parent | 14e502a548b5cb3b9bc8a0ba47317cd673806364 (diff) | |
avivo: change pll computation to meet new constraint.
It seems that AVIVO_PLL_POST_DIVIDER * AVIVO_PLL_DIVIDER needs
to be above 40 for PLL stability, changed PLL computation to
meet this. This seems to improve image stability and should fix
couple of bad behavior.
Diffstat (limited to 'include')
| -rw-r--r-- | include/radeon_reg.h | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/include/radeon_reg.h b/include/radeon_reg.h index cf46a55..3b4ee8c 100644 --- a/include/radeon_reg.h +++ b/include/radeon_reg.h @@ -3192,17 +3192,9 @@ * (vclk is video mode clock) * vclk = (1080 * AVIVO_PLL_POST_MUL) / * (AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV * 40) - * - * So computation for register: - * PLL_DIVIDER = 1080 / (vclk) - * PLL_POST_DIV = 2 - * PLL_POST_MUL = (40 * vclk * PLL_DIVIDER * PLL_POST_DIV) / (1080) - * AVIVO_PLL_POST_MUL must be inferior to 255 - * Then you repeat this until you come to the nearest value: - * increment PLL_POST_MUL recompute PLL_POST_DIV - * if new video mode clock value is better keep on otherwise last - * previously found value should be the better. - * Refclk appears to be 108MHz 1080000 / mode clock = this. + * It seems that AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV needs to be + * above 40 and that AVIVO_DIVIDER should be greater than AVIVO_PLL_POST_DIV + * Try to keep this constraint while computing PLL values. */ #define AVIVO_PLL1_POST_DIV_CNTL 0x0400 # define AVIVO_PLL_POST_DIV_EN (1 << 0) |