add sdma 4.2 block and update vega20 to use it

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

10 files changed, 5597 insertions, 2 deletions

diff --git a/scripts/soc15_parse.sh b/scripts/soc15_parse.sh
index c98ddca..438a14a 100644
--- a/scripts/soc15_parse.sh
+++ b/scripts/soc15_parse.sh
@@ -72,6 +72,9 @@ ENDCB
 ) > /tmp/countbits.c
 gcc /tmp/countbits.c -o /tmp/countbits
 
+parse_bits ${pk}/sdma1/sdma1_4_2 src/lib/ip/sdma142
+parse_bits ${pk}/sdma0/sdma0_4_2 src/lib/ip/sdma042
+
 parse_bits ${pk}/dce/dce_12_0 src/lib/ip/dce120
 parse_bits ${pk}/vce/vce_4_0 src/lib/ip/vce40
 parse_bits ${pk}/uvd/uvd_7_0 src/lib/ip/uvd70
diff --git a/src/lib/asic/vega20.c b/src/lib/asic/vega20.c
index 475c1ab..bfc8a76 100644
--- a/src/lib/asic/vega20.c
+++ b/src/lib/asic/vega20.c
@@ -40,8 +40,8 @@ struct umr_asic *umr_create_vega20(struct umr_options *options)
 			umr_create_hdp40(vega20_offs, options),
 			umr_create_nbio61(vega20_offs, options),
 			umr_create_oss40(vega20_offs, options),
-			umr_create_sdma040(vega20_offs, options),
-			umr_create_sdma140(vega20_offs, options),
+			umr_create_sdma042(vega20_offs, options),
+			umr_create_sdma142(vega20_offs, options),
 			umr_create_thm90(vega20_offs, options),
 			umr_create_mmhub10(vega20_offs, options),
 			umr_create_mp90(vega20_offs, options),
diff --git a/src/lib/ip/CMakeLists.txt b/src/lib/ip/CMakeLists.txt
index 5946061..5daa785 100644
--- a/src/lib/ip/CMakeLists.txt
+++ b/src/lib/ip/CMakeLists.txt
@@ -40,7 +40,9 @@ add_library(ip OBJECT
   oss401.c
   sdma040.c
   sdma041.c
+  sdma042.c
   sdma140.c
+  sdma142.c
   smu60.c
   smu700.c
   smu701.c
diff --git a/src/lib/ip/sdma042.c b/src/lib/ip/sdma042.c
new file mode 100644
index 0000000..00480a7
--- /dev/null
+++ b/src/lib/ip/sdma042.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "sdma042_bits.i"
+
+static const struct umr_reg_soc15 sdma042_registers[] = {
+#include "sdma042_regs.i"
+};
+
+struct umr_ip_block *umr_create_sdma042(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "sdma042";
+	ip->no_regs = sizeof(sdma042_registers)/sizeof(sdma042_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+
+	if (umr_transfer_soc15_to_reg(options, soc15_offsets, "SDMA0", sdma042_registers, ip)) {
+		free(ip);
+		return NULL;
+	}
+
+	return ip;
+}
diff --git a/src/lib/ip/sdma042_bits.i b/src/lib/ip/sdma042_bits.i
new file mode 100644
index 0000000..9ec26f7
--- /dev/null
+++ b/src/lib/ip/sdma042_bits.i
@@ -0,0 +1,2246 @@
+static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = {
+	 { "VALUE", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CNTL[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 30, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_CNTL[] = {
+	 { "PRIV", 0, 0, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE0[] = {
+	 { "SDMA0_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR_HI", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_CNTL", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE1[] = {
+	 { "SDMA0_GFX_STATUS", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_GFX_DOORBELL_OFFSET", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
+	 { "VOID_REG2", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_ADDR_HI", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_ADDR_LO", 19, 19, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_AQL_CNTL", 20, 20, &umr_bitfield_default },
+	 { "SDMA0_GFX_MINOR_PTR_UPDATE", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE2[] = {
+	 { "SDMA0_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA6", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA7", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA8", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_CNTL", 9, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE0[] = {
+	 { "SDMA0_UCODE_ADDR", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_UCODE_DATA", 1, 1, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_VM_CNTL", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_LO", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_ACTIVE_FCN_ID", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_VIRT_RESET_REQ", 9, 9, &umr_bitfield_default },
+	 { "RESERVED10", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_CONTEXT_REG_TYPE0", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_CONTEXT_REG_TYPE1", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_CONTEXT_REG_TYPE2", 13, 13, &umr_bitfield_default },
+	 { "SDMA0_CONTEXT_REG_TYPE3", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_PUB_REG_TYPE0", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_PUB_REG_TYPE1", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_PUB_REG_TYPE2", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_PUB_REG_TYPE3", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_MMHUB_CNTL", 19, 19, &umr_bitfield_default },
+	 { "RESERVED_FOR_PSPSMU_ACCESS_ONLY", 20, 24, &umr_bitfield_default },
+	 { "SDMA0_CONTEXT_GROUP_BOUNDARY", 25, 25, &umr_bitfield_default },
+	 { "SDMA0_POWER_CNTL", 26, 26, &umr_bitfield_default },
+	 { "SDMA0_CLK_CTRL", 27, 27, &umr_bitfield_default },
+	 { "SDMA0_CNTL", 28, 28, &umr_bitfield_default },
+	 { "SDMA0_CHICKEN_BITS", 29, 29, &umr_bitfield_default },
+	 { "SDMA0_GB_ADDR_CONFIG", 30, 30, &umr_bitfield_default },
+	 { "SDMA0_GB_ADDR_CONFIG_READ", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE1[] = {
+	 { "SDMA0_RB_RPTR_FETCH_HI", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_SEM_WAIT_FAIL_TIMER_CNTL", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_RB_RPTR_FETCH", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_IB_OFFSET_FETCH", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_PROGRAM", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_STATUS_REG", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_STATUS1_REG", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_RD_BURST_CNTL", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_HBM_PAGE_CONFIG", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_UCODE_CHECKSUM", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_F32_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_FREEZE", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_PHASE0_QUANTUM", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_PHASE1_QUANTUM", 13, 13, &umr_bitfield_default },
+	 { "SDMA_POWER_GATING", 14, 14, &umr_bitfield_default },
+	 { "SDMA_PGFSM_CONFIG", 15, 15, &umr_bitfield_default },
+	 { "SDMA_PGFSM_WRITE", 16, 16, &umr_bitfield_default },
+	 { "SDMA_PGFSM_READ", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_EDC_CONFIG", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_BA_THRESHOLD", 19, 19, &umr_bitfield_default },
+	 { "SDMA0_ID", 20, 20, &umr_bitfield_default },
+	 { "SDMA0_VERSION", 21, 21, &umr_bitfield_default },
+	 { "SDMA0_EDC_COUNTER", 22, 22, &umr_bitfield_default },
+	 { "SDMA0_EDC_COUNTER_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "SDMA0_STATUS2_REG", 24, 24, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_CNTL", 25, 25, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_PREOP_LO", 26, 26, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_PREOP_HI", 27, 27, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_CNTL", 28, 28, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_WATERMK", 29, 29, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_RD_STATUS", 30, 30, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_WR_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE2[] = {
+	 { "SDMA0_UTCL1_INV0", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_INV1", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_INV2", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_RD_XNACK0", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_RD_XNACK1", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_WR_XNACK0", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_WR_XNACK1", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_UTCL1_PAGE", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_POWER_CNTL_IDLE", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_RELAX_ORDERING_LUT", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_CHICKEN_BITS_2", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_STATUS3_REG", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_PHYSICAL_ADDR_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA0_PHYSICAL_ADDR_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_PHASE2_QUANTUM", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_ERROR_LOG", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_PUB_DUMMY_REG0", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_PUB_DUMMY_REG1", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_PUB_DUMMY_REG2", 19, 19, &umr_bitfield_default },
+	 { "SDMA0_PUB_DUMMY_REG3", 20, 20, &umr_bitfield_default },
+	 { "SDMA0_F32_COUNTER", 21, 21, &umr_bitfield_default },
+	 { "SDMA0_PERFMON_CNTL", 23, 23, &umr_bitfield_default },
+	 { "SDMA0_PERFCOUNTER0_RESULT", 24, 24, &umr_bitfield_default },
+	 { "SDMA0_PERFCOUNTER1_RESULT", 25, 25, &umr_bitfield_default },
+	 { "SDMA0_PERFCOUNTER_TAG_DELAY_RANGE", 26, 26, &umr_bitfield_default },
+	 { "SDMA0_CRD_CNTL", 27, 27, &umr_bitfield_default },
+	 { "SDMA0_GPU_IOV_VIOLATION_LOG", 29, 29, &umr_bitfield_default },
+	 { "SDMA0_ULV_CNTL", 30, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE3[] = {
+	 { "SDMA0_EA_DBIT_ADDR_DATA", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_EA_DBIT_ADDR_INDEX", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_MMHUB_CNTL[] = {
+	 { "UNIT_ID", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_GROUP_BOUNDARY[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_POWER_CNTL[] = {
+	 { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "EXT_PG_POWER_ON_REQ", 1, 1, &umr_bitfield_default },
+	 { "EXT_PG_POWER_OFF_REQ", 2, 2, &umr_bitfield_default },
+	 { "ON_OFF_CONDITION_HOLD_TIME", 3, 7, &umr_bitfield_default },
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
+	 { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
+	 { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
+	 { "ON_OFF_STATUS_DURATION_TIME", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UTC_L1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "WRITE_BURST_LENGTH", 8, 9, &umr_bitfield_default },
+	 { "WRITE_BURST_WAIT_CYCLE", 10, 12, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "RAW_CHECK_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+	 { "TIME_BASED_QOS", 25, 25, &umr_bitfield_default },
+	 { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
+	 { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
+	 { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_BANKS", 12, 14, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GB_ADDR_CONFIG_READ[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_BANKS", 12, 14, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "EX_START", 15, 15, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RD_BURST_CNTL[] = {
+	 { "RD_BURST", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUFFER_RD_BURST", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_HBM_PAGE_CONFIG[] = {
+	 { "PAGE_SIZE_EXPONENT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_CHECKSUM[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_FREEZE[] = {
+	 { "PREEMPT", 0, 0, &umr_bitfield_default },
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+	 { "F32_FREEZE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_POWER_GATING[] = {
+	 { "SDMA0_POWER_OFF_CONDITION", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_POWER_ON_CONDITION", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_POWER_OFF_REQ", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_POWER_ON_REQ", 3, 3, &umr_bitfield_default },
+	 { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_READ[] = {
+	 { "VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_BA_THRESHOLD[] = {
+	 { "READ_THRES", 0, 9, &umr_bitfield_default },
+	 { "WRITE_THRES", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VERSION[] = {
+	 { "MINVER", 0, 6, &umr_bitfield_default },
+	 { "MAJVER", 8, 14, &umr_bitfield_default },
+	 { "REV", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EDC_COUNTER[] = {
+	 { "SDMA_UCODE_BUF_SED", 0, 0, &umr_bitfield_default },
+	 { "SDMA_RB_CMD_BUF_SED", 2, 2, &umr_bitfield_default },
+	 { "SDMA_IB_CMD_BUF_SED", 3, 3, &umr_bitfield_default },
+	 { "SDMA_UTCL1_RD_FIFO_SED", 4, 4, &umr_bitfield_default },
+	 { "SDMA_UTCL1_RDBST_FIFO_SED", 5, 5, &umr_bitfield_default },
+	 { "SDMA_DATA_LUT_FIFO_SED", 6, 6, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF0_SED", 7, 7, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF1_SED", 8, 8, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF2_SED", 9, 9, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF3_SED", 10, 10, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF4_SED", 11, 11, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF5_SED", 12, 12, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF6_SED", 13, 13, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF7_SED", 14, 14, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF8_SED", 15, 15, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF9_SED", 16, 16, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF10_SED", 17, 17, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF11_SED", 18, 18, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF12_SED", 19, 19, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF13_SED", 20, 20, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF14_SED", 21, 21, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF15_SED", 22, 22, &umr_bitfield_default },
+	 { "SDMA_SPLIT_DAT_BUF_SED", 23, 23, &umr_bitfield_default },
+	 { "SDMA_MC_WR_ADDR_FIFO_SED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EDC_COUNTER_CLEAR[] = {
+	 { "DUMMY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS2_REG[] = {
+	 { "ID", 0, 1, &umr_bitfield_default },
+	 { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
+	 { "CMD_OP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_CNTL[] = {
+	 { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
+	 { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_HI[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_CNTL[] = {
+	 { "REDO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REDO_DELAY", 1, 10, &umr_bitfield_default },
+	 { "REDO_WATERMK", 11, 13, &umr_bitfield_default },
+	 { "INVACK_DELAY", 14, 23, &umr_bitfield_default },
+	 { "REQL2_CREDIT", 24, 28, &umr_bitfield_default },
+	 { "VADDR_WATERMK", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_WATERMK[] = {
+	 { "REQMC_WATERMK", 0, 8, &umr_bitfield_default },
+	 { "REQPG_WATERMK", 9, 16, &umr_bitfield_default },
+	 { "INVREQ_WATERMK", 17, 24, &umr_bitfield_default },
+	 { "XNACK_WATERMK", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_RD_STATUS[] = {
+	 { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
+	 { "PAGE_NULL", 19, 19, &umr_bitfield_default },
+	 { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
+	 { "CE_L1_STALL", 21, 21, &umr_bitfield_default },
+	 { "NEXT_RD_VECTOR", 22, 25, &umr_bitfield_default },
+	 { "MERGE_STATE", 26, 28, &umr_bitfield_default },
+	 { "ADDR_RD_RTR", 29, 29, &umr_bitfield_default },
+	 { "WPTR_POLLING", 30, 30, &umr_bitfield_default },
+	 { "INVREQ_SIZE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_WR_STATUS[] = {
+	 { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
+	 { "PAGE_NULL", 19, 19, &umr_bitfield_default },
+	 { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
+	 { "F32_WR_RTR", 21, 21, &umr_bitfield_default },
+	 { "NEXT_WR_VECTOR", 22, 24, &umr_bitfield_default },
+	 { "MERGE_STATE", 25, 27, &umr_bitfield_default },
+	 { "RPTR_DATA_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "RPTR_DATA_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "WRREQ_DATA_FIFO_EMPTY", 30, 30, &umr_bitfield_default },
+	 { "WRREQ_DATA_FIFO_FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_INV0[] = {
+	 { "INV_MIDDLE", 0, 0, &umr_bitfield_default },
+	 { "RD_TIMEOUT", 1, 1, &umr_bitfield_default },
+	 { "WR_TIMEOUT", 2, 2, &umr_bitfield_default },
+	 { "RD_IN_INVADR", 3, 3, &umr_bitfield_default },
+	 { "WR_IN_INVADR", 4, 4, &umr_bitfield_default },
+	 { "PAGE_NULL_SW", 5, 5, &umr_bitfield_default },
+	 { "XNACK_IS_INVADR", 6, 6, &umr_bitfield_default },
+	 { "INVREQ_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "NACK_TIMEOUT_SW", 8, 8, &umr_bitfield_default },
+	 { "NFLUSH_INV_IDLE", 9, 9, &umr_bitfield_default },
+	 { "FLUSH_INV_IDLE", 10, 10, &umr_bitfield_default },
+	 { "INV_FLUSHTYPE", 11, 11, &umr_bitfield_default },
+	 { "INV_VMID_VEC", 12, 27, &umr_bitfield_default },
+	 { "INV_ADDR_HI", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_INV1[] = {
+	 { "INV_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_INV2[] = {
+	 { "INV_NFLUSH_VMID_VEC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK0[] = {
+	 { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_RD_XNACK1[] = {
+	 { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "XNACK_VMID", 4, 7, &umr_bitfield_default },
+	 { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
+	 { "IS_XNACK", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK0[] = {
+	 { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_WR_XNACK1[] = {
+	 { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "XNACK_VMID", 4, 7, &umr_bitfield_default },
+	 { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
+	 { "IS_XNACK", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_TIMEOUT[] = {
+	 { "RD_XNACK_LIMIT", 0, 15, &umr_bitfield_default },
+	 { "WR_XNACK_LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UTCL1_PAGE[] = {
+	 { "VM_HOLE", 0, 0, &umr_bitfield_default },
+	 { "REQ_TYPE", 1, 4, &umr_bitfield_default },
+	 { "USE_MTYPE", 6, 8, &umr_bitfield_default },
+	 { "USE_PT_SNOOP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_POWER_CNTL_IDLE[] = {
+	 { "DELAY0", 0, 15, &umr_bitfield_default },
+	 { "DELAY1", 16, 23, &umr_bitfield_default },
+	 { "DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RELAX_ORDERING_LUT[] = {
+	 { "RESERVED0", 0, 0, &umr_bitfield_default },
+	 { "COPY", 1, 1, &umr_bitfield_default },
+	 { "WRITE", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+	 { "FENCE", 5, 5, &umr_bitfield_default },
+	 { "RESERVED76", 6, 7, &umr_bitfield_default },
+	 { "POLL_MEM", 8, 8, &umr_bitfield_default },
+	 { "COND_EXE", 9, 9, &umr_bitfield_default },
+	 { "ATOMIC", 10, 10, &umr_bitfield_default },
+	 { "CONST_FILL", 11, 11, &umr_bitfield_default },
+	 { "PTEPDE", 12, 12, &umr_bitfield_default },
+	 { "TIMESTAMP", 13, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 26, &umr_bitfield_default },
+	 { "WORLD_SWITCH", 27, 27, &umr_bitfield_default },
+	 { "RPTR_WRB", 28, 28, &umr_bitfield_default },
+	 { "WPTR_POLL", 29, 29, &umr_bitfield_default },
+	 { "IB_FETCH", 30, 30, &umr_bitfield_default },
+	 { "RB_FETCH", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CHICKEN_BITS_2[] = {
+	 { "F32_CMD_PROC_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS3_REG[] = {
+	 { "CMD_OP_STATUS", 0, 15, &umr_bitfield_default },
+	 { "PREV_VM_CMD", 16, 19, &umr_bitfield_default },
+	 { "EXCEPTION_IDLE", 20, 20, &umr_bitfield_default },
+	 { "QUEUE_ID_MATCH", 21, 21, &umr_bitfield_default },
+	 { "INT_QUEUE_ID", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_LO[] = {
+	 { "D_VALID", 0, 0, &umr_bitfield_default },
+	 { "DIRTY", 1, 1, &umr_bitfield_default },
+	 { "PHY_VALID", 2, 2, &umr_bitfield_default },
+	 { "ADDR", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHYSICAL_ADDR_HI[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE2_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ERROR_LOG[] = {
+	 { "OVERRIDE", 0, 15, &umr_bitfield_default },
+	 { "STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG2[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_DUMMY_REG3[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_F32_COUNTER[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 9, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 10, 10, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 11, 11, &umr_bitfield_default },
+	 { "PERF_SEL1", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[] = {
+	 { "RANGE_LOW", 0, 13, &umr_bitfield_default },
+	 { "RANGE_HIGH", 14, 27, &umr_bitfield_default },
+	 { "SELECT_RW", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CRD_CNTL[] = {
+	 { "MC_WRREQ_CREDIT", 7, 12, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GPU_IOV_VIOLATION_LOG[] = {
+	 { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "WRITE_OPERATION", 18, 18, &umr_bitfield_default },
+	 { "VF", 19, 19, &umr_bitfield_default },
+	 { "VFID", 20, 23, &umr_bitfield_default },
+	 { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ULV_CNTL[] = {
+	 { "HYSTERESIS", 0, 4, &umr_bitfield_default },
+	 { "ENTER_ULV_INT_CLR", 27, 27, &umr_bitfield_default },
+	 { "EXIT_ULV_INT_CLR", 28, 28, &umr_bitfield_default },
+	 { "ENTER_ULV_INT", 29, 29, &umr_bitfield_default },
+	 { "EXIT_ULV_INT", 30, 30, &umr_bitfield_default },
+	 { "ULV_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EA_DBIT_ADDR_INDEX[] = {
+	 { "VALUE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PAGE_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC2_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC3_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC4_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC5_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC6_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC7_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/sdma042_regs.i b/src/lib/ip/sdma042_regs.i
new file mode 100644
index 0000000..f5b6f32
--- /dev/null
+++ b/src/lib/ip/sdma042_regs.i
@@ -0,0 +1,509 @@
+	{ "mmSDMA0_UCODE_ADDR", REG_MMIO, 0x0000, 0, &mmSDMA0_UCODE_ADDR[0], sizeof(mmSDMA0_UCODE_ADDR)/sizeof(mmSDMA0_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_DATA", REG_MMIO, 0x0001, 0, &mmSDMA0_UCODE_DATA[0], sizeof(mmSDMA0_UCODE_DATA)/sizeof(mmSDMA0_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA0_VM_CNTL", REG_MMIO, 0x0004, 0, &mmSDMA0_VM_CNTL[0], sizeof(mmSDMA0_VM_CNTL)/sizeof(mmSDMA0_VM_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_LO", REG_MMIO, 0x0005, 0, &mmSDMA0_VM_CTX_LO[0], sizeof(mmSDMA0_VM_CTX_LO)/sizeof(mmSDMA0_VM_CTX_LO[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_HI", REG_MMIO, 0x0006, 0, &mmSDMA0_VM_CTX_HI[0], sizeof(mmSDMA0_VM_CTX_HI)/sizeof(mmSDMA0_VM_CTX_HI[0]), 0, 0 },
+	{ "mmSDMA0_ACTIVE_FCN_ID", REG_MMIO, 0x0007, 0, &mmSDMA0_ACTIVE_FCN_ID[0], sizeof(mmSDMA0_ACTIVE_FCN_ID)/sizeof(mmSDMA0_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_CNTL", REG_MMIO, 0x0008, 0, &mmSDMA0_VM_CTX_CNTL[0], sizeof(mmSDMA0_VM_CTX_CNTL)/sizeof(mmSDMA0_VM_CTX_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_VIRT_RESET_REQ", REG_MMIO, 0x0009, 0, &mmSDMA0_VIRT_RESET_REQ[0], sizeof(mmSDMA0_VIRT_RESET_REQ)/sizeof(mmSDMA0_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSDMA0_VF_ENABLE", REG_MMIO, 0x000a, 0, &mmSDMA0_VF_ENABLE[0], sizeof(mmSDMA0_VF_ENABLE)/sizeof(mmSDMA0_VF_ENABLE[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE0", REG_MMIO, 0x000b, 0, &mmSDMA0_CONTEXT_REG_TYPE0[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE0)/sizeof(mmSDMA0_CONTEXT_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE1", REG_MMIO, 0x000c, 0, &mmSDMA0_CONTEXT_REG_TYPE1[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE1)/sizeof(mmSDMA0_CONTEXT_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE2", REG_MMIO, 0x000d, 0, &mmSDMA0_CONTEXT_REG_TYPE2[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE2)/sizeof(mmSDMA0_CONTEXT_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE3", REG_MMIO, 0x000e, 0, &mmSDMA0_CONTEXT_REG_TYPE3[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE3)/sizeof(mmSDMA0_CONTEXT_REG_TYPE3[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE0", REG_MMIO, 0x000f, 0, &mmSDMA0_PUB_REG_TYPE0[0], sizeof(mmSDMA0_PUB_REG_TYPE0)/sizeof(mmSDMA0_PUB_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE1", REG_MMIO, 0x0010, 0, &mmSDMA0_PUB_REG_TYPE1[0], sizeof(mmSDMA0_PUB_REG_TYPE1)/sizeof(mmSDMA0_PUB_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE2", REG_MMIO, 0x0011, 0, &mmSDMA0_PUB_REG_TYPE2[0], sizeof(mmSDMA0_PUB_REG_TYPE2)/sizeof(mmSDMA0_PUB_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE3", REG_MMIO, 0x0012, 0, &mmSDMA0_PUB_REG_TYPE3[0], sizeof(mmSDMA0_PUB_REG_TYPE3)/sizeof(mmSDMA0_PUB_REG_TYPE3[0]), 0, 0 },
+	{ "mmSDMA0_MMHUB_CNTL", REG_MMIO, 0x0013, 0, &mmSDMA0_MMHUB_CNTL[0], sizeof(mmSDMA0_MMHUB_CNTL)/sizeof(mmSDMA0_MMHUB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_GROUP_BOUNDARY", REG_MMIO, 0x0019, 0, &mmSDMA0_CONTEXT_GROUP_BOUNDARY[0], sizeof(mmSDMA0_CONTEXT_GROUP_BOUNDARY)/sizeof(mmSDMA0_CONTEXT_GROUP_BOUNDARY[0]), 0, 0 },
+	{ "mmSDMA0_POWER_CNTL", REG_MMIO, 0x001a, 0, &mmSDMA0_POWER_CNTL[0], sizeof(mmSDMA0_POWER_CNTL)/sizeof(mmSDMA0_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CLK_CTRL", REG_MMIO, 0x001b, 0, &mmSDMA0_CLK_CTRL[0], sizeof(mmSDMA0_CLK_CTRL)/sizeof(mmSDMA0_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA0_CNTL", REG_MMIO, 0x001c, 0, &mmSDMA0_CNTL[0], sizeof(mmSDMA0_CNTL)/sizeof(mmSDMA0_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CHICKEN_BITS", REG_MMIO, 0x001d, 0, &mmSDMA0_CHICKEN_BITS[0], sizeof(mmSDMA0_CHICKEN_BITS)/sizeof(mmSDMA0_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA0_GB_ADDR_CONFIG", REG_MMIO, 0x001e, 0, &mmSDMA0_GB_ADDR_CONFIG[0], sizeof(mmSDMA0_GB_ADDR_CONFIG)/sizeof(mmSDMA0_GB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_GB_ADDR_CONFIG_READ", REG_MMIO, 0x001f, 0, &mmSDMA0_GB_ADDR_CONFIG_READ[0], sizeof(mmSDMA0_GB_ADDR_CONFIG_READ)/sizeof(mmSDMA0_GB_ADDR_CONFIG_READ[0]), 0, 0 },
+	{ "mmSDMA0_RB_RPTR_FETCH_HI", REG_MMIO, 0x0020, 0, &mmSDMA0_RB_RPTR_FETCH_HI[0], sizeof(mmSDMA0_RB_RPTR_FETCH_HI)/sizeof(mmSDMA0_RB_RPTR_FETCH_HI[0]), 0, 0 },
+	{ "mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x0021, 0, &mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RB_RPTR_FETCH", REG_MMIO, 0x0022, 0, &mmSDMA0_RB_RPTR_FETCH[0], sizeof(mmSDMA0_RB_RPTR_FETCH)/sizeof(mmSDMA0_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_IB_OFFSET_FETCH", REG_MMIO, 0x0023, 0, &mmSDMA0_IB_OFFSET_FETCH[0], sizeof(mmSDMA0_IB_OFFSET_FETCH)/sizeof(mmSDMA0_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_PROGRAM", REG_MMIO, 0x0024, 0, &mmSDMA0_PROGRAM[0], sizeof(mmSDMA0_PROGRAM)/sizeof(mmSDMA0_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA0_STATUS_REG", REG_MMIO, 0x0025, 0, &mmSDMA0_STATUS_REG[0], sizeof(mmSDMA0_STATUS_REG)/sizeof(mmSDMA0_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA0_STATUS1_REG", REG_MMIO, 0x0026, 0, &mmSDMA0_STATUS1_REG[0], sizeof(mmSDMA0_STATUS1_REG)/sizeof(mmSDMA0_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA0_RD_BURST_CNTL", REG_MMIO, 0x0027, 0, &mmSDMA0_RD_BURST_CNTL[0], sizeof(mmSDMA0_RD_BURST_CNTL)/sizeof(mmSDMA0_RD_BURST_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_HBM_PAGE_CONFIG", REG_MMIO, 0x0028, 0, &mmSDMA0_HBM_PAGE_CONFIG[0], sizeof(mmSDMA0_HBM_PAGE_CONFIG)/sizeof(mmSDMA0_HBM_PAGE_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_CHECKSUM", REG_MMIO, 0x0029, 0, &mmSDMA0_UCODE_CHECKSUM[0], sizeof(mmSDMA0_UCODE_CHECKSUM)/sizeof(mmSDMA0_UCODE_CHECKSUM[0]), 0, 0 },
+	{ "mmSDMA0_F32_CNTL", REG_MMIO, 0x002a, 0, &mmSDMA0_F32_CNTL[0], sizeof(mmSDMA0_F32_CNTL)/sizeof(mmSDMA0_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_FREEZE", REG_MMIO, 0x002b, 0, &mmSDMA0_FREEZE[0], sizeof(mmSDMA0_FREEZE)/sizeof(mmSDMA0_FREEZE[0]), 0, 0 },
+	{ "mmSDMA0_PHASE0_QUANTUM", REG_MMIO, 0x002c, 0, &mmSDMA0_PHASE0_QUANTUM[0], sizeof(mmSDMA0_PHASE0_QUANTUM)/sizeof(mmSDMA0_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA0_PHASE1_QUANTUM", REG_MMIO, 0x002d, 0, &mmSDMA0_PHASE1_QUANTUM[0], sizeof(mmSDMA0_PHASE1_QUANTUM)/sizeof(mmSDMA0_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA_POWER_GATING", REG_MMIO, 0x002e, 0, &mmSDMA_POWER_GATING[0], sizeof(mmSDMA_POWER_GATING)/sizeof(mmSDMA_POWER_GATING[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_CONFIG", REG_MMIO, 0x002f, 0, &mmSDMA_PGFSM_CONFIG[0], sizeof(mmSDMA_PGFSM_CONFIG)/sizeof(mmSDMA_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_WRITE", REG_MMIO, 0x0030, 0, &mmSDMA_PGFSM_WRITE[0], sizeof(mmSDMA_PGFSM_WRITE)/sizeof(mmSDMA_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_READ", REG_MMIO, 0x0031, 0, &mmSDMA_PGFSM_READ[0], sizeof(mmSDMA_PGFSM_READ)/sizeof(mmSDMA_PGFSM_READ[0]), 0, 0 },
+	{ "mmSDMA0_EDC_CONFIG", REG_MMIO, 0x0032, 0, &mmSDMA0_EDC_CONFIG[0], sizeof(mmSDMA0_EDC_CONFIG)/sizeof(mmSDMA0_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_BA_THRESHOLD", REG_MMIO, 0x0033, 0, &mmSDMA0_BA_THRESHOLD[0], sizeof(mmSDMA0_BA_THRESHOLD)/sizeof(mmSDMA0_BA_THRESHOLD[0]), 0, 0 },
+	{ "mmSDMA0_ID", REG_MMIO, 0x0034, 0, &mmSDMA0_ID[0], sizeof(mmSDMA0_ID)/sizeof(mmSDMA0_ID[0]), 0, 0 },
+	{ "mmSDMA0_VERSION", REG_MMIO, 0x0035, 0, &mmSDMA0_VERSION[0], sizeof(mmSDMA0_VERSION)/sizeof(mmSDMA0_VERSION[0]), 0, 0 },
+	{ "mmSDMA0_EDC_COUNTER", REG_MMIO, 0x0036, 0, &mmSDMA0_EDC_COUNTER[0], sizeof(mmSDMA0_EDC_COUNTER)/sizeof(mmSDMA0_EDC_COUNTER[0]), 0, 0 },
+	{ "mmSDMA0_EDC_COUNTER_CLEAR", REG_MMIO, 0x0037, 0, &mmSDMA0_EDC_COUNTER_CLEAR[0], sizeof(mmSDMA0_EDC_COUNTER_CLEAR)/sizeof(mmSDMA0_EDC_COUNTER_CLEAR[0]), 0, 0 },
+	{ "mmSDMA0_STATUS2_REG", REG_MMIO, 0x0038, 0, &mmSDMA0_STATUS2_REG[0], sizeof(mmSDMA0_STATUS2_REG)/sizeof(mmSDMA0_STATUS2_REG[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_CNTL", REG_MMIO, 0x0039, 0, &mmSDMA0_ATOMIC_CNTL[0], sizeof(mmSDMA0_ATOMIC_CNTL)/sizeof(mmSDMA0_ATOMIC_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_PREOP_LO", REG_MMIO, 0x003a, 0, &mmSDMA0_ATOMIC_PREOP_LO[0], sizeof(mmSDMA0_ATOMIC_PREOP_LO)/sizeof(mmSDMA0_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_PREOP_HI", REG_MMIO, 0x003b, 0, &mmSDMA0_ATOMIC_PREOP_HI[0], sizeof(mmSDMA0_ATOMIC_PREOP_HI)/sizeof(mmSDMA0_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_CNTL", REG_MMIO, 0x003c, 0, &mmSDMA0_UTCL1_CNTL[0], sizeof(mmSDMA0_UTCL1_CNTL)/sizeof(mmSDMA0_UTCL1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_WATERMK", REG_MMIO, 0x003d, 0, &mmSDMA0_UTCL1_WATERMK[0], sizeof(mmSDMA0_UTCL1_WATERMK)/sizeof(mmSDMA0_UTCL1_WATERMK[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_RD_STATUS", REG_MMIO, 0x003e, 0, &mmSDMA0_UTCL1_RD_STATUS[0], sizeof(mmSDMA0_UTCL1_RD_STATUS)/sizeof(mmSDMA0_UTCL1_RD_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_WR_STATUS", REG_MMIO, 0x003f, 0, &mmSDMA0_UTCL1_WR_STATUS[0], sizeof(mmSDMA0_UTCL1_WR_STATUS)/sizeof(mmSDMA0_UTCL1_WR_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_INV0", REG_MMIO, 0x0040, 0, &mmSDMA0_UTCL1_INV0[0], sizeof(mmSDMA0_UTCL1_INV0)/sizeof(mmSDMA0_UTCL1_INV0[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_INV1", REG_MMIO, 0x0041, 0, &mmSDMA0_UTCL1_INV1[0], sizeof(mmSDMA0_UTCL1_INV1)/sizeof(mmSDMA0_UTCL1_INV1[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_INV2", REG_MMIO, 0x0042, 0, &mmSDMA0_UTCL1_INV2[0], sizeof(mmSDMA0_UTCL1_INV2)/sizeof(mmSDMA0_UTCL1_INV2[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_RD_XNACK0", REG_MMIO, 0x0043, 0, &mmSDMA0_UTCL1_RD_XNACK0[0], sizeof(mmSDMA0_UTCL1_RD_XNACK0)/sizeof(mmSDMA0_UTCL1_RD_XNACK0[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_RD_XNACK1", REG_MMIO, 0x0044, 0, &mmSDMA0_UTCL1_RD_XNACK1[0], sizeof(mmSDMA0_UTCL1_RD_XNACK1)/sizeof(mmSDMA0_UTCL1_RD_XNACK1[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_WR_XNACK0", REG_MMIO, 0x0045, 0, &mmSDMA0_UTCL1_WR_XNACK0[0], sizeof(mmSDMA0_UTCL1_WR_XNACK0)/sizeof(mmSDMA0_UTCL1_WR_XNACK0[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_WR_XNACK1", REG_MMIO, 0x0046, 0, &mmSDMA0_UTCL1_WR_XNACK1[0], sizeof(mmSDMA0_UTCL1_WR_XNACK1)/sizeof(mmSDMA0_UTCL1_WR_XNACK1[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_TIMEOUT", REG_MMIO, 0x0047, 0, &mmSDMA0_UTCL1_TIMEOUT[0], sizeof(mmSDMA0_UTCL1_TIMEOUT)/sizeof(mmSDMA0_UTCL1_TIMEOUT[0]), 0, 0 },
+	{ "mmSDMA0_UTCL1_PAGE", REG_MMIO, 0x0048, 0, &mmSDMA0_UTCL1_PAGE[0], sizeof(mmSDMA0_UTCL1_PAGE)/sizeof(mmSDMA0_UTCL1_PAGE[0]), 0, 0 },
+	{ "mmSDMA0_POWER_CNTL_IDLE", REG_MMIO, 0x0049, 0, &mmSDMA0_POWER_CNTL_IDLE[0], sizeof(mmSDMA0_POWER_CNTL_IDLE)/sizeof(mmSDMA0_POWER_CNTL_IDLE[0]), 0, 0 },
+	{ "mmSDMA0_RELAX_ORDERING_LUT", REG_MMIO, 0x004a, 0, &mmSDMA0_RELAX_ORDERING_LUT[0], sizeof(mmSDMA0_RELAX_ORDERING_LUT)/sizeof(mmSDMA0_RELAX_ORDERING_LUT[0]), 0, 0 },
+	{ "mmSDMA0_CHICKEN_BITS_2", REG_MMIO, 0x004b, 0, &mmSDMA0_CHICKEN_BITS_2[0], sizeof(mmSDMA0_CHICKEN_BITS_2)/sizeof(mmSDMA0_CHICKEN_BITS_2[0]), 0, 0 },
+	{ "mmSDMA0_STATUS3_REG", REG_MMIO, 0x004c, 0, &mmSDMA0_STATUS3_REG[0], sizeof(mmSDMA0_STATUS3_REG)/sizeof(mmSDMA0_STATUS3_REG[0]), 0, 0 },
+	{ "mmSDMA0_PHYSICAL_ADDR_LO", REG_MMIO, 0x004d, 0, &mmSDMA0_PHYSICAL_ADDR_LO[0], sizeof(mmSDMA0_PHYSICAL_ADDR_LO)/sizeof(mmSDMA0_PHYSICAL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_PHYSICAL_ADDR_HI", REG_MMIO, 0x004e, 0, &mmSDMA0_PHYSICAL_ADDR_HI[0], sizeof(mmSDMA0_PHYSICAL_ADDR_HI)/sizeof(mmSDMA0_PHYSICAL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PHASE2_QUANTUM", REG_MMIO, 0x004f, 0, &mmSDMA0_PHASE2_QUANTUM[0], sizeof(mmSDMA0_PHASE2_QUANTUM)/sizeof(mmSDMA0_PHASE2_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA0_ERROR_LOG", REG_MMIO, 0x0050, 0, &mmSDMA0_ERROR_LOG[0], sizeof(mmSDMA0_ERROR_LOG)/sizeof(mmSDMA0_ERROR_LOG[0]), 0, 0 },
+	{ "mmSDMA0_PUB_DUMMY_REG0", REG_MMIO, 0x0051, 0, &mmSDMA0_PUB_DUMMY_REG0[0], sizeof(mmSDMA0_PUB_DUMMY_REG0)/sizeof(mmSDMA0_PUB_DUMMY_REG0[0]), 0, 0 },
+	{ "mmSDMA0_PUB_DUMMY_REG1", REG_MMIO, 0x0052, 0, &mmSDMA0_PUB_DUMMY_REG1[0], sizeof(mmSDMA0_PUB_DUMMY_REG1)/sizeof(mmSDMA0_PUB_DUMMY_REG1[0]), 0, 0 },
+	{ "mmSDMA0_PUB_DUMMY_REG2", REG_MMIO, 0x0053, 0, &mmSDMA0_PUB_DUMMY_REG2[0], sizeof(mmSDMA0_PUB_DUMMY_REG2)/sizeof(mmSDMA0_PUB_DUMMY_REG2[0]), 0, 0 },
+	{ "mmSDMA0_PUB_DUMMY_REG3", REG_MMIO, 0x0054, 0, &mmSDMA0_PUB_DUMMY_REG3[0], sizeof(mmSDMA0_PUB_DUMMY_REG3)/sizeof(mmSDMA0_PUB_DUMMY_REG3[0]), 0, 0 },
+	{ "mmSDMA0_F32_COUNTER", REG_MMIO, 0x0055, 0, &mmSDMA0_F32_COUNTER[0], sizeof(mmSDMA0_F32_COUNTER)/sizeof(mmSDMA0_F32_COUNTER[0]), 0, 0 },
+	{ "mmSDMA0_PERFMON_CNTL", REG_MMIO, 0x0057, 0, &mmSDMA0_PERFMON_CNTL[0], sizeof(mmSDMA0_PERFMON_CNTL)/sizeof(mmSDMA0_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER0_RESULT", REG_MMIO, 0x0058, 0, &mmSDMA0_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER0_RESULT)/sizeof(mmSDMA0_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER1_RESULT", REG_MMIO, 0x0059, 0, &mmSDMA0_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER1_RESULT)/sizeof(mmSDMA0_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE", REG_MMIO, 0x005a, 0, &mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[0], sizeof(mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE)/sizeof(mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE[0]), 0, 0 },
+	{ "mmSDMA0_CRD_CNTL", REG_MMIO, 0x005b, 0, &mmSDMA0_CRD_CNTL[0], sizeof(mmSDMA0_CRD_CNTL)/sizeof(mmSDMA0_CRD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GPU_IOV_VIOLATION_LOG", REG_MMIO, 0x005d, 0, &mmSDMA0_GPU_IOV_VIOLATION_LOG[0], sizeof(mmSDMA0_GPU_IOV_VIOLATION_LOG)/sizeof(mmSDMA0_GPU_IOV_VIOLATION_LOG[0]), 0, 0 },
+	{ "mmSDMA0_ULV_CNTL", REG_MMIO, 0x005e, 0, &mmSDMA0_ULV_CNTL[0], sizeof(mmSDMA0_ULV_CNTL)/sizeof(mmSDMA0_ULV_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_EA_DBIT_ADDR_DATA", REG_MMIO, 0x0060, 0, &mmSDMA0_EA_DBIT_ADDR_DATA[0], sizeof(mmSDMA0_EA_DBIT_ADDR_DATA)/sizeof(mmSDMA0_EA_DBIT_ADDR_DATA[0]), 0, 0 },
+	{ "mmSDMA0_EA_DBIT_ADDR_INDEX", REG_MMIO, 0x0061, 0, &mmSDMA0_EA_DBIT_ADDR_INDEX[0], sizeof(mmSDMA0_EA_DBIT_ADDR_INDEX)/sizeof(mmSDMA0_EA_DBIT_ADDR_INDEX[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_CNTL", REG_MMIO, 0x0080, 0, &mmSDMA0_GFX_RB_CNTL[0], sizeof(mmSDMA0_GFX_RB_CNTL)/sizeof(mmSDMA0_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE", REG_MMIO, 0x0081, 0, &mmSDMA0_GFX_RB_BASE[0], sizeof(mmSDMA0_GFX_RB_BASE)/sizeof(mmSDMA0_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE_HI", REG_MMIO, 0x0082, 0, &mmSDMA0_GFX_RB_BASE_HI[0], sizeof(mmSDMA0_GFX_RB_BASE_HI)/sizeof(mmSDMA0_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR", REG_MMIO, 0x0083, 0, &mmSDMA0_GFX_RB_RPTR[0], sizeof(mmSDMA0_GFX_RB_RPTR)/sizeof(mmSDMA0_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_HI", REG_MMIO, 0x0084, 0, &mmSDMA0_GFX_RB_RPTR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR", REG_MMIO, 0x0085, 0, &mmSDMA0_GFX_RB_WPTR[0], sizeof(mmSDMA0_GFX_RB_WPTR)/sizeof(mmSDMA0_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_HI", REG_MMIO, 0x0086, 0, &mmSDMA0_GFX_RB_WPTR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0087, 0, &mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x0088, 0, &mmSDMA0_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x0089, 0, &mmSDMA0_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_CNTL", REG_MMIO, 0x008a, 0, &mmSDMA0_GFX_IB_CNTL[0], sizeof(mmSDMA0_GFX_IB_CNTL)/sizeof(mmSDMA0_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_RPTR", REG_MMIO, 0x008b, 0, &mmSDMA0_GFX_IB_RPTR[0], sizeof(mmSDMA0_GFX_IB_RPTR)/sizeof(mmSDMA0_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_OFFSET", REG_MMIO, 0x008c, 0, &mmSDMA0_GFX_IB_OFFSET[0], sizeof(mmSDMA0_GFX_IB_OFFSET)/sizeof(mmSDMA0_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_LO", REG_MMIO, 0x008d, 0, &mmSDMA0_GFX_IB_BASE_LO[0], sizeof(mmSDMA0_GFX_IB_BASE_LO)/sizeof(mmSDMA0_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_HI", REG_MMIO, 0x008e, 0, &mmSDMA0_GFX_IB_BASE_HI[0], sizeof(mmSDMA0_GFX_IB_BASE_HI)/sizeof(mmSDMA0_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_SIZE", REG_MMIO, 0x008f, 0, &mmSDMA0_GFX_IB_SIZE[0], sizeof(mmSDMA0_GFX_IB_SIZE)/sizeof(mmSDMA0_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_SKIP_CNTL", REG_MMIO, 0x0090, 0, &mmSDMA0_GFX_SKIP_CNTL[0], sizeof(mmSDMA0_GFX_SKIP_CNTL)/sizeof(mmSDMA0_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_STATUS", REG_MMIO, 0x0091, 0, &mmSDMA0_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA0_GFX_CONTEXT_STATUS)/sizeof(mmSDMA0_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DOORBELL", REG_MMIO, 0x0092, 0, &mmSDMA0_GFX_DOORBELL[0], sizeof(mmSDMA0_GFX_DOORBELL)/sizeof(mmSDMA0_GFX_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_CNTL", REG_MMIO, 0x0093, 0, &mmSDMA0_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA0_GFX_CONTEXT_CNTL)/sizeof(mmSDMA0_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_STATUS", REG_MMIO, 0x00a8, 0, &mmSDMA0_GFX_STATUS[0], sizeof(mmSDMA0_GFX_STATUS)/sizeof(mmSDMA0_GFX_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DOORBELL_LOG", REG_MMIO, 0x00a9, 0, &mmSDMA0_GFX_DOORBELL_LOG[0], sizeof(mmSDMA0_GFX_DOORBELL_LOG)/sizeof(mmSDMA0_GFX_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_GFX_WATERMARK", REG_MMIO, 0x00aa, 0, &mmSDMA0_GFX_WATERMARK[0], sizeof(mmSDMA0_GFX_WATERMARK)/sizeof(mmSDMA0_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DOORBELL_OFFSET", REG_MMIO, 0x00ab, 0, &mmSDMA0_GFX_DOORBELL_OFFSET[0], sizeof(mmSDMA0_GFX_DOORBELL_OFFSET)/sizeof(mmSDMA0_GFX_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CSA_ADDR_LO", REG_MMIO, 0x00ac, 0, &mmSDMA0_GFX_CSA_ADDR_LO[0], sizeof(mmSDMA0_GFX_CSA_ADDR_LO)/sizeof(mmSDMA0_GFX_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CSA_ADDR_HI", REG_MMIO, 0x00ad, 0, &mmSDMA0_GFX_CSA_ADDR_HI[0], sizeof(mmSDMA0_GFX_CSA_ADDR_HI)/sizeof(mmSDMA0_GFX_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_SUB_REMAIN", REG_MMIO, 0x00af, 0, &mmSDMA0_GFX_IB_SUB_REMAIN[0], sizeof(mmSDMA0_GFX_IB_SUB_REMAIN)/sizeof(mmSDMA0_GFX_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_GFX_PREEMPT", REG_MMIO, 0x00b0, 0, &mmSDMA0_GFX_PREEMPT[0], sizeof(mmSDMA0_GFX_PREEMPT)/sizeof(mmSDMA0_GFX_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DUMMY_REG", REG_MMIO, 0x00b1, 0, &mmSDMA0_GFX_DUMMY_REG[0], sizeof(mmSDMA0_GFX_DUMMY_REG)/sizeof(mmSDMA0_GFX_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x00b2, 0, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x00b3, 0, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_AQL_CNTL", REG_MMIO, 0x00b4, 0, &mmSDMA0_GFX_RB_AQL_CNTL[0], sizeof(mmSDMA0_GFX_RB_AQL_CNTL)/sizeof(mmSDMA0_GFX_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MINOR_PTR_UPDATE", REG_MMIO, 0x00b5, 0, &mmSDMA0_GFX_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_GFX_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_GFX_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA0", REG_MMIO, 0x00c0, 0, &mmSDMA0_GFX_MIDCMD_DATA0[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA0)/sizeof(mmSDMA0_GFX_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA1", REG_MMIO, 0x00c1, 0, &mmSDMA0_GFX_MIDCMD_DATA1[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA1)/sizeof(mmSDMA0_GFX_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA2", REG_MMIO, 0x00c2, 0, &mmSDMA0_GFX_MIDCMD_DATA2[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA2)/sizeof(mmSDMA0_GFX_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA3", REG_MMIO, 0x00c3, 0, &mmSDMA0_GFX_MIDCMD_DATA3[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA3)/sizeof(mmSDMA0_GFX_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA4", REG_MMIO, 0x00c4, 0, &mmSDMA0_GFX_MIDCMD_DATA4[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA4)/sizeof(mmSDMA0_GFX_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA5", REG_MMIO, 0x00c5, 0, &mmSDMA0_GFX_MIDCMD_DATA5[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA5)/sizeof(mmSDMA0_GFX_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA6", REG_MMIO, 0x00c6, 0, &mmSDMA0_GFX_MIDCMD_DATA6[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA6)/sizeof(mmSDMA0_GFX_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA7", REG_MMIO, 0x00c7, 0, &mmSDMA0_GFX_MIDCMD_DATA7[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA7)/sizeof(mmSDMA0_GFX_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA8", REG_MMIO, 0x00c8, 0, &mmSDMA0_GFX_MIDCMD_DATA8[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA8)/sizeof(mmSDMA0_GFX_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_CNTL", REG_MMIO, 0x00c9, 0, &mmSDMA0_GFX_MIDCMD_CNTL[0], sizeof(mmSDMA0_GFX_MIDCMD_CNTL)/sizeof(mmSDMA0_GFX_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_CNTL", REG_MMIO, 0x00e0, 0, &mmSDMA0_PAGE_RB_CNTL[0], sizeof(mmSDMA0_PAGE_RB_CNTL)/sizeof(mmSDMA0_PAGE_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_BASE", REG_MMIO, 0x00e1, 0, &mmSDMA0_PAGE_RB_BASE[0], sizeof(mmSDMA0_PAGE_RB_BASE)/sizeof(mmSDMA0_PAGE_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_BASE_HI", REG_MMIO, 0x00e2, 0, &mmSDMA0_PAGE_RB_BASE_HI[0], sizeof(mmSDMA0_PAGE_RB_BASE_HI)/sizeof(mmSDMA0_PAGE_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_RPTR", REG_MMIO, 0x00e3, 0, &mmSDMA0_PAGE_RB_RPTR[0], sizeof(mmSDMA0_PAGE_RB_RPTR)/sizeof(mmSDMA0_PAGE_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_RPTR_HI", REG_MMIO, 0x00e4, 0, &mmSDMA0_PAGE_RB_RPTR_HI[0], sizeof(mmSDMA0_PAGE_RB_RPTR_HI)/sizeof(mmSDMA0_PAGE_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_WPTR", REG_MMIO, 0x00e5, 0, &mmSDMA0_PAGE_RB_WPTR[0], sizeof(mmSDMA0_PAGE_RB_WPTR)/sizeof(mmSDMA0_PAGE_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_WPTR_HI", REG_MMIO, 0x00e6, 0, &mmSDMA0_PAGE_RB_WPTR_HI[0], sizeof(mmSDMA0_PAGE_RB_WPTR_HI)/sizeof(mmSDMA0_PAGE_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_WPTR_POLL_CNTL", REG_MMIO, 0x00e7, 0, &mmSDMA0_PAGE_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_RPTR_ADDR_HI", REG_MMIO, 0x00e8, 0, &mmSDMA0_PAGE_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_PAGE_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_PAGE_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_RPTR_ADDR_LO", REG_MMIO, 0x00e9, 0, &mmSDMA0_PAGE_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_PAGE_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_PAGE_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_CNTL", REG_MMIO, 0x00ea, 0, &mmSDMA0_PAGE_IB_CNTL[0], sizeof(mmSDMA0_PAGE_IB_CNTL)/sizeof(mmSDMA0_PAGE_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_RPTR", REG_MMIO, 0x00eb, 0, &mmSDMA0_PAGE_IB_RPTR[0], sizeof(mmSDMA0_PAGE_IB_RPTR)/sizeof(mmSDMA0_PAGE_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_OFFSET", REG_MMIO, 0x00ec, 0, &mmSDMA0_PAGE_IB_OFFSET[0], sizeof(mmSDMA0_PAGE_IB_OFFSET)/sizeof(mmSDMA0_PAGE_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_BASE_LO", REG_MMIO, 0x00ed, 0, &mmSDMA0_PAGE_IB_BASE_LO[0], sizeof(mmSDMA0_PAGE_IB_BASE_LO)/sizeof(mmSDMA0_PAGE_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_BASE_HI", REG_MMIO, 0x00ee, 0, &mmSDMA0_PAGE_IB_BASE_HI[0], sizeof(mmSDMA0_PAGE_IB_BASE_HI)/sizeof(mmSDMA0_PAGE_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_SIZE", REG_MMIO, 0x00ef, 0, &mmSDMA0_PAGE_IB_SIZE[0], sizeof(mmSDMA0_PAGE_IB_SIZE)/sizeof(mmSDMA0_PAGE_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_SKIP_CNTL", REG_MMIO, 0x00f0, 0, &mmSDMA0_PAGE_SKIP_CNTL[0], sizeof(mmSDMA0_PAGE_SKIP_CNTL)/sizeof(mmSDMA0_PAGE_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_CONTEXT_STATUS", REG_MMIO, 0x00f1, 0, &mmSDMA0_PAGE_CONTEXT_STATUS[0], sizeof(mmSDMA0_PAGE_CONTEXT_STATUS)/sizeof(mmSDMA0_PAGE_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_DOORBELL", REG_MMIO, 0x00f2, 0, &mmSDMA0_PAGE_DOORBELL[0], sizeof(mmSDMA0_PAGE_DOORBELL)/sizeof(mmSDMA0_PAGE_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_STATUS", REG_MMIO, 0x0108, 0, &mmSDMA0_PAGE_STATUS[0], sizeof(mmSDMA0_PAGE_STATUS)/sizeof(mmSDMA0_PAGE_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_DOORBELL_LOG", REG_MMIO, 0x0109, 0, &mmSDMA0_PAGE_DOORBELL_LOG[0], sizeof(mmSDMA0_PAGE_DOORBELL_LOG)/sizeof(mmSDMA0_PAGE_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_WATERMARK", REG_MMIO, 0x010a, 0, &mmSDMA0_PAGE_WATERMARK[0], sizeof(mmSDMA0_PAGE_WATERMARK)/sizeof(mmSDMA0_PAGE_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_DOORBELL_OFFSET", REG_MMIO, 0x010b, 0, &mmSDMA0_PAGE_DOORBELL_OFFSET[0], sizeof(mmSDMA0_PAGE_DOORBELL_OFFSET)/sizeof(mmSDMA0_PAGE_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_CSA_ADDR_LO", REG_MMIO, 0x010c, 0, &mmSDMA0_PAGE_CSA_ADDR_LO[0], sizeof(mmSDMA0_PAGE_CSA_ADDR_LO)/sizeof(mmSDMA0_PAGE_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_CSA_ADDR_HI", REG_MMIO, 0x010d, 0, &mmSDMA0_PAGE_CSA_ADDR_HI[0], sizeof(mmSDMA0_PAGE_CSA_ADDR_HI)/sizeof(mmSDMA0_PAGE_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_IB_SUB_REMAIN", REG_MMIO, 0x010f, 0, &mmSDMA0_PAGE_IB_SUB_REMAIN[0], sizeof(mmSDMA0_PAGE_IB_SUB_REMAIN)/sizeof(mmSDMA0_PAGE_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_PREEMPT", REG_MMIO, 0x0110, 0, &mmSDMA0_PAGE_PREEMPT[0], sizeof(mmSDMA0_PAGE_PREEMPT)/sizeof(mmSDMA0_PAGE_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_DUMMY_REG", REG_MMIO, 0x0111, 0, &mmSDMA0_PAGE_DUMMY_REG[0], sizeof(mmSDMA0_PAGE_DUMMY_REG)/sizeof(mmSDMA0_PAGE_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0112, 0, &mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0113, 0, &mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_RB_AQL_CNTL", REG_MMIO, 0x0114, 0, &mmSDMA0_PAGE_RB_AQL_CNTL[0], sizeof(mmSDMA0_PAGE_RB_AQL_CNTL)/sizeof(mmSDMA0_PAGE_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MINOR_PTR_UPDATE", REG_MMIO, 0x0115, 0, &mmSDMA0_PAGE_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_PAGE_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_PAGE_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA0", REG_MMIO, 0x0120, 0, &mmSDMA0_PAGE_MIDCMD_DATA0[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA0)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA1", REG_MMIO, 0x0121, 0, &mmSDMA0_PAGE_MIDCMD_DATA1[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA1)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA2", REG_MMIO, 0x0122, 0, &mmSDMA0_PAGE_MIDCMD_DATA2[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA2)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA3", REG_MMIO, 0x0123, 0, &mmSDMA0_PAGE_MIDCMD_DATA3[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA3)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA4", REG_MMIO, 0x0124, 0, &mmSDMA0_PAGE_MIDCMD_DATA4[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA4)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA5", REG_MMIO, 0x0125, 0, &mmSDMA0_PAGE_MIDCMD_DATA5[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA5)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA6", REG_MMIO, 0x0126, 0, &mmSDMA0_PAGE_MIDCMD_DATA6[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA6)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA7", REG_MMIO, 0x0127, 0, &mmSDMA0_PAGE_MIDCMD_DATA7[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA7)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_DATA8", REG_MMIO, 0x0128, 0, &mmSDMA0_PAGE_MIDCMD_DATA8[0], sizeof(mmSDMA0_PAGE_MIDCMD_DATA8)/sizeof(mmSDMA0_PAGE_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_PAGE_MIDCMD_CNTL", REG_MMIO, 0x0129, 0, &mmSDMA0_PAGE_MIDCMD_CNTL[0], sizeof(mmSDMA0_PAGE_MIDCMD_CNTL)/sizeof(mmSDMA0_PAGE_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_CNTL", REG_MMIO, 0x0140, 0, &mmSDMA0_RLC0_RB_CNTL[0], sizeof(mmSDMA0_RLC0_RB_CNTL)/sizeof(mmSDMA0_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE", REG_MMIO, 0x0141, 0, &mmSDMA0_RLC0_RB_BASE[0], sizeof(mmSDMA0_RLC0_RB_BASE)/sizeof(mmSDMA0_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE_HI", REG_MMIO, 0x0142, 0, &mmSDMA0_RLC0_RB_BASE_HI[0], sizeof(mmSDMA0_RLC0_RB_BASE_HI)/sizeof(mmSDMA0_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR", REG_MMIO, 0x0143, 0, &mmSDMA0_RLC0_RB_RPTR[0], sizeof(mmSDMA0_RLC0_RB_RPTR)/sizeof(mmSDMA0_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_HI", REG_MMIO, 0x0144, 0, &mmSDMA0_RLC0_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR", REG_MMIO, 0x0145, 0, &mmSDMA0_RLC0_RB_WPTR[0], sizeof(mmSDMA0_RLC0_RB_WPTR)/sizeof(mmSDMA0_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_HI", REG_MMIO, 0x0146, 0, &mmSDMA0_RLC0_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0147, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x0148, 0, &mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x0149, 0, &mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_CNTL", REG_MMIO, 0x014a, 0, &mmSDMA0_RLC0_IB_CNTL[0], sizeof(mmSDMA0_RLC0_IB_CNTL)/sizeof(mmSDMA0_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_RPTR", REG_MMIO, 0x014b, 0, &mmSDMA0_RLC0_IB_RPTR[0], sizeof(mmSDMA0_RLC0_IB_RPTR)/sizeof(mmSDMA0_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_OFFSET", REG_MMIO, 0x014c, 0, &mmSDMA0_RLC0_IB_OFFSET[0], sizeof(mmSDMA0_RLC0_IB_OFFSET)/sizeof(mmSDMA0_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_LO", REG_MMIO, 0x014d, 0, &mmSDMA0_RLC0_IB_BASE_LO[0], sizeof(mmSDMA0_RLC0_IB_BASE_LO)/sizeof(mmSDMA0_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_HI", REG_MMIO, 0x014e, 0, &mmSDMA0_RLC0_IB_BASE_HI[0], sizeof(mmSDMA0_RLC0_IB_BASE_HI)/sizeof(mmSDMA0_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_SIZE", REG_MMIO, 0x014f, 0, &mmSDMA0_RLC0_IB_SIZE[0], sizeof(mmSDMA0_RLC0_IB_SIZE)/sizeof(mmSDMA0_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_SKIP_CNTL", REG_MMIO, 0x0150, 0, &mmSDMA0_RLC0_SKIP_CNTL[0], sizeof(mmSDMA0_RLC0_SKIP_CNTL)/sizeof(mmSDMA0_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CONTEXT_STATUS", REG_MMIO, 0x0151, 0, &mmSDMA0_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL", REG_MMIO, 0x0152, 0, &mmSDMA0_RLC0_DOORBELL[0], sizeof(mmSDMA0_RLC0_DOORBELL)/sizeof(mmSDMA0_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_STATUS", REG_MMIO, 0x0168, 0, &mmSDMA0_RLC0_STATUS[0], sizeof(mmSDMA0_RLC0_STATUS)/sizeof(mmSDMA0_RLC0_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL_LOG", REG_MMIO, 0x0169, 0, &mmSDMA0_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC0_DOORBELL_LOG)/sizeof(mmSDMA0_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_WATERMARK", REG_MMIO, 0x016a, 0, &mmSDMA0_RLC0_WATERMARK[0], sizeof(mmSDMA0_RLC0_WATERMARK)/sizeof(mmSDMA0_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL_OFFSET", REG_MMIO, 0x016b, 0, &mmSDMA0_RLC0_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC0_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC0_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CSA_ADDR_LO", REG_MMIO, 0x016c, 0, &mmSDMA0_RLC0_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC0_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CSA_ADDR_HI", REG_MMIO, 0x016d, 0, &mmSDMA0_RLC0_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC0_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_SUB_REMAIN", REG_MMIO, 0x016f, 0, &mmSDMA0_RLC0_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_PREEMPT", REG_MMIO, 0x0170, 0, &mmSDMA0_RLC0_PREEMPT[0], sizeof(mmSDMA0_RLC0_PREEMPT)/sizeof(mmSDMA0_RLC0_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DUMMY_REG", REG_MMIO, 0x0171, 0, &mmSDMA0_RLC0_DUMMY_REG[0], sizeof(mmSDMA0_RLC0_DUMMY_REG)/sizeof(mmSDMA0_RLC0_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0172, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0173, 0, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_AQL_CNTL", REG_MMIO, 0x0174, 0, &mmSDMA0_RLC0_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC0_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MINOR_PTR_UPDATE", REG_MMIO, 0x0175, 0, &mmSDMA0_RLC0_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC0_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC0_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA0", REG_MMIO, 0x0180, 0, &mmSDMA0_RLC0_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA1", REG_MMIO, 0x0181, 0, &mmSDMA0_RLC0_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA2", REG_MMIO, 0x0182, 0, &mmSDMA0_RLC0_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA3", REG_MMIO, 0x0183, 0, &mmSDMA0_RLC0_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA4", REG_MMIO, 0x0184, 0, &mmSDMA0_RLC0_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA5", REG_MMIO, 0x0185, 0, &mmSDMA0_RLC0_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA6", REG_MMIO, 0x0186, 0, &mmSDMA0_RLC0_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA7", REG_MMIO, 0x0187, 0, &mmSDMA0_RLC0_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA8", REG_MMIO, 0x0188, 0, &mmSDMA0_RLC0_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_CNTL", REG_MMIO, 0x0189, 0, &mmSDMA0_RLC0_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC0_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC0_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_CNTL", REG_MMIO, 0x01a0, 0, &mmSDMA0_RLC1_RB_CNTL[0], sizeof(mmSDMA0_RLC1_RB_CNTL)/sizeof(mmSDMA0_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE", REG_MMIO, 0x01a1, 0, &mmSDMA0_RLC1_RB_BASE[0], sizeof(mmSDMA0_RLC1_RB_BASE)/sizeof(mmSDMA0_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE_HI", REG_MMIO, 0x01a2, 0, &mmSDMA0_RLC1_RB_BASE_HI[0], sizeof(mmSDMA0_RLC1_RB_BASE_HI)/sizeof(mmSDMA0_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR", REG_MMIO, 0x01a3, 0, &mmSDMA0_RLC1_RB_RPTR[0], sizeof(mmSDMA0_RLC1_RB_RPTR)/sizeof(mmSDMA0_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_HI", REG_MMIO, 0x01a4, 0, &mmSDMA0_RLC1_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR", REG_MMIO, 0x01a5, 0, &mmSDMA0_RLC1_RB_WPTR[0], sizeof(mmSDMA0_RLC1_RB_WPTR)/sizeof(mmSDMA0_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_HI", REG_MMIO, 0x01a6, 0, &mmSDMA0_RLC1_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x01a7, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x01a8, 0, &mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x01a9, 0, &mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_CNTL", REG_MMIO, 0x01aa, 0, &mmSDMA0_RLC1_IB_CNTL[0], sizeof(mmSDMA0_RLC1_IB_CNTL)/sizeof(mmSDMA0_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_RPTR", REG_MMIO, 0x01ab, 0, &mmSDMA0_RLC1_IB_RPTR[0], sizeof(mmSDMA0_RLC1_IB_RPTR)/sizeof(mmSDMA0_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_OFFSET", REG_MMIO, 0x01ac, 0, &mmSDMA0_RLC1_IB_OFFSET[0], sizeof(mmSDMA0_RLC1_IB_OFFSET)/sizeof(mmSDMA0_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_LO", REG_MMIO, 0x01ad, 0, &mmSDMA0_RLC1_IB_BASE_LO[0], sizeof(mmSDMA0_RLC1_IB_BASE_LO)/sizeof(mmSDMA0_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_HI", REG_MMIO, 0x01ae, 0, &mmSDMA0_RLC1_IB_BASE_HI[0], sizeof(mmSDMA0_RLC1_IB_BASE_HI)/sizeof(mmSDMA0_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_SIZE", REG_MMIO, 0x01af, 0, &mmSDMA0_RLC1_IB_SIZE[0], sizeof(mmSDMA0_RLC1_IB_SIZE)/sizeof(mmSDMA0_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_SKIP_CNTL", REG_MMIO, 0x01b0, 0, &mmSDMA0_RLC1_SKIP_CNTL[0], sizeof(mmSDMA0_RLC1_SKIP_CNTL)/sizeof(mmSDMA0_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CONTEXT_STATUS", REG_MMIO, 0x01b1, 0, &mmSDMA0_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL", REG_MMIO, 0x01b2, 0, &mmSDMA0_RLC1_DOORBELL[0], sizeof(mmSDMA0_RLC1_DOORBELL)/sizeof(mmSDMA0_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_STATUS", REG_MMIO, 0x01c8, 0, &mmSDMA0_RLC1_STATUS[0], sizeof(mmSDMA0_RLC1_STATUS)/sizeof(mmSDMA0_RLC1_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL_LOG", REG_MMIO, 0x01c9, 0, &mmSDMA0_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC1_DOORBELL_LOG)/sizeof(mmSDMA0_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_WATERMARK", REG_MMIO, 0x01ca, 0, &mmSDMA0_RLC1_WATERMARK[0], sizeof(mmSDMA0_RLC1_WATERMARK)/sizeof(mmSDMA0_RLC1_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL_OFFSET", REG_MMIO, 0x01cb, 0, &mmSDMA0_RLC1_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC1_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC1_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CSA_ADDR_LO", REG_MMIO, 0x01cc, 0, &mmSDMA0_RLC1_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC1_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CSA_ADDR_HI", REG_MMIO, 0x01cd, 0, &mmSDMA0_RLC1_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC1_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_SUB_REMAIN", REG_MMIO, 0x01cf, 0, &mmSDMA0_RLC1_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_PREEMPT", REG_MMIO, 0x01d0, 0, &mmSDMA0_RLC1_PREEMPT[0], sizeof(mmSDMA0_RLC1_PREEMPT)/sizeof(mmSDMA0_RLC1_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DUMMY_REG", REG_MMIO, 0x01d1, 0, &mmSDMA0_RLC1_DUMMY_REG[0], sizeof(mmSDMA0_RLC1_DUMMY_REG)/sizeof(mmSDMA0_RLC1_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x01d2, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x01d3, 0, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_AQL_CNTL", REG_MMIO, 0x01d4, 0, &mmSDMA0_RLC1_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC1_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MINOR_PTR_UPDATE", REG_MMIO, 0x01d5, 0, &mmSDMA0_RLC1_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC1_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC1_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA0", REG_MMIO, 0x01e0, 0, &mmSDMA0_RLC1_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA1", REG_MMIO, 0x01e1, 0, &mmSDMA0_RLC1_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA2", REG_MMIO, 0x01e2, 0, &mmSDMA0_RLC1_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA3", REG_MMIO, 0x01e3, 0, &mmSDMA0_RLC1_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA4", REG_MMIO, 0x01e4, 0, &mmSDMA0_RLC1_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA5", REG_MMIO, 0x01e5, 0, &mmSDMA0_RLC1_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA6", REG_MMIO, 0x01e6, 0, &mmSDMA0_RLC1_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA7", REG_MMIO, 0x01e7, 0, &mmSDMA0_RLC1_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA8", REG_MMIO, 0x01e8, 0, &mmSDMA0_RLC1_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_CNTL", REG_MMIO, 0x01e9, 0, &mmSDMA0_RLC1_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC1_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC1_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_CNTL", REG_MMIO, 0x0200, 0, &mmSDMA0_RLC2_RB_CNTL[0], sizeof(mmSDMA0_RLC2_RB_CNTL)/sizeof(mmSDMA0_RLC2_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_BASE", REG_MMIO, 0x0201, 0, &mmSDMA0_RLC2_RB_BASE[0], sizeof(mmSDMA0_RLC2_RB_BASE)/sizeof(mmSDMA0_RLC2_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_BASE_HI", REG_MMIO, 0x0202, 0, &mmSDMA0_RLC2_RB_BASE_HI[0], sizeof(mmSDMA0_RLC2_RB_BASE_HI)/sizeof(mmSDMA0_RLC2_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_RPTR", REG_MMIO, 0x0203, 0, &mmSDMA0_RLC2_RB_RPTR[0], sizeof(mmSDMA0_RLC2_RB_RPTR)/sizeof(mmSDMA0_RLC2_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_RPTR_HI", REG_MMIO, 0x0204, 0, &mmSDMA0_RLC2_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC2_RB_RPTR_HI)/sizeof(mmSDMA0_RLC2_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_WPTR", REG_MMIO, 0x0205, 0, &mmSDMA0_RLC2_RB_WPTR[0], sizeof(mmSDMA0_RLC2_RB_WPTR)/sizeof(mmSDMA0_RLC2_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_WPTR_HI", REG_MMIO, 0x0206, 0, &mmSDMA0_RLC2_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC2_RB_WPTR_HI)/sizeof(mmSDMA0_RLC2_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0207, 0, &mmSDMA0_RLC2_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_RPTR_ADDR_HI", REG_MMIO, 0x0208, 0, &mmSDMA0_RLC2_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC2_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC2_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_RPTR_ADDR_LO", REG_MMIO, 0x0209, 0, &mmSDMA0_RLC2_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC2_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC2_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_CNTL", REG_MMIO, 0x020a, 0, &mmSDMA0_RLC2_IB_CNTL[0], sizeof(mmSDMA0_RLC2_IB_CNTL)/sizeof(mmSDMA0_RLC2_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_RPTR", REG_MMIO, 0x020b, 0, &mmSDMA0_RLC2_IB_RPTR[0], sizeof(mmSDMA0_RLC2_IB_RPTR)/sizeof(mmSDMA0_RLC2_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_OFFSET", REG_MMIO, 0x020c, 0, &mmSDMA0_RLC2_IB_OFFSET[0], sizeof(mmSDMA0_RLC2_IB_OFFSET)/sizeof(mmSDMA0_RLC2_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_BASE_LO", REG_MMIO, 0x020d, 0, &mmSDMA0_RLC2_IB_BASE_LO[0], sizeof(mmSDMA0_RLC2_IB_BASE_LO)/sizeof(mmSDMA0_RLC2_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_BASE_HI", REG_MMIO, 0x020e, 0, &mmSDMA0_RLC2_IB_BASE_HI[0], sizeof(mmSDMA0_RLC2_IB_BASE_HI)/sizeof(mmSDMA0_RLC2_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_SIZE", REG_MMIO, 0x020f, 0, &mmSDMA0_RLC2_IB_SIZE[0], sizeof(mmSDMA0_RLC2_IB_SIZE)/sizeof(mmSDMA0_RLC2_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_SKIP_CNTL", REG_MMIO, 0x0210, 0, &mmSDMA0_RLC2_SKIP_CNTL[0], sizeof(mmSDMA0_RLC2_SKIP_CNTL)/sizeof(mmSDMA0_RLC2_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_CONTEXT_STATUS", REG_MMIO, 0x0211, 0, &mmSDMA0_RLC2_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC2_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC2_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_DOORBELL", REG_MMIO, 0x0212, 0, &mmSDMA0_RLC2_DOORBELL[0], sizeof(mmSDMA0_RLC2_DOORBELL)/sizeof(mmSDMA0_RLC2_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_STATUS", REG_MMIO, 0x0228, 0, &mmSDMA0_RLC2_STATUS[0], sizeof(mmSDMA0_RLC2_STATUS)/sizeof(mmSDMA0_RLC2_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_DOORBELL_LOG", REG_MMIO, 0x0229, 0, &mmSDMA0_RLC2_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC2_DOORBELL_LOG)/sizeof(mmSDMA0_RLC2_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_WATERMARK", REG_MMIO, 0x022a, 0, &mmSDMA0_RLC2_WATERMARK[0], sizeof(mmSDMA0_RLC2_WATERMARK)/sizeof(mmSDMA0_RLC2_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_DOORBELL_OFFSET", REG_MMIO, 0x022b, 0, &mmSDMA0_RLC2_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC2_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC2_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_CSA_ADDR_LO", REG_MMIO, 0x022c, 0, &mmSDMA0_RLC2_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC2_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC2_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_CSA_ADDR_HI", REG_MMIO, 0x022d, 0, &mmSDMA0_RLC2_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC2_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC2_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_IB_SUB_REMAIN", REG_MMIO, 0x022f, 0, &mmSDMA0_RLC2_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC2_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC2_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_PREEMPT", REG_MMIO, 0x0230, 0, &mmSDMA0_RLC2_PREEMPT[0], sizeof(mmSDMA0_RLC2_PREEMPT)/sizeof(mmSDMA0_RLC2_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_DUMMY_REG", REG_MMIO, 0x0231, 0, &mmSDMA0_RLC2_DUMMY_REG[0], sizeof(mmSDMA0_RLC2_DUMMY_REG)/sizeof(mmSDMA0_RLC2_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0232, 0, &mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0233, 0, &mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_RB_AQL_CNTL", REG_MMIO, 0x0234, 0, &mmSDMA0_RLC2_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC2_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC2_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MINOR_PTR_UPDATE", REG_MMIO, 0x0235, 0, &mmSDMA0_RLC2_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC2_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC2_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA0", REG_MMIO, 0x0240, 0, &mmSDMA0_RLC2_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA1", REG_MMIO, 0x0241, 0, &mmSDMA0_RLC2_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA2", REG_MMIO, 0x0242, 0, &mmSDMA0_RLC2_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA3", REG_MMIO, 0x0243, 0, &mmSDMA0_RLC2_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA4", REG_MMIO, 0x0244, 0, &mmSDMA0_RLC2_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA5", REG_MMIO, 0x0245, 0, &mmSDMA0_RLC2_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA6", REG_MMIO, 0x0246, 0, &mmSDMA0_RLC2_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA7", REG_MMIO, 0x0247, 0, &mmSDMA0_RLC2_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_DATA8", REG_MMIO, 0x0248, 0, &mmSDMA0_RLC2_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC2_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC2_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC2_MIDCMD_CNTL", REG_MMIO, 0x0249, 0, &mmSDMA0_RLC2_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC2_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC2_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_CNTL", REG_MMIO, 0x0260, 0, &mmSDMA0_RLC3_RB_CNTL[0], sizeof(mmSDMA0_RLC3_RB_CNTL)/sizeof(mmSDMA0_RLC3_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_BASE", REG_MMIO, 0x0261, 0, &mmSDMA0_RLC3_RB_BASE[0], sizeof(mmSDMA0_RLC3_RB_BASE)/sizeof(mmSDMA0_RLC3_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_BASE_HI", REG_MMIO, 0x0262, 0, &mmSDMA0_RLC3_RB_BASE_HI[0], sizeof(mmSDMA0_RLC3_RB_BASE_HI)/sizeof(mmSDMA0_RLC3_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_RPTR", REG_MMIO, 0x0263, 0, &mmSDMA0_RLC3_RB_RPTR[0], sizeof(mmSDMA0_RLC3_RB_RPTR)/sizeof(mmSDMA0_RLC3_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_RPTR_HI", REG_MMIO, 0x0264, 0, &mmSDMA0_RLC3_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC3_RB_RPTR_HI)/sizeof(mmSDMA0_RLC3_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_WPTR", REG_MMIO, 0x0265, 0, &mmSDMA0_RLC3_RB_WPTR[0], sizeof(mmSDMA0_RLC3_RB_WPTR)/sizeof(mmSDMA0_RLC3_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_WPTR_HI", REG_MMIO, 0x0266, 0, &mmSDMA0_RLC3_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC3_RB_WPTR_HI)/sizeof(mmSDMA0_RLC3_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0267, 0, &mmSDMA0_RLC3_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_RPTR_ADDR_HI", REG_MMIO, 0x0268, 0, &mmSDMA0_RLC3_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC3_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC3_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_RPTR_ADDR_LO", REG_MMIO, 0x0269, 0, &mmSDMA0_RLC3_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC3_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC3_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_CNTL", REG_MMIO, 0x026a, 0, &mmSDMA0_RLC3_IB_CNTL[0], sizeof(mmSDMA0_RLC3_IB_CNTL)/sizeof(mmSDMA0_RLC3_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_RPTR", REG_MMIO, 0x026b, 0, &mmSDMA0_RLC3_IB_RPTR[0], sizeof(mmSDMA0_RLC3_IB_RPTR)/sizeof(mmSDMA0_RLC3_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_OFFSET", REG_MMIO, 0x026c, 0, &mmSDMA0_RLC3_IB_OFFSET[0], sizeof(mmSDMA0_RLC3_IB_OFFSET)/sizeof(mmSDMA0_RLC3_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_BASE_LO", REG_MMIO, 0x026d, 0, &mmSDMA0_RLC3_IB_BASE_LO[0], sizeof(mmSDMA0_RLC3_IB_BASE_LO)/sizeof(mmSDMA0_RLC3_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_BASE_HI", REG_MMIO, 0x026e, 0, &mmSDMA0_RLC3_IB_BASE_HI[0], sizeof(mmSDMA0_RLC3_IB_BASE_HI)/sizeof(mmSDMA0_RLC3_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_SIZE", REG_MMIO, 0x026f, 0, &mmSDMA0_RLC3_IB_SIZE[0], sizeof(mmSDMA0_RLC3_IB_SIZE)/sizeof(mmSDMA0_RLC3_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_SKIP_CNTL", REG_MMIO, 0x0270, 0, &mmSDMA0_RLC3_SKIP_CNTL[0], sizeof(mmSDMA0_RLC3_SKIP_CNTL)/sizeof(mmSDMA0_RLC3_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_CONTEXT_STATUS", REG_MMIO, 0x0271, 0, &mmSDMA0_RLC3_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC3_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC3_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_DOORBELL", REG_MMIO, 0x0272, 0, &mmSDMA0_RLC3_DOORBELL[0], sizeof(mmSDMA0_RLC3_DOORBELL)/sizeof(mmSDMA0_RLC3_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_STATUS", REG_MMIO, 0x0288, 0, &mmSDMA0_RLC3_STATUS[0], sizeof(mmSDMA0_RLC3_STATUS)/sizeof(mmSDMA0_RLC3_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_DOORBELL_LOG", REG_MMIO, 0x0289, 0, &mmSDMA0_RLC3_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC3_DOORBELL_LOG)/sizeof(mmSDMA0_RLC3_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_WATERMARK", REG_MMIO, 0x028a, 0, &mmSDMA0_RLC3_WATERMARK[0], sizeof(mmSDMA0_RLC3_WATERMARK)/sizeof(mmSDMA0_RLC3_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_DOORBELL_OFFSET", REG_MMIO, 0x028b, 0, &mmSDMA0_RLC3_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC3_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC3_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_CSA_ADDR_LO", REG_MMIO, 0x028c, 0, &mmSDMA0_RLC3_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC3_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC3_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_CSA_ADDR_HI", REG_MMIO, 0x028d, 0, &mmSDMA0_RLC3_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC3_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC3_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_IB_SUB_REMAIN", REG_MMIO, 0x028f, 0, &mmSDMA0_RLC3_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC3_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC3_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_PREEMPT", REG_MMIO, 0x0290, 0, &mmSDMA0_RLC3_PREEMPT[0], sizeof(mmSDMA0_RLC3_PREEMPT)/sizeof(mmSDMA0_RLC3_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_DUMMY_REG", REG_MMIO, 0x0291, 0, &mmSDMA0_RLC3_DUMMY_REG[0], sizeof(mmSDMA0_RLC3_DUMMY_REG)/sizeof(mmSDMA0_RLC3_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0292, 0, &mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0293, 0, &mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_RB_AQL_CNTL", REG_MMIO, 0x0294, 0, &mmSDMA0_RLC3_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC3_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC3_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MINOR_PTR_UPDATE", REG_MMIO, 0x0295, 0, &mmSDMA0_RLC3_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC3_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC3_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA0", REG_MMIO, 0x02a0, 0, &mmSDMA0_RLC3_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA1", REG_MMIO, 0x02a1, 0, &mmSDMA0_RLC3_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA2", REG_MMIO, 0x02a2, 0, &mmSDMA0_RLC3_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA3", REG_MMIO, 0x02a3, 0, &mmSDMA0_RLC3_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA4", REG_MMIO, 0x02a4, 0, &mmSDMA0_RLC3_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA5", REG_MMIO, 0x02a5, 0, &mmSDMA0_RLC3_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA6", REG_MMIO, 0x02a6, 0, &mmSDMA0_RLC3_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA7", REG_MMIO, 0x02a7, 0, &mmSDMA0_RLC3_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_DATA8", REG_MMIO, 0x02a8, 0, &mmSDMA0_RLC3_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC3_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC3_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC3_MIDCMD_CNTL", REG_MMIO, 0x02a9, 0, &mmSDMA0_RLC3_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC3_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC3_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_CNTL", REG_MMIO, 0x02c0, 0, &mmSDMA0_RLC4_RB_CNTL[0], sizeof(mmSDMA0_RLC4_RB_CNTL)/sizeof(mmSDMA0_RLC4_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_BASE", REG_MMIO, 0x02c1, 0, &mmSDMA0_RLC4_RB_BASE[0], sizeof(mmSDMA0_RLC4_RB_BASE)/sizeof(mmSDMA0_RLC4_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_BASE_HI", REG_MMIO, 0x02c2, 0, &mmSDMA0_RLC4_RB_BASE_HI[0], sizeof(mmSDMA0_RLC4_RB_BASE_HI)/sizeof(mmSDMA0_RLC4_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_RPTR", REG_MMIO, 0x02c3, 0, &mmSDMA0_RLC4_RB_RPTR[0], sizeof(mmSDMA0_RLC4_RB_RPTR)/sizeof(mmSDMA0_RLC4_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_RPTR_HI", REG_MMIO, 0x02c4, 0, &mmSDMA0_RLC4_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC4_RB_RPTR_HI)/sizeof(mmSDMA0_RLC4_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_WPTR", REG_MMIO, 0x02c5, 0, &mmSDMA0_RLC4_RB_WPTR[0], sizeof(mmSDMA0_RLC4_RB_WPTR)/sizeof(mmSDMA0_RLC4_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_WPTR_HI", REG_MMIO, 0x02c6, 0, &mmSDMA0_RLC4_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC4_RB_WPTR_HI)/sizeof(mmSDMA0_RLC4_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_WPTR_POLL_CNTL", REG_MMIO, 0x02c7, 0, &mmSDMA0_RLC4_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_RPTR_ADDR_HI", REG_MMIO, 0x02c8, 0, &mmSDMA0_RLC4_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC4_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC4_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_RPTR_ADDR_LO", REG_MMIO, 0x02c9, 0, &mmSDMA0_RLC4_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC4_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC4_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_CNTL", REG_MMIO, 0x02ca, 0, &mmSDMA0_RLC4_IB_CNTL[0], sizeof(mmSDMA0_RLC4_IB_CNTL)/sizeof(mmSDMA0_RLC4_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_RPTR", REG_MMIO, 0x02cb, 0, &mmSDMA0_RLC4_IB_RPTR[0], sizeof(mmSDMA0_RLC4_IB_RPTR)/sizeof(mmSDMA0_RLC4_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_OFFSET", REG_MMIO, 0x02cc, 0, &mmSDMA0_RLC4_IB_OFFSET[0], sizeof(mmSDMA0_RLC4_IB_OFFSET)/sizeof(mmSDMA0_RLC4_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_BASE_LO", REG_MMIO, 0x02cd, 0, &mmSDMA0_RLC4_IB_BASE_LO[0], sizeof(mmSDMA0_RLC4_IB_BASE_LO)/sizeof(mmSDMA0_RLC4_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_BASE_HI", REG_MMIO, 0x02ce, 0, &mmSDMA0_RLC4_IB_BASE_HI[0], sizeof(mmSDMA0_RLC4_IB_BASE_HI)/sizeof(mmSDMA0_RLC4_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_SIZE", REG_MMIO, 0x02cf, 0, &mmSDMA0_RLC4_IB_SIZE[0], sizeof(mmSDMA0_RLC4_IB_SIZE)/sizeof(mmSDMA0_RLC4_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_SKIP_CNTL", REG_MMIO, 0x02d0, 0, &mmSDMA0_RLC4_SKIP_CNTL[0], sizeof(mmSDMA0_RLC4_SKIP_CNTL)/sizeof(mmSDMA0_RLC4_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_CONTEXT_STATUS", REG_MMIO, 0x02d1, 0, &mmSDMA0_RLC4_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC4_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC4_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_DOORBELL", REG_MMIO, 0x02d2, 0, &mmSDMA0_RLC4_DOORBELL[0], sizeof(mmSDMA0_RLC4_DOORBELL)/sizeof(mmSDMA0_RLC4_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_STATUS", REG_MMIO, 0x02e8, 0, &mmSDMA0_RLC4_STATUS[0], sizeof(mmSDMA0_RLC4_STATUS)/sizeof(mmSDMA0_RLC4_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_DOORBELL_LOG", REG_MMIO, 0x02e9, 0, &mmSDMA0_RLC4_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC4_DOORBELL_LOG)/sizeof(mmSDMA0_RLC4_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_WATERMARK", REG_MMIO, 0x02ea, 0, &mmSDMA0_RLC4_WATERMARK[0], sizeof(mmSDMA0_RLC4_WATERMARK)/sizeof(mmSDMA0_RLC4_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_DOORBELL_OFFSET", REG_MMIO, 0x02eb, 0, &mmSDMA0_RLC4_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC4_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC4_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_CSA_ADDR_LO", REG_MMIO, 0x02ec, 0, &mmSDMA0_RLC4_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC4_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC4_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_CSA_ADDR_HI", REG_MMIO, 0x02ed, 0, &mmSDMA0_RLC4_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC4_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC4_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_IB_SUB_REMAIN", REG_MMIO, 0x02ef, 0, &mmSDMA0_RLC4_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC4_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC4_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_PREEMPT", REG_MMIO, 0x02f0, 0, &mmSDMA0_RLC4_PREEMPT[0], sizeof(mmSDMA0_RLC4_PREEMPT)/sizeof(mmSDMA0_RLC4_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_DUMMY_REG", REG_MMIO, 0x02f1, 0, &mmSDMA0_RLC4_DUMMY_REG[0], sizeof(mmSDMA0_RLC4_DUMMY_REG)/sizeof(mmSDMA0_RLC4_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x02f2, 0, &mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x02f3, 0, &mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_RB_AQL_CNTL", REG_MMIO, 0x02f4, 0, &mmSDMA0_RLC4_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC4_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC4_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MINOR_PTR_UPDATE", REG_MMIO, 0x02f5, 0, &mmSDMA0_RLC4_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC4_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC4_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA0", REG_MMIO, 0x0300, 0, &mmSDMA0_RLC4_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA1", REG_MMIO, 0x0301, 0, &mmSDMA0_RLC4_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA2", REG_MMIO, 0x0302, 0, &mmSDMA0_RLC4_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA3", REG_MMIO, 0x0303, 0, &mmSDMA0_RLC4_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA4", REG_MMIO, 0x0304, 0, &mmSDMA0_RLC4_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA5", REG_MMIO, 0x0305, 0, &mmSDMA0_RLC4_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA6", REG_MMIO, 0x0306, 0, &mmSDMA0_RLC4_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA7", REG_MMIO, 0x0307, 0, &mmSDMA0_RLC4_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_DATA8", REG_MMIO, 0x0308, 0, &mmSDMA0_RLC4_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC4_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC4_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC4_MIDCMD_CNTL", REG_MMIO, 0x0309, 0, &mmSDMA0_RLC4_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC4_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC4_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_CNTL", REG_MMIO, 0x0320, 0, &mmSDMA0_RLC5_RB_CNTL[0], sizeof(mmSDMA0_RLC5_RB_CNTL)/sizeof(mmSDMA0_RLC5_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_BASE", REG_MMIO, 0x0321, 0, &mmSDMA0_RLC5_RB_BASE[0], sizeof(mmSDMA0_RLC5_RB_BASE)/sizeof(mmSDMA0_RLC5_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_BASE_HI", REG_MMIO, 0x0322, 0, &mmSDMA0_RLC5_RB_BASE_HI[0], sizeof(mmSDMA0_RLC5_RB_BASE_HI)/sizeof(mmSDMA0_RLC5_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_RPTR", REG_MMIO, 0x0323, 0, &mmSDMA0_RLC5_RB_RPTR[0], sizeof(mmSDMA0_RLC5_RB_RPTR)/sizeof(mmSDMA0_RLC5_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_RPTR_HI", REG_MMIO, 0x0324, 0, &mmSDMA0_RLC5_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC5_RB_RPTR_HI)/sizeof(mmSDMA0_RLC5_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_WPTR", REG_MMIO, 0x0325, 0, &mmSDMA0_RLC5_RB_WPTR[0], sizeof(mmSDMA0_RLC5_RB_WPTR)/sizeof(mmSDMA0_RLC5_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_WPTR_HI", REG_MMIO, 0x0326, 0, &mmSDMA0_RLC5_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC5_RB_WPTR_HI)/sizeof(mmSDMA0_RLC5_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0327, 0, &mmSDMA0_RLC5_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_RPTR_ADDR_HI", REG_MMIO, 0x0328, 0, &mmSDMA0_RLC5_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC5_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC5_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_RPTR_ADDR_LO", REG_MMIO, 0x0329, 0, &mmSDMA0_RLC5_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC5_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC5_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_CNTL", REG_MMIO, 0x032a, 0, &mmSDMA0_RLC5_IB_CNTL[0], sizeof(mmSDMA0_RLC5_IB_CNTL)/sizeof(mmSDMA0_RLC5_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_RPTR", REG_MMIO, 0x032b, 0, &mmSDMA0_RLC5_IB_RPTR[0], sizeof(mmSDMA0_RLC5_IB_RPTR)/sizeof(mmSDMA0_RLC5_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_OFFSET", REG_MMIO, 0x032c, 0, &mmSDMA0_RLC5_IB_OFFSET[0], sizeof(mmSDMA0_RLC5_IB_OFFSET)/sizeof(mmSDMA0_RLC5_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_BASE_LO", REG_MMIO, 0x032d, 0, &mmSDMA0_RLC5_IB_BASE_LO[0], sizeof(mmSDMA0_RLC5_IB_BASE_LO)/sizeof(mmSDMA0_RLC5_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_BASE_HI", REG_MMIO, 0x032e, 0, &mmSDMA0_RLC5_IB_BASE_HI[0], sizeof(mmSDMA0_RLC5_IB_BASE_HI)/sizeof(mmSDMA0_RLC5_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_SIZE", REG_MMIO, 0x032f, 0, &mmSDMA0_RLC5_IB_SIZE[0], sizeof(mmSDMA0_RLC5_IB_SIZE)/sizeof(mmSDMA0_RLC5_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_SKIP_CNTL", REG_MMIO, 0x0330, 0, &mmSDMA0_RLC5_SKIP_CNTL[0], sizeof(mmSDMA0_RLC5_SKIP_CNTL)/sizeof(mmSDMA0_RLC5_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_CONTEXT_STATUS", REG_MMIO, 0x0331, 0, &mmSDMA0_RLC5_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC5_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC5_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_DOORBELL", REG_MMIO, 0x0332, 0, &mmSDMA0_RLC5_DOORBELL[0], sizeof(mmSDMA0_RLC5_DOORBELL)/sizeof(mmSDMA0_RLC5_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_STATUS", REG_MMIO, 0x0348, 0, &mmSDMA0_RLC5_STATUS[0], sizeof(mmSDMA0_RLC5_STATUS)/sizeof(mmSDMA0_RLC5_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_DOORBELL_LOG", REG_MMIO, 0x0349, 0, &mmSDMA0_RLC5_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC5_DOORBELL_LOG)/sizeof(mmSDMA0_RLC5_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_WATERMARK", REG_MMIO, 0x034a, 0, &mmSDMA0_RLC5_WATERMARK[0], sizeof(mmSDMA0_RLC5_WATERMARK)/sizeof(mmSDMA0_RLC5_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_DOORBELL_OFFSET", REG_MMIO, 0x034b, 0, &mmSDMA0_RLC5_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC5_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC5_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_CSA_ADDR_LO", REG_MMIO, 0x034c, 0, &mmSDMA0_RLC5_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC5_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC5_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_CSA_ADDR_HI", REG_MMIO, 0x034d, 0, &mmSDMA0_RLC5_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC5_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC5_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_IB_SUB_REMAIN", REG_MMIO, 0x034f, 0, &mmSDMA0_RLC5_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC5_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC5_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_PREEMPT", REG_MMIO, 0x0350, 0, &mmSDMA0_RLC5_PREEMPT[0], sizeof(mmSDMA0_RLC5_PREEMPT)/sizeof(mmSDMA0_RLC5_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_DUMMY_REG", REG_MMIO, 0x0351, 0, &mmSDMA0_RLC5_DUMMY_REG[0], sizeof(mmSDMA0_RLC5_DUMMY_REG)/sizeof(mmSDMA0_RLC5_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0352, 0, &mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0353, 0, &mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_RB_AQL_CNTL", REG_MMIO, 0x0354, 0, &mmSDMA0_RLC5_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC5_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC5_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MINOR_PTR_UPDATE", REG_MMIO, 0x0355, 0, &mmSDMA0_RLC5_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC5_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC5_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA0", REG_MMIO, 0x0360, 0, &mmSDMA0_RLC5_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA1", REG_MMIO, 0x0361, 0, &mmSDMA0_RLC5_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA2", REG_MMIO, 0x0362, 0, &mmSDMA0_RLC5_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA3", REG_MMIO, 0x0363, 0, &mmSDMA0_RLC5_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA4", REG_MMIO, 0x0364, 0, &mmSDMA0_RLC5_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA5", REG_MMIO, 0x0365, 0, &mmSDMA0_RLC5_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA6", REG_MMIO, 0x0366, 0, &mmSDMA0_RLC5_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA7", REG_MMIO, 0x0367, 0, &mmSDMA0_RLC5_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_DATA8", REG_MMIO, 0x0368, 0, &mmSDMA0_RLC5_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC5_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC5_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC5_MIDCMD_CNTL", REG_MMIO, 0x0369, 0, &mmSDMA0_RLC5_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC5_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC5_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_CNTL", REG_MMIO, 0x0380, 0, &mmSDMA0_RLC6_RB_CNTL[0], sizeof(mmSDMA0_RLC6_RB_CNTL)/sizeof(mmSDMA0_RLC6_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_BASE", REG_MMIO, 0x0381, 0, &mmSDMA0_RLC6_RB_BASE[0], sizeof(mmSDMA0_RLC6_RB_BASE)/sizeof(mmSDMA0_RLC6_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_BASE_HI", REG_MMIO, 0x0382, 0, &mmSDMA0_RLC6_RB_BASE_HI[0], sizeof(mmSDMA0_RLC6_RB_BASE_HI)/sizeof(mmSDMA0_RLC6_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_RPTR", REG_MMIO, 0x0383, 0, &mmSDMA0_RLC6_RB_RPTR[0], sizeof(mmSDMA0_RLC6_RB_RPTR)/sizeof(mmSDMA0_RLC6_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_RPTR_HI", REG_MMIO, 0x0384, 0, &mmSDMA0_RLC6_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC6_RB_RPTR_HI)/sizeof(mmSDMA0_RLC6_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_WPTR", REG_MMIO, 0x0385, 0, &mmSDMA0_RLC6_RB_WPTR[0], sizeof(mmSDMA0_RLC6_RB_WPTR)/sizeof(mmSDMA0_RLC6_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_WPTR_HI", REG_MMIO, 0x0386, 0, &mmSDMA0_RLC6_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC6_RB_WPTR_HI)/sizeof(mmSDMA0_RLC6_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0387, 0, &mmSDMA0_RLC6_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_RPTR_ADDR_HI", REG_MMIO, 0x0388, 0, &mmSDMA0_RLC6_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC6_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC6_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_RPTR_ADDR_LO", REG_MMIO, 0x0389, 0, &mmSDMA0_RLC6_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC6_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC6_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_CNTL", REG_MMIO, 0x038a, 0, &mmSDMA0_RLC6_IB_CNTL[0], sizeof(mmSDMA0_RLC6_IB_CNTL)/sizeof(mmSDMA0_RLC6_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_RPTR", REG_MMIO, 0x038b, 0, &mmSDMA0_RLC6_IB_RPTR[0], sizeof(mmSDMA0_RLC6_IB_RPTR)/sizeof(mmSDMA0_RLC6_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_OFFSET", REG_MMIO, 0x038c, 0, &mmSDMA0_RLC6_IB_OFFSET[0], sizeof(mmSDMA0_RLC6_IB_OFFSET)/sizeof(mmSDMA0_RLC6_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_BASE_LO", REG_MMIO, 0x038d, 0, &mmSDMA0_RLC6_IB_BASE_LO[0], sizeof(mmSDMA0_RLC6_IB_BASE_LO)/sizeof(mmSDMA0_RLC6_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_BASE_HI", REG_MMIO, 0x038e, 0, &mmSDMA0_RLC6_IB_BASE_HI[0], sizeof(mmSDMA0_RLC6_IB_BASE_HI)/sizeof(mmSDMA0_RLC6_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_SIZE", REG_MMIO, 0x038f, 0, &mmSDMA0_RLC6_IB_SIZE[0], sizeof(mmSDMA0_RLC6_IB_SIZE)/sizeof(mmSDMA0_RLC6_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_SKIP_CNTL", REG_MMIO, 0x0390, 0, &mmSDMA0_RLC6_SKIP_CNTL[0], sizeof(mmSDMA0_RLC6_SKIP_CNTL)/sizeof(mmSDMA0_RLC6_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_CONTEXT_STATUS", REG_MMIO, 0x0391, 0, &mmSDMA0_RLC6_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC6_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC6_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_DOORBELL", REG_MMIO, 0x0392, 0, &mmSDMA0_RLC6_DOORBELL[0], sizeof(mmSDMA0_RLC6_DOORBELL)/sizeof(mmSDMA0_RLC6_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_STATUS", REG_MMIO, 0x03a8, 0, &mmSDMA0_RLC6_STATUS[0], sizeof(mmSDMA0_RLC6_STATUS)/sizeof(mmSDMA0_RLC6_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_DOORBELL_LOG", REG_MMIO, 0x03a9, 0, &mmSDMA0_RLC6_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC6_DOORBELL_LOG)/sizeof(mmSDMA0_RLC6_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_WATERMARK", REG_MMIO, 0x03aa, 0, &mmSDMA0_RLC6_WATERMARK[0], sizeof(mmSDMA0_RLC6_WATERMARK)/sizeof(mmSDMA0_RLC6_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_DOORBELL_OFFSET", REG_MMIO, 0x03ab, 0, &mmSDMA0_RLC6_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC6_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC6_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_CSA_ADDR_LO", REG_MMIO, 0x03ac, 0, &mmSDMA0_RLC6_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC6_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC6_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_CSA_ADDR_HI", REG_MMIO, 0x03ad, 0, &mmSDMA0_RLC6_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC6_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC6_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_IB_SUB_REMAIN", REG_MMIO, 0x03af, 0, &mmSDMA0_RLC6_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC6_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC6_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_PREEMPT", REG_MMIO, 0x03b0, 0, &mmSDMA0_RLC6_PREEMPT[0], sizeof(mmSDMA0_RLC6_PREEMPT)/sizeof(mmSDMA0_RLC6_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_DUMMY_REG", REG_MMIO, 0x03b1, 0, &mmSDMA0_RLC6_DUMMY_REG[0], sizeof(mmSDMA0_RLC6_DUMMY_REG)/sizeof(mmSDMA0_RLC6_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x03b2, 0, &mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x03b3, 0, &mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_RB_AQL_CNTL", REG_MMIO, 0x03b4, 0, &mmSDMA0_RLC6_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC6_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC6_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MINOR_PTR_UPDATE", REG_MMIO, 0x03b5, 0, &mmSDMA0_RLC6_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC6_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC6_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA0", REG_MMIO, 0x03c0, 0, &mmSDMA0_RLC6_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA1", REG_MMIO, 0x03c1, 0, &mmSDMA0_RLC6_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA2", REG_MMIO, 0x03c2, 0, &mmSDMA0_RLC6_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA3", REG_MMIO, 0x03c3, 0, &mmSDMA0_RLC6_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA4", REG_MMIO, 0x03c4, 0, &mmSDMA0_RLC6_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA5", REG_MMIO, 0x03c5, 0, &mmSDMA0_RLC6_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA6", REG_MMIO, 0x03c6, 0, &mmSDMA0_RLC6_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA7", REG_MMIO, 0x03c7, 0, &mmSDMA0_RLC6_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_DATA8", REG_MMIO, 0x03c8, 0, &mmSDMA0_RLC6_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC6_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC6_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC6_MIDCMD_CNTL", REG_MMIO, 0x03c9, 0, &mmSDMA0_RLC6_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC6_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC6_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_CNTL", REG_MMIO, 0x03e0, 0, &mmSDMA0_RLC7_RB_CNTL[0], sizeof(mmSDMA0_RLC7_RB_CNTL)/sizeof(mmSDMA0_RLC7_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_BASE", REG_MMIO, 0x03e1, 0, &mmSDMA0_RLC7_RB_BASE[0], sizeof(mmSDMA0_RLC7_RB_BASE)/sizeof(mmSDMA0_RLC7_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_BASE_HI", REG_MMIO, 0x03e2, 0, &mmSDMA0_RLC7_RB_BASE_HI[0], sizeof(mmSDMA0_RLC7_RB_BASE_HI)/sizeof(mmSDMA0_RLC7_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_RPTR", REG_MMIO, 0x03e3, 0, &mmSDMA0_RLC7_RB_RPTR[0], sizeof(mmSDMA0_RLC7_RB_RPTR)/sizeof(mmSDMA0_RLC7_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_RPTR_HI", REG_MMIO, 0x03e4, 0, &mmSDMA0_RLC7_RB_RPTR_HI[0], sizeof(mmSDMA0_RLC7_RB_RPTR_HI)/sizeof(mmSDMA0_RLC7_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_WPTR", REG_MMIO, 0x03e5, 0, &mmSDMA0_RLC7_RB_WPTR[0], sizeof(mmSDMA0_RLC7_RB_WPTR)/sizeof(mmSDMA0_RLC7_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_WPTR_HI", REG_MMIO, 0x03e6, 0, &mmSDMA0_RLC7_RB_WPTR_HI[0], sizeof(mmSDMA0_RLC7_RB_WPTR_HI)/sizeof(mmSDMA0_RLC7_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_WPTR_POLL_CNTL", REG_MMIO, 0x03e7, 0, &mmSDMA0_RLC7_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_RPTR_ADDR_HI", REG_MMIO, 0x03e8, 0, &mmSDMA0_RLC7_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC7_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC7_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_RPTR_ADDR_LO", REG_MMIO, 0x03e9, 0, &mmSDMA0_RLC7_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC7_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC7_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_CNTL", REG_MMIO, 0x03ea, 0, &mmSDMA0_RLC7_IB_CNTL[0], sizeof(mmSDMA0_RLC7_IB_CNTL)/sizeof(mmSDMA0_RLC7_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_RPTR", REG_MMIO, 0x03eb, 0, &mmSDMA0_RLC7_IB_RPTR[0], sizeof(mmSDMA0_RLC7_IB_RPTR)/sizeof(mmSDMA0_RLC7_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_OFFSET", REG_MMIO, 0x03ec, 0, &mmSDMA0_RLC7_IB_OFFSET[0], sizeof(mmSDMA0_RLC7_IB_OFFSET)/sizeof(mmSDMA0_RLC7_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_BASE_LO", REG_MMIO, 0x03ed, 0, &mmSDMA0_RLC7_IB_BASE_LO[0], sizeof(mmSDMA0_RLC7_IB_BASE_LO)/sizeof(mmSDMA0_RLC7_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_BASE_HI", REG_MMIO, 0x03ee, 0, &mmSDMA0_RLC7_IB_BASE_HI[0], sizeof(mmSDMA0_RLC7_IB_BASE_HI)/sizeof(mmSDMA0_RLC7_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_SIZE", REG_MMIO, 0x03ef, 0, &mmSDMA0_RLC7_IB_SIZE[0], sizeof(mmSDMA0_RLC7_IB_SIZE)/sizeof(mmSDMA0_RLC7_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_SKIP_CNTL", REG_MMIO, 0x03f0, 0, &mmSDMA0_RLC7_SKIP_CNTL[0], sizeof(mmSDMA0_RLC7_SKIP_CNTL)/sizeof(mmSDMA0_RLC7_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_CONTEXT_STATUS", REG_MMIO, 0x03f1, 0, &mmSDMA0_RLC7_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC7_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC7_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_DOORBELL", REG_MMIO, 0x03f2, 0, &mmSDMA0_RLC7_DOORBELL[0], sizeof(mmSDMA0_RLC7_DOORBELL)/sizeof(mmSDMA0_RLC7_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_STATUS", REG_MMIO, 0x0408, 0, &mmSDMA0_RLC7_STATUS[0], sizeof(mmSDMA0_RLC7_STATUS)/sizeof(mmSDMA0_RLC7_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_DOORBELL_LOG", REG_MMIO, 0x0409, 0, &mmSDMA0_RLC7_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC7_DOORBELL_LOG)/sizeof(mmSDMA0_RLC7_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_WATERMARK", REG_MMIO, 0x040a, 0, &mmSDMA0_RLC7_WATERMARK[0], sizeof(mmSDMA0_RLC7_WATERMARK)/sizeof(mmSDMA0_RLC7_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_DOORBELL_OFFSET", REG_MMIO, 0x040b, 0, &mmSDMA0_RLC7_DOORBELL_OFFSET[0], sizeof(mmSDMA0_RLC7_DOORBELL_OFFSET)/sizeof(mmSDMA0_RLC7_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_CSA_ADDR_LO", REG_MMIO, 0x040c, 0, &mmSDMA0_RLC7_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC7_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC7_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_CSA_ADDR_HI", REG_MMIO, 0x040d, 0, &mmSDMA0_RLC7_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC7_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC7_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_IB_SUB_REMAIN", REG_MMIO, 0x040f, 0, &mmSDMA0_RLC7_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC7_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC7_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_PREEMPT", REG_MMIO, 0x0410, 0, &mmSDMA0_RLC7_PREEMPT[0], sizeof(mmSDMA0_RLC7_PREEMPT)/sizeof(mmSDMA0_RLC7_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_DUMMY_REG", REG_MMIO, 0x0411, 0, &mmSDMA0_RLC7_DUMMY_REG[0], sizeof(mmSDMA0_RLC7_DUMMY_REG)/sizeof(mmSDMA0_RLC7_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0412, 0, &mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0413, 0, &mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_RB_AQL_CNTL", REG_MMIO, 0x0414, 0, &mmSDMA0_RLC7_RB_AQL_CNTL[0], sizeof(mmSDMA0_RLC7_RB_AQL_CNTL)/sizeof(mmSDMA0_RLC7_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MINOR_PTR_UPDATE", REG_MMIO, 0x0415, 0, &mmSDMA0_RLC7_MINOR_PTR_UPDATE[0], sizeof(mmSDMA0_RLC7_MINOR_PTR_UPDATE)/sizeof(mmSDMA0_RLC7_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA0", REG_MMIO, 0x0420, 0, &mmSDMA0_RLC7_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA1", REG_MMIO, 0x0421, 0, &mmSDMA0_RLC7_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA2", REG_MMIO, 0x0422, 0, &mmSDMA0_RLC7_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA3", REG_MMIO, 0x0423, 0, &mmSDMA0_RLC7_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA4", REG_MMIO, 0x0424, 0, &mmSDMA0_RLC7_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA5", REG_MMIO, 0x0425, 0, &mmSDMA0_RLC7_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA6", REG_MMIO, 0x0426, 0, &mmSDMA0_RLC7_MIDCMD_DATA6[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA6)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA7", REG_MMIO, 0x0427, 0, &mmSDMA0_RLC7_MIDCMD_DATA7[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA7)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_DATA8", REG_MMIO, 0x0428, 0, &mmSDMA0_RLC7_MIDCMD_DATA8[0], sizeof(mmSDMA0_RLC7_MIDCMD_DATA8)/sizeof(mmSDMA0_RLC7_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA0_RLC7_MIDCMD_CNTL", REG_MMIO, 0x0429, 0, &mmSDMA0_RLC7_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC7_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC7_MIDCMD_CNTL[0]), 0, 0 },
diff --git a/src/lib/ip/sdma142.c b/src/lib/ip/sdma142.c
new file mode 100644
index 0000000..eedbc1e
--- /dev/null
+++ b/src/lib/ip/sdma142.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "sdma142_bits.i"
+
+static const struct umr_reg_soc15 sdma142_registers[] = {
+#include "sdma142_regs.i"
+};
+
+struct umr_ip_block *umr_create_sdma142(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "sdma142";
+	ip->no_regs = sizeof(sdma142_registers)/sizeof(sdma142_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(ip->regs[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+
+	if (umr_transfer_soc15_to_reg(options, soc15_offsets, "SDMA1", sdma142_registers, ip)) {
+		free(ip);
+		return NULL;
+	}
+
+	return ip;
+}
diff --git a/src/lib/ip/sdma142_bits.i b/src/lib/ip/sdma142_bits.i
new file mode 100644
index 0000000..31cdadd
--- /dev/null
+++ b/src/lib/ip/sdma142_bits.i
@@ -0,0 +1,2218 @@
+static struct umr_bitfield mmSDMA1_UCODE_ADDR[] = {
+	 { "VALUE", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CNTL[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 30, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_CNTL[] = {
+	 { "PRIV", 0, 0, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE0[] = {
+	 { "SDMA1_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR_HI", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_CNTL", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE1[] = {
+	 { "SDMA1_GFX_STATUS", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_GFX_DOORBELL_OFFSET", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
+	 { "VOID_REG2", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_ADDR_HI", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_ADDR_LO", 19, 19, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_AQL_CNTL", 20, 20, &umr_bitfield_default },
+	 { "SDMA1_GFX_MINOR_PTR_UPDATE", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE2[] = {
+	 { "SDMA1_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA6", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA7", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA8", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_CNTL", 9, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE0[] = {
+	 { "SDMA1_UCODE_ADDR", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_UCODE_DATA", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_REGISTER_SECURITY_CNTL", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_VM_CNTL", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_LO", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_ACTIVE_FCN_ID", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_VIRT_RESET_REQ", 9, 9, &umr_bitfield_default },
+	 { "RESERVED10", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_CONTEXT_REG_TYPE0", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_CONTEXT_REG_TYPE1", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_CONTEXT_REG_TYPE2", 13, 13, &umr_bitfield_default },
+	 { "SDMA1_CONTEXT_REG_TYPE3", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_PUB_REG_TYPE0", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_PUB_REG_TYPE1", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_PUB_REG_TYPE2", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_PUB_REG_TYPE3", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_MMHUB_CNTL", 19, 19, &umr_bitfield_default },
+	 { "RESERVED_FOR_PSPSMU_ACCESS_ONLY", 20, 24, &umr_bitfield_default },
+	 { "SDMA1_CONTEXT_GROUP_BOUNDARY", 25, 25, &umr_bitfield_default },
+	 { "SDMA1_POWER_CNTL", 26, 26, &umr_bitfield_default },
+	 { "SDMA1_CLK_CTRL", 27, 27, &umr_bitfield_default },
+	 { "SDMA1_CNTL", 28, 28, &umr_bitfield_default },
+	 { "SDMA1_CHICKEN_BITS", 29, 29, &umr_bitfield_default },
+	 { "SDMA1_GB_ADDR_CONFIG", 30, 30, &umr_bitfield_default },
+	 { "SDMA1_GB_ADDR_CONFIG_READ", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE1[] = {
+	 { "SDMA1_RB_RPTR_FETCH_HI", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_SEM_WAIT_FAIL_TIMER_CNTL", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_RB_RPTR_FETCH", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_IB_OFFSET_FETCH", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_PROGRAM", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_STATUS_REG", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_STATUS1_REG", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_RD_BURST_CNTL", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_HBM_PAGE_CONFIG", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_UCODE_CHECKSUM", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_F32_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_FREEZE", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_PHASE0_QUANTUM", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_PHASE1_QUANTUM", 13, 13, &umr_bitfield_default },
+	 { "SDMA_POWER_GATING", 14, 14, &umr_bitfield_default },
+	 { "SDMA_PGFSM_CONFIG", 15, 15, &umr_bitfield_default },
+	 { "SDMA_PGFSM_WRITE", 16, 16, &umr_bitfield_default },
+	 { "SDMA_PGFSM_READ", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_EDC_CONFIG", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_BA_THRESHOLD", 19, 19, &umr_bitfield_default },
+	 { "SDMA1_ID", 20, 20, &umr_bitfield_default },
+	 { "SDMA1_VERSION", 21, 21, &umr_bitfield_default },
+	 { "SDMA1_EDC_COUNTER", 22, 22, &umr_bitfield_default },
+	 { "SDMA1_EDC_COUNTER_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "SDMA1_STATUS2_REG", 24, 24, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_CNTL", 25, 25, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_PREOP_LO", 26, 26, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_PREOP_HI", 27, 27, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_CNTL", 28, 28, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_WATERMK", 29, 29, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_RD_STATUS", 30, 30, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_WR_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE2[] = {
+	 { "SDMA1_UTCL1_INV0", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_INV1", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_INV2", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_RD_XNACK0", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_RD_XNACK1", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_WR_XNACK0", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_WR_XNACK1", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_UTCL1_PAGE", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_POWER_CNTL_IDLE", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_RELAX_ORDERING_LUT", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_CHICKEN_BITS_2", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_STATUS3_REG", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_PHYSICAL_ADDR_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA1_PHYSICAL_ADDR_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_PHASE2_QUANTUM", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_ERROR_LOG", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_PUB_DUMMY_REG0", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_PUB_DUMMY_REG1", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_PUB_DUMMY_REG2", 19, 19, &umr_bitfield_default },
+	 { "SDMA1_PUB_DUMMY_REG3", 20, 20, &umr_bitfield_default },
+	 { "SDMA1_F32_COUNTER", 21, 21, &umr_bitfield_default },
+	 { "SDMA1_PERFMON_CNTL", 23, 23, &umr_bitfield_default },
+	 { "SDMA1_PERFCOUNTER0_RESULT", 24, 24, &umr_bitfield_default },
+	 { "SDMA1_PERFCOUNTER1_RESULT", 25, 25, &umr_bitfield_default },
+	 { "SDMA1_PERFCOUNTER_TAG_DELAY_RANGE", 26, 26, &umr_bitfield_default },
+	 { "SDMA1_CRD_CNTL", 27, 27, &umr_bitfield_default },
+	 { "SDMA1_GPU_IOV_VIOLATION_LOG", 29, 29, &umr_bitfield_default },
+	 { "SDMA1_ULV_CNTL", 30, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE3[] = {
+	 { "SDMA1_EA_DBIT_ADDR_DATA", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_EA_DBIT_ADDR_INDEX", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_MMHUB_CNTL[] = {
+	 { "UNIT_ID", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_GROUP_BOUNDARY[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_POWER_CNTL[] = {
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
+	 { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
+	 { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UTC_L1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "WRITE_BURST_LENGTH", 8, 9, &umr_bitfield_default },
+	 { "WRITE_BURST_WAIT_CYCLE", 10, 12, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "RAW_CHECK_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+	 { "TIME_BASED_QOS", 25, 25, &umr_bitfield_default },
+	 { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
+	 { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
+	 { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_BANKS", 12, 14, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GB_ADDR_CONFIG_READ[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 3, 5, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_BANKS", 12, 14, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "EX_START", 15, 15, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RD_BURST_CNTL[] = {
+	 { "RD_BURST", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUFFER_RD_BURST", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_HBM_PAGE_CONFIG[] = {
+	 { "PAGE_SIZE_EXPONENT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_CHECKSUM[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_FREEZE[] = {
+	 { "PREEMPT", 0, 0, &umr_bitfield_default },
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+	 { "F32_FREEZE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_BA_THRESHOLD[] = {
+	 { "READ_THRES", 0, 9, &umr_bitfield_default },
+	 { "WRITE_THRES", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VERSION[] = {
+	 { "MINVER", 0, 6, &umr_bitfield_default },
+	 { "MAJVER", 8, 14, &umr_bitfield_default },
+	 { "REV", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EDC_COUNTER[] = {
+	 { "SDMA_UCODE_BUF_SED", 0, 0, &umr_bitfield_default },
+	 { "SDMA_RB_CMD_BUF_SED", 2, 2, &umr_bitfield_default },
+	 { "SDMA_IB_CMD_BUF_SED", 3, 3, &umr_bitfield_default },
+	 { "SDMA_UTCL1_RD_FIFO_SED", 4, 4, &umr_bitfield_default },
+	 { "SDMA_UTCL1_RDBST_FIFO_SED", 5, 5, &umr_bitfield_default },
+	 { "SDMA_DATA_LUT_FIFO_SED", 6, 6, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF0_SED", 7, 7, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF1_SED", 8, 8, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF2_SED", 9, 9, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF3_SED", 10, 10, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF4_SED", 11, 11, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF5_SED", 12, 12, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF6_SED", 13, 13, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF7_SED", 14, 14, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF8_SED", 15, 15, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF9_SED", 16, 16, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF10_SED", 17, 17, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF11_SED", 18, 18, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF12_SED", 19, 19, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF13_SED", 20, 20, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF14_SED", 21, 21, &umr_bitfield_default },
+	 { "SDMA_MBANK_DATA_BUF15_SED", 22, 22, &umr_bitfield_default },
+	 { "SDMA_SPLIT_DAT_BUF_SED", 23, 23, &umr_bitfield_default },
+	 { "SDMA_MC_WR_ADDR_FIFO_SED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EDC_COUNTER_CLEAR[] = {
+	 { "DUMMY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS2_REG[] = {
+	 { "ID", 0, 1, &umr_bitfield_default },
+	 { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
+	 { "CMD_OP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_CNTL[] = {
+	 { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
+	 { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_HI[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_CNTL[] = {
+	 { "REDO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REDO_DELAY", 1, 10, &umr_bitfield_default },
+	 { "REDO_WATERMK", 11, 13, &umr_bitfield_default },
+	 { "INVACK_DELAY", 14, 23, &umr_bitfield_default },
+	 { "REQL2_CREDIT", 24, 28, &umr_bitfield_default },
+	 { "VADDR_WATERMK", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_WATERMK[] = {
+	 { "REQMC_WATERMK", 0, 8, &umr_bitfield_default },
+	 { "REQPG_WATERMK", 9, 16, &umr_bitfield_default },
+	 { "INVREQ_WATERMK", 17, 24, &umr_bitfield_default },
+	 { "XNACK_WATERMK", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_RD_STATUS[] = {
+	 { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
+	 { "PAGE_NULL", 19, 19, &umr_bitfield_default },
+	 { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
+	 { "CE_L1_STALL", 21, 21, &umr_bitfield_default },
+	 { "NEXT_RD_VECTOR", 22, 25, &umr_bitfield_default },
+	 { "MERGE_STATE", 26, 28, &umr_bitfield_default },
+	 { "ADDR_RD_RTR", 29, 29, &umr_bitfield_default },
+	 { "WPTR_POLLING", 30, 30, &umr_bitfield_default },
+	 { "INVREQ_SIZE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_WR_STATUS[] = {
+	 { "RQMC_RET_ADDR_FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_EMPTY", 1, 1, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_EMPTY", 3, 3, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_EMPTY", 4, 4, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_EMPTY", 6, 6, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_EMPTY", 7, 7, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "RQMC_RET_ADDR_FIFO_FULL", 9, 9, &umr_bitfield_default },
+	 { "RQMC_REQ_FIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "RTPG_RET_BUF_FULL", 11, 11, &umr_bitfield_default },
+	 { "RTPG_VADDR_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "RQPG_HEAD_VIRT_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RQPG_REDO_FIFO_FULL", 14, 14, &umr_bitfield_default },
+	 { "RQPG_REQPAGE_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "RQPG_XNACK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "RQPG_INVREQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "PAGE_FAULT", 18, 18, &umr_bitfield_default },
+	 { "PAGE_NULL", 19, 19, &umr_bitfield_default },
+	 { "REQL2_IDLE", 20, 20, &umr_bitfield_default },
+	 { "F32_WR_RTR", 21, 21, &umr_bitfield_default },
+	 { "NEXT_WR_VECTOR", 22, 24, &umr_bitfield_default },
+	 { "MERGE_STATE", 25, 27, &umr_bitfield_default },
+	 { "RPTR_DATA_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "RPTR_DATA_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "WRREQ_DATA_FIFO_EMPTY", 30, 30, &umr_bitfield_default },
+	 { "WRREQ_DATA_FIFO_FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_INV0[] = {
+	 { "INV_MIDDLE", 0, 0, &umr_bitfield_default },
+	 { "RD_TIMEOUT", 1, 1, &umr_bitfield_default },
+	 { "WR_TIMEOUT", 2, 2, &umr_bitfield_default },
+	 { "RD_IN_INVADR", 3, 3, &umr_bitfield_default },
+	 { "WR_IN_INVADR", 4, 4, &umr_bitfield_default },
+	 { "PAGE_NULL_SW", 5, 5, &umr_bitfield_default },
+	 { "XNACK_IS_INVADR", 6, 6, &umr_bitfield_default },
+	 { "INVREQ_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "NACK_TIMEOUT_SW", 8, 8, &umr_bitfield_default },
+	 { "NFLUSH_INV_IDLE", 9, 9, &umr_bitfield_default },
+	 { "FLUSH_INV_IDLE", 10, 10, &umr_bitfield_default },
+	 { "INV_FLUSHTYPE", 11, 11, &umr_bitfield_default },
+	 { "INV_VMID_VEC", 12, 27, &umr_bitfield_default },
+	 { "INV_ADDR_HI", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_INV1[] = {
+	 { "INV_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_INV2[] = {
+	 { "INV_NFLUSH_VMID_VEC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_RD_XNACK0[] = {
+	 { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_RD_XNACK1[] = {
+	 { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "XNACK_VMID", 4, 7, &umr_bitfield_default },
+	 { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
+	 { "IS_XNACK", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_WR_XNACK0[] = {
+	 { "XNACK_ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_WR_XNACK1[] = {
+	 { "XNACK_ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "XNACK_VMID", 4, 7, &umr_bitfield_default },
+	 { "XNACK_VECTOR", 8, 25, &umr_bitfield_default },
+	 { "IS_XNACK", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_TIMEOUT[] = {
+	 { "RD_XNACK_LIMIT", 0, 15, &umr_bitfield_default },
+	 { "WR_XNACK_LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UTCL1_PAGE[] = {
+	 { "VM_HOLE", 0, 0, &umr_bitfield_default },
+	 { "REQ_TYPE", 1, 4, &umr_bitfield_default },
+	 { "USE_MTYPE", 6, 8, &umr_bitfield_default },
+	 { "USE_PT_SNOOP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_POWER_CNTL_IDLE[] = {
+	 { "DELAY0", 0, 15, &umr_bitfield_default },
+	 { "DELAY1", 16, 23, &umr_bitfield_default },
+	 { "DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RELAX_ORDERING_LUT[] = {
+	 { "RESERVED0", 0, 0, &umr_bitfield_default },
+	 { "COPY", 1, 1, &umr_bitfield_default },
+	 { "WRITE", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+	 { "FENCE", 5, 5, &umr_bitfield_default },
+	 { "RESERVED76", 6, 7, &umr_bitfield_default },
+	 { "POLL_MEM", 8, 8, &umr_bitfield_default },
+	 { "COND_EXE", 9, 9, &umr_bitfield_default },
+	 { "ATOMIC", 10, 10, &umr_bitfield_default },
+	 { "CONST_FILL", 11, 11, &umr_bitfield_default },
+	 { "PTEPDE", 12, 12, &umr_bitfield_default },
+	 { "TIMESTAMP", 13, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 26, &umr_bitfield_default },
+	 { "WORLD_SWITCH", 27, 27, &umr_bitfield_default },
+	 { "RPTR_WRB", 28, 28, &umr_bitfield_default },
+	 { "WPTR_POLL", 29, 29, &umr_bitfield_default },
+	 { "IB_FETCH", 30, 30, &umr_bitfield_default },
+	 { "RB_FETCH", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CHICKEN_BITS_2[] = {
+	 { "F32_CMD_PROC_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS3_REG[] = {
+	 { "CMD_OP_STATUS", 0, 15, &umr_bitfield_default },
+	 { "PREV_VM_CMD", 16, 19, &umr_bitfield_default },
+	 { "EXCEPTION_IDLE", 20, 20, &umr_bitfield_default },
+	 { "QUEUE_ID_MATCH", 21, 21, &umr_bitfield_default },
+	 { "INT_QUEUE_ID", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHYSICAL_ADDR_LO[] = {
+	 { "D_VALID", 0, 0, &umr_bitfield_default },
+	 { "DIRTY", 1, 1, &umr_bitfield_default },
+	 { "PHY_VALID", 2, 2, &umr_bitfield_default },
+	 { "ADDR", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHYSICAL_ADDR_HI[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE2_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ERROR_LOG[] = {
+	 { "OVERRIDE", 0, 15, &umr_bitfield_default },
+	 { "STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG2[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_DUMMY_REG3[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_F32_COUNTER[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 9, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 10, 10, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 11, 11, &umr_bitfield_default },
+	 { "PERF_SEL1", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE[] = {
+	 { "RANGE_LOW", 0, 13, &umr_bitfield_default },
+	 { "RANGE_HIGH", 14, 27, &umr_bitfield_default },
+	 { "SELECT_RW", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CRD_CNTL[] = {
+	 { "MC_WRREQ_CREDIT", 7, 12, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GPU_IOV_VIOLATION_LOG[] = {
+	 { "VIOLATION_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MULTIPLE_VIOLATION_STATUS", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "WRITE_OPERATION", 18, 18, &umr_bitfield_default },
+	 { "VF", 19, 19, &umr_bitfield_default },
+	 { "VFID", 20, 23, &umr_bitfield_default },
+	 { "INITIATOR_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ULV_CNTL[] = {
+	 { "HYSTERESIS", 0, 4, &umr_bitfield_default },
+	 { "ENTER_ULV_INT_CLR", 27, 27, &umr_bitfield_default },
+	 { "EXIT_ULV_INT_CLR", 28, 28, &umr_bitfield_default },
+	 { "ENTER_ULV_INT", 29, 29, &umr_bitfield_default },
+	 { "EXIT_ULV_INT", 30, 30, &umr_bitfield_default },
+	 { "ULV_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EA_DBIT_ADDR_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EA_DBIT_ADDR_INDEX[] = {
+	 { "VALUE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PAGE_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC2_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC3_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC4_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC5_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC6_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_RPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_RPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_WPTR_HI[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_RPTR_ADDR_LO[] = {
+	 { "RPTR_WB_IDLE", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_DOORBELL[] = {
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_STATUS[] = {
+	 { "WPTR_UPDATE_FAIL_COUNT", 0, 7, &umr_bitfield_default },
+	 { "WPTR_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_DOORBELL_OFFSET[] = {
+	 { "OFFSET", 2, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_RB_AQL_CNTL[] = {
+	 { "AQL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AQL_PACKET_SIZE", 1, 7, &umr_bitfield_default },
+	 { "PACKET_STEP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MINOR_PTR_UPDATE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA6[] = {
+	 { "DATA6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA7[] = {
+	 { "DATA7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_DATA8[] = {
+	 { "DATA8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC7_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/sdma142_regs.i b/src/lib/ip/sdma142_regs.i
new file mode 100644
index 0000000..ba94635
--- /dev/null
+++ b/src/lib/ip/sdma142_regs.i
@@ -0,0 +1,505 @@
+	{ "mmSDMA1_UCODE_ADDR", REG_MMIO, 0x0000, 0, &mmSDMA1_UCODE_ADDR[0], sizeof(mmSDMA1_UCODE_ADDR)/sizeof(mmSDMA1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_DATA", REG_MMIO, 0x0001, 0, &mmSDMA1_UCODE_DATA[0], sizeof(mmSDMA1_UCODE_DATA)/sizeof(mmSDMA1_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA1_VM_CNTL", REG_MMIO, 0x0004, 0, &mmSDMA1_VM_CNTL[0], sizeof(mmSDMA1_VM_CNTL)/sizeof(mmSDMA1_VM_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_LO", REG_MMIO, 0x0005, 0, &mmSDMA1_VM_CTX_LO[0], sizeof(mmSDMA1_VM_CTX_LO)/sizeof(mmSDMA1_VM_CTX_LO[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_HI", REG_MMIO, 0x0006, 0, &mmSDMA1_VM_CTX_HI[0], sizeof(mmSDMA1_VM_CTX_HI)/sizeof(mmSDMA1_VM_CTX_HI[0]), 0, 0 },
+	{ "mmSDMA1_ACTIVE_FCN_ID", REG_MMIO, 0x0007, 0, &mmSDMA1_ACTIVE_FCN_ID[0], sizeof(mmSDMA1_ACTIVE_FCN_ID)/sizeof(mmSDMA1_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_CNTL", REG_MMIO, 0x0008, 0, &mmSDMA1_VM_CTX_CNTL[0], sizeof(mmSDMA1_VM_CTX_CNTL)/sizeof(mmSDMA1_VM_CTX_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_VIRT_RESET_REQ", REG_MMIO, 0x0009, 0, &mmSDMA1_VIRT_RESET_REQ[0], sizeof(mmSDMA1_VIRT_RESET_REQ)/sizeof(mmSDMA1_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSDMA1_VF_ENABLE", REG_MMIO, 0x000a, 0, &mmSDMA1_VF_ENABLE[0], sizeof(mmSDMA1_VF_ENABLE)/sizeof(mmSDMA1_VF_ENABLE[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE0", REG_MMIO, 0x000b, 0, &mmSDMA1_CONTEXT_REG_TYPE0[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE0)/sizeof(mmSDMA1_CONTEXT_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE1", REG_MMIO, 0x000c, 0, &mmSDMA1_CONTEXT_REG_TYPE1[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE1)/sizeof(mmSDMA1_CONTEXT_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE2", REG_MMIO, 0x000d, 0, &mmSDMA1_CONTEXT_REG_TYPE2[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE2)/sizeof(mmSDMA1_CONTEXT_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE3", REG_MMIO, 0x000e, 0, &mmSDMA1_CONTEXT_REG_TYPE3[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE3)/sizeof(mmSDMA1_CONTEXT_REG_TYPE3[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE0", REG_MMIO, 0x000f, 0, &mmSDMA1_PUB_REG_TYPE0[0], sizeof(mmSDMA1_PUB_REG_TYPE0)/sizeof(mmSDMA1_PUB_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE1", REG_MMIO, 0x0010, 0, &mmSDMA1_PUB_REG_TYPE1[0], sizeof(mmSDMA1_PUB_REG_TYPE1)/sizeof(mmSDMA1_PUB_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE2", REG_MMIO, 0x0011, 0, &mmSDMA1_PUB_REG_TYPE2[0], sizeof(mmSDMA1_PUB_REG_TYPE2)/sizeof(mmSDMA1_PUB_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE3", REG_MMIO, 0x0012, 0, &mmSDMA1_PUB_REG_TYPE3[0], sizeof(mmSDMA1_PUB_REG_TYPE3)/sizeof(mmSDMA1_PUB_REG_TYPE3[0]), 0, 0 },
+	{ "mmSDMA1_MMHUB_CNTL", REG_MMIO, 0x0013, 0, &mmSDMA1_MMHUB_CNTL[0], sizeof(mmSDMA1_MMHUB_CNTL)/sizeof(mmSDMA1_MMHUB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_GROUP_BOUNDARY", REG_MMIO, 0x0019, 0, &mmSDMA1_CONTEXT_GROUP_BOUNDARY[0], sizeof(mmSDMA1_CONTEXT_GROUP_BOUNDARY)/sizeof(mmSDMA1_CONTEXT_GROUP_BOUNDARY[0]), 0, 0 },
+	{ "mmSDMA1_POWER_CNTL", REG_MMIO, 0x001a, 0, &mmSDMA1_POWER_CNTL[0], sizeof(mmSDMA1_POWER_CNTL)/sizeof(mmSDMA1_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CLK_CTRL", REG_MMIO, 0x001b, 0, &mmSDMA1_CLK_CTRL[0], sizeof(mmSDMA1_CLK_CTRL)/sizeof(mmSDMA1_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA1_CNTL", REG_MMIO, 0x001c, 0, &mmSDMA1_CNTL[0], sizeof(mmSDMA1_CNTL)/sizeof(mmSDMA1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CHICKEN_BITS", REG_MMIO, 0x001d, 0, &mmSDMA1_CHICKEN_BITS[0], sizeof(mmSDMA1_CHICKEN_BITS)/sizeof(mmSDMA1_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA1_GB_ADDR_CONFIG", REG_MMIO, 0x001e, 0, &mmSDMA1_GB_ADDR_CONFIG[0], sizeof(mmSDMA1_GB_ADDR_CONFIG)/sizeof(mmSDMA1_GB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_GB_ADDR_CONFIG_READ", REG_MMIO, 0x001f, 0, &mmSDMA1_GB_ADDR_CONFIG_READ[0], sizeof(mmSDMA1_GB_ADDR_CONFIG_READ)/sizeof(mmSDMA1_GB_ADDR_CONFIG_READ[0]), 0, 0 },
+	{ "mmSDMA1_RB_RPTR_FETCH_HI", REG_MMIO, 0x0020, 0, &mmSDMA1_RB_RPTR_FETCH_HI[0], sizeof(mmSDMA1_RB_RPTR_FETCH_HI)/sizeof(mmSDMA1_RB_RPTR_FETCH_HI[0]), 0, 0 },
+	{ "mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x0021, 0, &mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RB_RPTR_FETCH", REG_MMIO, 0x0022, 0, &mmSDMA1_RB_RPTR_FETCH[0], sizeof(mmSDMA1_RB_RPTR_FETCH)/sizeof(mmSDMA1_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_IB_OFFSET_FETCH", REG_MMIO, 0x0023, 0, &mmSDMA1_IB_OFFSET_FETCH[0], sizeof(mmSDMA1_IB_OFFSET_FETCH)/sizeof(mmSDMA1_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_PROGRAM", REG_MMIO, 0x0024, 0, &mmSDMA1_PROGRAM[0], sizeof(mmSDMA1_PROGRAM)/sizeof(mmSDMA1_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA1_STATUS_REG", REG_MMIO, 0x0025, 0, &mmSDMA1_STATUS_REG[0], sizeof(mmSDMA1_STATUS_REG)/sizeof(mmSDMA1_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA1_STATUS1_REG", REG_MMIO, 0x0026, 0, &mmSDMA1_STATUS1_REG[0], sizeof(mmSDMA1_STATUS1_REG)/sizeof(mmSDMA1_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA1_RD_BURST_CNTL", REG_MMIO, 0x0027, 0, &mmSDMA1_RD_BURST_CNTL[0], sizeof(mmSDMA1_RD_BURST_CNTL)/sizeof(mmSDMA1_RD_BURST_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_HBM_PAGE_CONFIG", REG_MMIO, 0x0028, 0, &mmSDMA1_HBM_PAGE_CONFIG[0], sizeof(mmSDMA1_HBM_PAGE_CONFIG)/sizeof(mmSDMA1_HBM_PAGE_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_CHECKSUM", REG_MMIO, 0x0029, 0, &mmSDMA1_UCODE_CHECKSUM[0], sizeof(mmSDMA1_UCODE_CHECKSUM)/sizeof(mmSDMA1_UCODE_CHECKSUM[0]), 0, 0 },
+	{ "mmSDMA1_F32_CNTL", REG_MMIO, 0x002a, 0, &mmSDMA1_F32_CNTL[0], sizeof(mmSDMA1_F32_CNTL)/sizeof(mmSDMA1_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_FREEZE", REG_MMIO, 0x002b, 0, &mmSDMA1_FREEZE[0], sizeof(mmSDMA1_FREEZE)/sizeof(mmSDMA1_FREEZE[0]), 0, 0 },
+	{ "mmSDMA1_PHASE0_QUANTUM", REG_MMIO, 0x002c, 0, &mmSDMA1_PHASE0_QUANTUM[0], sizeof(mmSDMA1_PHASE0_QUANTUM)/sizeof(mmSDMA1_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_PHASE1_QUANTUM", REG_MMIO, 0x002d, 0, &mmSDMA1_PHASE1_QUANTUM[0], sizeof(mmSDMA1_PHASE1_QUANTUM)/sizeof(mmSDMA1_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_EDC_CONFIG", REG_MMIO, 0x0032, 0, &mmSDMA1_EDC_CONFIG[0], sizeof(mmSDMA1_EDC_CONFIG)/sizeof(mmSDMA1_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_BA_THRESHOLD", REG_MMIO, 0x0033, 0, &mmSDMA1_BA_THRESHOLD[0], sizeof(mmSDMA1_BA_THRESHOLD)/sizeof(mmSDMA1_BA_THRESHOLD[0]), 0, 0 },
+	{ "mmSDMA1_ID", REG_MMIO, 0x0034, 0, &mmSDMA1_ID[0], sizeof(mmSDMA1_ID)/sizeof(mmSDMA1_ID[0]), 0, 0 },
+	{ "mmSDMA1_VERSION", REG_MMIO, 0x0035, 0, &mmSDMA1_VERSION[0], sizeof(mmSDMA1_VERSION)/sizeof(mmSDMA1_VERSION[0]), 0, 0 },
+	{ "mmSDMA1_EDC_COUNTER", REG_MMIO, 0x0036, 0, &mmSDMA1_EDC_COUNTER[0], sizeof(mmSDMA1_EDC_COUNTER)/sizeof(mmSDMA1_EDC_COUNTER[0]), 0, 0 },
+	{ "mmSDMA1_EDC_COUNTER_CLEAR", REG_MMIO, 0x0037, 0, &mmSDMA1_EDC_COUNTER_CLEAR[0], sizeof(mmSDMA1_EDC_COUNTER_CLEAR)/sizeof(mmSDMA1_EDC_COUNTER_CLEAR[0]), 0, 0 },
+	{ "mmSDMA1_STATUS2_REG", REG_MMIO, 0x0038, 0, &mmSDMA1_STATUS2_REG[0], sizeof(mmSDMA1_STATUS2_REG)/sizeof(mmSDMA1_STATUS2_REG[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_CNTL", REG_MMIO, 0x0039, 0, &mmSDMA1_ATOMIC_CNTL[0], sizeof(mmSDMA1_ATOMIC_CNTL)/sizeof(mmSDMA1_ATOMIC_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_PREOP_LO", REG_MMIO, 0x003a, 0, &mmSDMA1_ATOMIC_PREOP_LO[0], sizeof(mmSDMA1_ATOMIC_PREOP_LO)/sizeof(mmSDMA1_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_PREOP_HI", REG_MMIO, 0x003b, 0, &mmSDMA1_ATOMIC_PREOP_HI[0], sizeof(mmSDMA1_ATOMIC_PREOP_HI)/sizeof(mmSDMA1_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_CNTL", REG_MMIO, 0x003c, 0, &mmSDMA1_UTCL1_CNTL[0], sizeof(mmSDMA1_UTCL1_CNTL)/sizeof(mmSDMA1_UTCL1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_WATERMK", REG_MMIO, 0x003d, 0, &mmSDMA1_UTCL1_WATERMK[0], sizeof(mmSDMA1_UTCL1_WATERMK)/sizeof(mmSDMA1_UTCL1_WATERMK[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_RD_STATUS", REG_MMIO, 0x003e, 0, &mmSDMA1_UTCL1_RD_STATUS[0], sizeof(mmSDMA1_UTCL1_RD_STATUS)/sizeof(mmSDMA1_UTCL1_RD_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_WR_STATUS", REG_MMIO, 0x003f, 0, &mmSDMA1_UTCL1_WR_STATUS[0], sizeof(mmSDMA1_UTCL1_WR_STATUS)/sizeof(mmSDMA1_UTCL1_WR_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_INV0", REG_MMIO, 0x0040, 0, &mmSDMA1_UTCL1_INV0[0], sizeof(mmSDMA1_UTCL1_INV0)/sizeof(mmSDMA1_UTCL1_INV0[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_INV1", REG_MMIO, 0x0041, 0, &mmSDMA1_UTCL1_INV1[0], sizeof(mmSDMA1_UTCL1_INV1)/sizeof(mmSDMA1_UTCL1_INV1[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_INV2", REG_MMIO, 0x0042, 0, &mmSDMA1_UTCL1_INV2[0], sizeof(mmSDMA1_UTCL1_INV2)/sizeof(mmSDMA1_UTCL1_INV2[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_RD_XNACK0", REG_MMIO, 0x0043, 0, &mmSDMA1_UTCL1_RD_XNACK0[0], sizeof(mmSDMA1_UTCL1_RD_XNACK0)/sizeof(mmSDMA1_UTCL1_RD_XNACK0[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_RD_XNACK1", REG_MMIO, 0x0044, 0, &mmSDMA1_UTCL1_RD_XNACK1[0], sizeof(mmSDMA1_UTCL1_RD_XNACK1)/sizeof(mmSDMA1_UTCL1_RD_XNACK1[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_WR_XNACK0", REG_MMIO, 0x0045, 0, &mmSDMA1_UTCL1_WR_XNACK0[0], sizeof(mmSDMA1_UTCL1_WR_XNACK0)/sizeof(mmSDMA1_UTCL1_WR_XNACK0[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_WR_XNACK1", REG_MMIO, 0x0046, 0, &mmSDMA1_UTCL1_WR_XNACK1[0], sizeof(mmSDMA1_UTCL1_WR_XNACK1)/sizeof(mmSDMA1_UTCL1_WR_XNACK1[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_TIMEOUT", REG_MMIO, 0x0047, 0, &mmSDMA1_UTCL1_TIMEOUT[0], sizeof(mmSDMA1_UTCL1_TIMEOUT)/sizeof(mmSDMA1_UTCL1_TIMEOUT[0]), 0, 0 },
+	{ "mmSDMA1_UTCL1_PAGE", REG_MMIO, 0x0048, 0, &mmSDMA1_UTCL1_PAGE[0], sizeof(mmSDMA1_UTCL1_PAGE)/sizeof(mmSDMA1_UTCL1_PAGE[0]), 0, 0 },
+	{ "mmSDMA1_POWER_CNTL_IDLE", REG_MMIO, 0x0049, 0, &mmSDMA1_POWER_CNTL_IDLE[0], sizeof(mmSDMA1_POWER_CNTL_IDLE)/sizeof(mmSDMA1_POWER_CNTL_IDLE[0]), 0, 0 },
+	{ "mmSDMA1_RELAX_ORDERING_LUT", REG_MMIO, 0x004a, 0, &mmSDMA1_RELAX_ORDERING_LUT[0], sizeof(mmSDMA1_RELAX_ORDERING_LUT)/sizeof(mmSDMA1_RELAX_ORDERING_LUT[0]), 0, 0 },
+	{ "mmSDMA1_CHICKEN_BITS_2", REG_MMIO, 0x004b, 0, &mmSDMA1_CHICKEN_BITS_2[0], sizeof(mmSDMA1_CHICKEN_BITS_2)/sizeof(mmSDMA1_CHICKEN_BITS_2[0]), 0, 0 },
+	{ "mmSDMA1_STATUS3_REG", REG_MMIO, 0x004c, 0, &mmSDMA1_STATUS3_REG[0], sizeof(mmSDMA1_STATUS3_REG)/sizeof(mmSDMA1_STATUS3_REG[0]), 0, 0 },
+	{ "mmSDMA1_PHYSICAL_ADDR_LO", REG_MMIO, 0x004d, 0, &mmSDMA1_PHYSICAL_ADDR_LO[0], sizeof(mmSDMA1_PHYSICAL_ADDR_LO)/sizeof(mmSDMA1_PHYSICAL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_PHYSICAL_ADDR_HI", REG_MMIO, 0x004e, 0, &mmSDMA1_PHYSICAL_ADDR_HI[0], sizeof(mmSDMA1_PHYSICAL_ADDR_HI)/sizeof(mmSDMA1_PHYSICAL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PHASE2_QUANTUM", REG_MMIO, 0x004f, 0, &mmSDMA1_PHASE2_QUANTUM[0], sizeof(mmSDMA1_PHASE2_QUANTUM)/sizeof(mmSDMA1_PHASE2_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_ERROR_LOG", REG_MMIO, 0x0050, 0, &mmSDMA1_ERROR_LOG[0], sizeof(mmSDMA1_ERROR_LOG)/sizeof(mmSDMA1_ERROR_LOG[0]), 0, 0 },
+	{ "mmSDMA1_PUB_DUMMY_REG0", REG_MMIO, 0x0051, 0, &mmSDMA1_PUB_DUMMY_REG0[0], sizeof(mmSDMA1_PUB_DUMMY_REG0)/sizeof(mmSDMA1_PUB_DUMMY_REG0[0]), 0, 0 },
+	{ "mmSDMA1_PUB_DUMMY_REG1", REG_MMIO, 0x0052, 0, &mmSDMA1_PUB_DUMMY_REG1[0], sizeof(mmSDMA1_PUB_DUMMY_REG1)/sizeof(mmSDMA1_PUB_DUMMY_REG1[0]), 0, 0 },
+	{ "mmSDMA1_PUB_DUMMY_REG2", REG_MMIO, 0x0053, 0, &mmSDMA1_PUB_DUMMY_REG2[0], sizeof(mmSDMA1_PUB_DUMMY_REG2)/sizeof(mmSDMA1_PUB_DUMMY_REG2[0]), 0, 0 },
+	{ "mmSDMA1_PUB_DUMMY_REG3", REG_MMIO, 0x0054, 0, &mmSDMA1_PUB_DUMMY_REG3[0], sizeof(mmSDMA1_PUB_DUMMY_REG3)/sizeof(mmSDMA1_PUB_DUMMY_REG3[0]), 0, 0 },
+	{ "mmSDMA1_F32_COUNTER", REG_MMIO, 0x0055, 0, &mmSDMA1_F32_COUNTER[0], sizeof(mmSDMA1_F32_COUNTER)/sizeof(mmSDMA1_F32_COUNTER[0]), 0, 0 },
+	{ "mmSDMA1_PERFMON_CNTL", REG_MMIO, 0x0057, 0, &mmSDMA1_PERFMON_CNTL[0], sizeof(mmSDMA1_PERFMON_CNTL)/sizeof(mmSDMA1_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER0_RESULT", REG_MMIO, 0x0058, 0, &mmSDMA1_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER0_RESULT)/sizeof(mmSDMA1_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER1_RESULT", REG_MMIO, 0x0059, 0, &mmSDMA1_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER1_RESULT)/sizeof(mmSDMA1_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE", REG_MMIO, 0x005a, 0, &mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE[0], sizeof(mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE)/sizeof(mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE[0]), 0, 0 },
+	{ "mmSDMA1_CRD_CNTL", REG_MMIO, 0x005b, 0, &mmSDMA1_CRD_CNTL[0], sizeof(mmSDMA1_CRD_CNTL)/sizeof(mmSDMA1_CRD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GPU_IOV_VIOLATION_LOG", REG_MMIO, 0x005d, 0, &mmSDMA1_GPU_IOV_VIOLATION_LOG[0], sizeof(mmSDMA1_GPU_IOV_VIOLATION_LOG)/sizeof(mmSDMA1_GPU_IOV_VIOLATION_LOG[0]), 0, 0 },
+	{ "mmSDMA1_ULV_CNTL", REG_MMIO, 0x005e, 0, &mmSDMA1_ULV_CNTL[0], sizeof(mmSDMA1_ULV_CNTL)/sizeof(mmSDMA1_ULV_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_EA_DBIT_ADDR_DATA", REG_MMIO, 0x0060, 0, &mmSDMA1_EA_DBIT_ADDR_DATA[0], sizeof(mmSDMA1_EA_DBIT_ADDR_DATA)/sizeof(mmSDMA1_EA_DBIT_ADDR_DATA[0]), 0, 0 },
+	{ "mmSDMA1_EA_DBIT_ADDR_INDEX", REG_MMIO, 0x0061, 0, &mmSDMA1_EA_DBIT_ADDR_INDEX[0], sizeof(mmSDMA1_EA_DBIT_ADDR_INDEX)/sizeof(mmSDMA1_EA_DBIT_ADDR_INDEX[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_CNTL", REG_MMIO, 0x0080, 0, &mmSDMA1_GFX_RB_CNTL[0], sizeof(mmSDMA1_GFX_RB_CNTL)/sizeof(mmSDMA1_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE", REG_MMIO, 0x0081, 0, &mmSDMA1_GFX_RB_BASE[0], sizeof(mmSDMA1_GFX_RB_BASE)/sizeof(mmSDMA1_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE_HI", REG_MMIO, 0x0082, 0, &mmSDMA1_GFX_RB_BASE_HI[0], sizeof(mmSDMA1_GFX_RB_BASE_HI)/sizeof(mmSDMA1_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR", REG_MMIO, 0x0083, 0, &mmSDMA1_GFX_RB_RPTR[0], sizeof(mmSDMA1_GFX_RB_RPTR)/sizeof(mmSDMA1_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_HI", REG_MMIO, 0x0084, 0, &mmSDMA1_GFX_RB_RPTR_HI[0], sizeof(mmSDMA1_GFX_RB_RPTR_HI)/sizeof(mmSDMA1_GFX_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR", REG_MMIO, 0x0085, 0, &mmSDMA1_GFX_RB_WPTR[0], sizeof(mmSDMA1_GFX_RB_WPTR)/sizeof(mmSDMA1_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_HI", REG_MMIO, 0x0086, 0, &mmSDMA1_GFX_RB_WPTR_HI[0], sizeof(mmSDMA1_GFX_RB_WPTR_HI)/sizeof(mmSDMA1_GFX_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0087, 0, &mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x0088, 0, &mmSDMA1_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x0089, 0, &mmSDMA1_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_CNTL", REG_MMIO, 0x008a, 0, &mmSDMA1_GFX_IB_CNTL[0], sizeof(mmSDMA1_GFX_IB_CNTL)/sizeof(mmSDMA1_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_RPTR", REG_MMIO, 0x008b, 0, &mmSDMA1_GFX_IB_RPTR[0], sizeof(mmSDMA1_GFX_IB_RPTR)/sizeof(mmSDMA1_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_OFFSET", REG_MMIO, 0x008c, 0, &mmSDMA1_GFX_IB_OFFSET[0], sizeof(mmSDMA1_GFX_IB_OFFSET)/sizeof(mmSDMA1_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_LO", REG_MMIO, 0x008d, 0, &mmSDMA1_GFX_IB_BASE_LO[0], sizeof(mmSDMA1_GFX_IB_BASE_LO)/sizeof(mmSDMA1_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_HI", REG_MMIO, 0x008e, 0, &mmSDMA1_GFX_IB_BASE_HI[0], sizeof(mmSDMA1_GFX_IB_BASE_HI)/sizeof(mmSDMA1_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_SIZE", REG_MMIO, 0x008f, 0, &mmSDMA1_GFX_IB_SIZE[0], sizeof(mmSDMA1_GFX_IB_SIZE)/sizeof(mmSDMA1_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_SKIP_CNTL", REG_MMIO, 0x0090, 0, &mmSDMA1_GFX_SKIP_CNTL[0], sizeof(mmSDMA1_GFX_SKIP_CNTL)/sizeof(mmSDMA1_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_STATUS", REG_MMIO, 0x0091, 0, &mmSDMA1_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA1_GFX_CONTEXT_STATUS)/sizeof(mmSDMA1_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DOORBELL", REG_MMIO, 0x0092, 0, &mmSDMA1_GFX_DOORBELL[0], sizeof(mmSDMA1_GFX_DOORBELL)/sizeof(mmSDMA1_GFX_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_CNTL", REG_MMIO, 0x0093, 0, &mmSDMA1_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA1_GFX_CONTEXT_CNTL)/sizeof(mmSDMA1_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_STATUS", REG_MMIO, 0x00a8, 0, &mmSDMA1_GFX_STATUS[0], sizeof(mmSDMA1_GFX_STATUS)/sizeof(mmSDMA1_GFX_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DOORBELL_LOG", REG_MMIO, 0x00a9, 0, &mmSDMA1_GFX_DOORBELL_LOG[0], sizeof(mmSDMA1_GFX_DOORBELL_LOG)/sizeof(mmSDMA1_GFX_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_GFX_WATERMARK", REG_MMIO, 0x00aa, 0, &mmSDMA1_GFX_WATERMARK[0], sizeof(mmSDMA1_GFX_WATERMARK)/sizeof(mmSDMA1_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DOORBELL_OFFSET", REG_MMIO, 0x00ab, 0, &mmSDMA1_GFX_DOORBELL_OFFSET[0], sizeof(mmSDMA1_GFX_DOORBELL_OFFSET)/sizeof(mmSDMA1_GFX_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CSA_ADDR_LO", REG_MMIO, 0x00ac, 0, &mmSDMA1_GFX_CSA_ADDR_LO[0], sizeof(mmSDMA1_GFX_CSA_ADDR_LO)/sizeof(mmSDMA1_GFX_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CSA_ADDR_HI", REG_MMIO, 0x00ad, 0, &mmSDMA1_GFX_CSA_ADDR_HI[0], sizeof(mmSDMA1_GFX_CSA_ADDR_HI)/sizeof(mmSDMA1_GFX_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_SUB_REMAIN", REG_MMIO, 0x00af, 0, &mmSDMA1_GFX_IB_SUB_REMAIN[0], sizeof(mmSDMA1_GFX_IB_SUB_REMAIN)/sizeof(mmSDMA1_GFX_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_GFX_PREEMPT", REG_MMIO, 0x00b0, 0, &mmSDMA1_GFX_PREEMPT[0], sizeof(mmSDMA1_GFX_PREEMPT)/sizeof(mmSDMA1_GFX_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DUMMY_REG", REG_MMIO, 0x00b1, 0, &mmSDMA1_GFX_DUMMY_REG[0], sizeof(mmSDMA1_GFX_DUMMY_REG)/sizeof(mmSDMA1_GFX_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x00b2, 0, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x00b3, 0, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_AQL_CNTL", REG_MMIO, 0x00b4, 0, &mmSDMA1_GFX_RB_AQL_CNTL[0], sizeof(mmSDMA1_GFX_RB_AQL_CNTL)/sizeof(mmSDMA1_GFX_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MINOR_PTR_UPDATE", REG_MMIO, 0x00b5, 0, &mmSDMA1_GFX_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_GFX_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_GFX_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA0", REG_MMIO, 0x00c0, 0, &mmSDMA1_GFX_MIDCMD_DATA0[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA0)/sizeof(mmSDMA1_GFX_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA1", REG_MMIO, 0x00c1, 0, &mmSDMA1_GFX_MIDCMD_DATA1[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA1)/sizeof(mmSDMA1_GFX_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA2", REG_MMIO, 0x00c2, 0, &mmSDMA1_GFX_MIDCMD_DATA2[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA2)/sizeof(mmSDMA1_GFX_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA3", REG_MMIO, 0x00c3, 0, &mmSDMA1_GFX_MIDCMD_DATA3[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA3)/sizeof(mmSDMA1_GFX_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA4", REG_MMIO, 0x00c4, 0, &mmSDMA1_GFX_MIDCMD_DATA4[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA4)/sizeof(mmSDMA1_GFX_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA5", REG_MMIO, 0x00c5, 0, &mmSDMA1_GFX_MIDCMD_DATA5[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA5)/sizeof(mmSDMA1_GFX_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA6", REG_MMIO, 0x00c6, 0, &mmSDMA1_GFX_MIDCMD_DATA6[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA6)/sizeof(mmSDMA1_GFX_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA7", REG_MMIO, 0x00c7, 0, &mmSDMA1_GFX_MIDCMD_DATA7[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA7)/sizeof(mmSDMA1_GFX_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA8", REG_MMIO, 0x00c8, 0, &mmSDMA1_GFX_MIDCMD_DATA8[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA8)/sizeof(mmSDMA1_GFX_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_CNTL", REG_MMIO, 0x00c9, 0, &mmSDMA1_GFX_MIDCMD_CNTL[0], sizeof(mmSDMA1_GFX_MIDCMD_CNTL)/sizeof(mmSDMA1_GFX_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_CNTL", REG_MMIO, 0x00e0, 0, &mmSDMA1_PAGE_RB_CNTL[0], sizeof(mmSDMA1_PAGE_RB_CNTL)/sizeof(mmSDMA1_PAGE_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_BASE", REG_MMIO, 0x00e1, 0, &mmSDMA1_PAGE_RB_BASE[0], sizeof(mmSDMA1_PAGE_RB_BASE)/sizeof(mmSDMA1_PAGE_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_BASE_HI", REG_MMIO, 0x00e2, 0, &mmSDMA1_PAGE_RB_BASE_HI[0], sizeof(mmSDMA1_PAGE_RB_BASE_HI)/sizeof(mmSDMA1_PAGE_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_RPTR", REG_MMIO, 0x00e3, 0, &mmSDMA1_PAGE_RB_RPTR[0], sizeof(mmSDMA1_PAGE_RB_RPTR)/sizeof(mmSDMA1_PAGE_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_RPTR_HI", REG_MMIO, 0x00e4, 0, &mmSDMA1_PAGE_RB_RPTR_HI[0], sizeof(mmSDMA1_PAGE_RB_RPTR_HI)/sizeof(mmSDMA1_PAGE_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_WPTR", REG_MMIO, 0x00e5, 0, &mmSDMA1_PAGE_RB_WPTR[0], sizeof(mmSDMA1_PAGE_RB_WPTR)/sizeof(mmSDMA1_PAGE_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_WPTR_HI", REG_MMIO, 0x00e6, 0, &mmSDMA1_PAGE_RB_WPTR_HI[0], sizeof(mmSDMA1_PAGE_RB_WPTR_HI)/sizeof(mmSDMA1_PAGE_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_WPTR_POLL_CNTL", REG_MMIO, 0x00e7, 0, &mmSDMA1_PAGE_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_RPTR_ADDR_HI", REG_MMIO, 0x00e8, 0, &mmSDMA1_PAGE_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_PAGE_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_PAGE_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_RPTR_ADDR_LO", REG_MMIO, 0x00e9, 0, &mmSDMA1_PAGE_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_PAGE_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_PAGE_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_CNTL", REG_MMIO, 0x00ea, 0, &mmSDMA1_PAGE_IB_CNTL[0], sizeof(mmSDMA1_PAGE_IB_CNTL)/sizeof(mmSDMA1_PAGE_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_RPTR", REG_MMIO, 0x00eb, 0, &mmSDMA1_PAGE_IB_RPTR[0], sizeof(mmSDMA1_PAGE_IB_RPTR)/sizeof(mmSDMA1_PAGE_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_OFFSET", REG_MMIO, 0x00ec, 0, &mmSDMA1_PAGE_IB_OFFSET[0], sizeof(mmSDMA1_PAGE_IB_OFFSET)/sizeof(mmSDMA1_PAGE_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_BASE_LO", REG_MMIO, 0x00ed, 0, &mmSDMA1_PAGE_IB_BASE_LO[0], sizeof(mmSDMA1_PAGE_IB_BASE_LO)/sizeof(mmSDMA1_PAGE_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_BASE_HI", REG_MMIO, 0x00ee, 0, &mmSDMA1_PAGE_IB_BASE_HI[0], sizeof(mmSDMA1_PAGE_IB_BASE_HI)/sizeof(mmSDMA1_PAGE_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_SIZE", REG_MMIO, 0x00ef, 0, &mmSDMA1_PAGE_IB_SIZE[0], sizeof(mmSDMA1_PAGE_IB_SIZE)/sizeof(mmSDMA1_PAGE_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_SKIP_CNTL", REG_MMIO, 0x00f0, 0, &mmSDMA1_PAGE_SKIP_CNTL[0], sizeof(mmSDMA1_PAGE_SKIP_CNTL)/sizeof(mmSDMA1_PAGE_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_CONTEXT_STATUS", REG_MMIO, 0x00f1, 0, &mmSDMA1_PAGE_CONTEXT_STATUS[0], sizeof(mmSDMA1_PAGE_CONTEXT_STATUS)/sizeof(mmSDMA1_PAGE_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_DOORBELL", REG_MMIO, 0x00f2, 0, &mmSDMA1_PAGE_DOORBELL[0], sizeof(mmSDMA1_PAGE_DOORBELL)/sizeof(mmSDMA1_PAGE_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_STATUS", REG_MMIO, 0x0108, 0, &mmSDMA1_PAGE_STATUS[0], sizeof(mmSDMA1_PAGE_STATUS)/sizeof(mmSDMA1_PAGE_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_DOORBELL_LOG", REG_MMIO, 0x0109, 0, &mmSDMA1_PAGE_DOORBELL_LOG[0], sizeof(mmSDMA1_PAGE_DOORBELL_LOG)/sizeof(mmSDMA1_PAGE_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_WATERMARK", REG_MMIO, 0x010a, 0, &mmSDMA1_PAGE_WATERMARK[0], sizeof(mmSDMA1_PAGE_WATERMARK)/sizeof(mmSDMA1_PAGE_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_DOORBELL_OFFSET", REG_MMIO, 0x010b, 0, &mmSDMA1_PAGE_DOORBELL_OFFSET[0], sizeof(mmSDMA1_PAGE_DOORBELL_OFFSET)/sizeof(mmSDMA1_PAGE_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_CSA_ADDR_LO", REG_MMIO, 0x010c, 0, &mmSDMA1_PAGE_CSA_ADDR_LO[0], sizeof(mmSDMA1_PAGE_CSA_ADDR_LO)/sizeof(mmSDMA1_PAGE_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_CSA_ADDR_HI", REG_MMIO, 0x010d, 0, &mmSDMA1_PAGE_CSA_ADDR_HI[0], sizeof(mmSDMA1_PAGE_CSA_ADDR_HI)/sizeof(mmSDMA1_PAGE_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_IB_SUB_REMAIN", REG_MMIO, 0x010f, 0, &mmSDMA1_PAGE_IB_SUB_REMAIN[0], sizeof(mmSDMA1_PAGE_IB_SUB_REMAIN)/sizeof(mmSDMA1_PAGE_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_PREEMPT", REG_MMIO, 0x0110, 0, &mmSDMA1_PAGE_PREEMPT[0], sizeof(mmSDMA1_PAGE_PREEMPT)/sizeof(mmSDMA1_PAGE_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_DUMMY_REG", REG_MMIO, 0x0111, 0, &mmSDMA1_PAGE_DUMMY_REG[0], sizeof(mmSDMA1_PAGE_DUMMY_REG)/sizeof(mmSDMA1_PAGE_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0112, 0, &mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0113, 0, &mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_RB_AQL_CNTL", REG_MMIO, 0x0114, 0, &mmSDMA1_PAGE_RB_AQL_CNTL[0], sizeof(mmSDMA1_PAGE_RB_AQL_CNTL)/sizeof(mmSDMA1_PAGE_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MINOR_PTR_UPDATE", REG_MMIO, 0x0115, 0, &mmSDMA1_PAGE_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_PAGE_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_PAGE_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA0", REG_MMIO, 0x0120, 0, &mmSDMA1_PAGE_MIDCMD_DATA0[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA0)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA1", REG_MMIO, 0x0121, 0, &mmSDMA1_PAGE_MIDCMD_DATA1[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA1)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA2", REG_MMIO, 0x0122, 0, &mmSDMA1_PAGE_MIDCMD_DATA2[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA2)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA3", REG_MMIO, 0x0123, 0, &mmSDMA1_PAGE_MIDCMD_DATA3[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA3)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA4", REG_MMIO, 0x0124, 0, &mmSDMA1_PAGE_MIDCMD_DATA4[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA4)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA5", REG_MMIO, 0x0125, 0, &mmSDMA1_PAGE_MIDCMD_DATA5[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA5)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA6", REG_MMIO, 0x0126, 0, &mmSDMA1_PAGE_MIDCMD_DATA6[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA6)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA7", REG_MMIO, 0x0127, 0, &mmSDMA1_PAGE_MIDCMD_DATA7[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA7)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_DATA8", REG_MMIO, 0x0128, 0, &mmSDMA1_PAGE_MIDCMD_DATA8[0], sizeof(mmSDMA1_PAGE_MIDCMD_DATA8)/sizeof(mmSDMA1_PAGE_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_PAGE_MIDCMD_CNTL", REG_MMIO, 0x0129, 0, &mmSDMA1_PAGE_MIDCMD_CNTL[0], sizeof(mmSDMA1_PAGE_MIDCMD_CNTL)/sizeof(mmSDMA1_PAGE_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_CNTL", REG_MMIO, 0x0140, 0, &mmSDMA1_RLC0_RB_CNTL[0], sizeof(mmSDMA1_RLC0_RB_CNTL)/sizeof(mmSDMA1_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE", REG_MMIO, 0x0141, 0, &mmSDMA1_RLC0_RB_BASE[0], sizeof(mmSDMA1_RLC0_RB_BASE)/sizeof(mmSDMA1_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE_HI", REG_MMIO, 0x0142, 0, &mmSDMA1_RLC0_RB_BASE_HI[0], sizeof(mmSDMA1_RLC0_RB_BASE_HI)/sizeof(mmSDMA1_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR", REG_MMIO, 0x0143, 0, &mmSDMA1_RLC0_RB_RPTR[0], sizeof(mmSDMA1_RLC0_RB_RPTR)/sizeof(mmSDMA1_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_HI", REG_MMIO, 0x0144, 0, &mmSDMA1_RLC0_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC0_RB_RPTR_HI)/sizeof(mmSDMA1_RLC0_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR", REG_MMIO, 0x0145, 0, &mmSDMA1_RLC0_RB_WPTR[0], sizeof(mmSDMA1_RLC0_RB_WPTR)/sizeof(mmSDMA1_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_HI", REG_MMIO, 0x0146, 0, &mmSDMA1_RLC0_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC0_RB_WPTR_HI)/sizeof(mmSDMA1_RLC0_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0147, 0, &mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x0148, 0, &mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x0149, 0, &mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_CNTL", REG_MMIO, 0x014a, 0, &mmSDMA1_RLC0_IB_CNTL[0], sizeof(mmSDMA1_RLC0_IB_CNTL)/sizeof(mmSDMA1_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_RPTR", REG_MMIO, 0x014b, 0, &mmSDMA1_RLC0_IB_RPTR[0], sizeof(mmSDMA1_RLC0_IB_RPTR)/sizeof(mmSDMA1_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_OFFSET", REG_MMIO, 0x014c, 0, &mmSDMA1_RLC0_IB_OFFSET[0], sizeof(mmSDMA1_RLC0_IB_OFFSET)/sizeof(mmSDMA1_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_LO", REG_MMIO, 0x014d, 0, &mmSDMA1_RLC0_IB_BASE_LO[0], sizeof(mmSDMA1_RLC0_IB_BASE_LO)/sizeof(mmSDMA1_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_HI", REG_MMIO, 0x014e, 0, &mmSDMA1_RLC0_IB_BASE_HI[0], sizeof(mmSDMA1_RLC0_IB_BASE_HI)/sizeof(mmSDMA1_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_SIZE", REG_MMIO, 0x014f, 0, &mmSDMA1_RLC0_IB_SIZE[0], sizeof(mmSDMA1_RLC0_IB_SIZE)/sizeof(mmSDMA1_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_SKIP_CNTL", REG_MMIO, 0x0150, 0, &mmSDMA1_RLC0_SKIP_CNTL[0], sizeof(mmSDMA1_RLC0_SKIP_CNTL)/sizeof(mmSDMA1_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CONTEXT_STATUS", REG_MMIO, 0x0151, 0, &mmSDMA1_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL", REG_MMIO, 0x0152, 0, &mmSDMA1_RLC0_DOORBELL[0], sizeof(mmSDMA1_RLC0_DOORBELL)/sizeof(mmSDMA1_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_STATUS", REG_MMIO, 0x0168, 0, &mmSDMA1_RLC0_STATUS[0], sizeof(mmSDMA1_RLC0_STATUS)/sizeof(mmSDMA1_RLC0_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL_LOG", REG_MMIO, 0x0169, 0, &mmSDMA1_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC0_DOORBELL_LOG)/sizeof(mmSDMA1_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_WATERMARK", REG_MMIO, 0x016a, 0, &mmSDMA1_RLC0_WATERMARK[0], sizeof(mmSDMA1_RLC0_WATERMARK)/sizeof(mmSDMA1_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL_OFFSET", REG_MMIO, 0x016b, 0, &mmSDMA1_RLC0_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC0_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC0_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CSA_ADDR_LO", REG_MMIO, 0x016c, 0, &mmSDMA1_RLC0_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC0_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC0_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CSA_ADDR_HI", REG_MMIO, 0x016d, 0, &mmSDMA1_RLC0_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC0_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC0_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_SUB_REMAIN", REG_MMIO, 0x016f, 0, &mmSDMA1_RLC0_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC0_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC0_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_PREEMPT", REG_MMIO, 0x0170, 0, &mmSDMA1_RLC0_PREEMPT[0], sizeof(mmSDMA1_RLC0_PREEMPT)/sizeof(mmSDMA1_RLC0_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DUMMY_REG", REG_MMIO, 0x0171, 0, &mmSDMA1_RLC0_DUMMY_REG[0], sizeof(mmSDMA1_RLC0_DUMMY_REG)/sizeof(mmSDMA1_RLC0_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0172, 0, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0173, 0, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_AQL_CNTL", REG_MMIO, 0x0174, 0, &mmSDMA1_RLC0_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC0_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC0_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MINOR_PTR_UPDATE", REG_MMIO, 0x0175, 0, &mmSDMA1_RLC0_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC0_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC0_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA0", REG_MMIO, 0x0180, 0, &mmSDMA1_RLC0_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA1", REG_MMIO, 0x0181, 0, &mmSDMA1_RLC0_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA2", REG_MMIO, 0x0182, 0, &mmSDMA1_RLC0_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA3", REG_MMIO, 0x0183, 0, &mmSDMA1_RLC0_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA4", REG_MMIO, 0x0184, 0, &mmSDMA1_RLC0_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA5", REG_MMIO, 0x0185, 0, &mmSDMA1_RLC0_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA6", REG_MMIO, 0x0186, 0, &mmSDMA1_RLC0_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA7", REG_MMIO, 0x0187, 0, &mmSDMA1_RLC0_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA8", REG_MMIO, 0x0188, 0, &mmSDMA1_RLC0_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_CNTL", REG_MMIO, 0x0189, 0, &mmSDMA1_RLC0_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC0_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC0_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_CNTL", REG_MMIO, 0x01a0, 0, &mmSDMA1_RLC1_RB_CNTL[0], sizeof(mmSDMA1_RLC1_RB_CNTL)/sizeof(mmSDMA1_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE", REG_MMIO, 0x01a1, 0, &mmSDMA1_RLC1_RB_BASE[0], sizeof(mmSDMA1_RLC1_RB_BASE)/sizeof(mmSDMA1_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE_HI", REG_MMIO, 0x01a2, 0, &mmSDMA1_RLC1_RB_BASE_HI[0], sizeof(mmSDMA1_RLC1_RB_BASE_HI)/sizeof(mmSDMA1_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR", REG_MMIO, 0x01a3, 0, &mmSDMA1_RLC1_RB_RPTR[0], sizeof(mmSDMA1_RLC1_RB_RPTR)/sizeof(mmSDMA1_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_HI", REG_MMIO, 0x01a4, 0, &mmSDMA1_RLC1_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC1_RB_RPTR_HI)/sizeof(mmSDMA1_RLC1_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR", REG_MMIO, 0x01a5, 0, &mmSDMA1_RLC1_RB_WPTR[0], sizeof(mmSDMA1_RLC1_RB_WPTR)/sizeof(mmSDMA1_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_HI", REG_MMIO, 0x01a6, 0, &mmSDMA1_RLC1_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC1_RB_WPTR_HI)/sizeof(mmSDMA1_RLC1_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x01a7, 0, &mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x01a8, 0, &mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x01a9, 0, &mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_CNTL", REG_MMIO, 0x01aa, 0, &mmSDMA1_RLC1_IB_CNTL[0], sizeof(mmSDMA1_RLC1_IB_CNTL)/sizeof(mmSDMA1_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_RPTR", REG_MMIO, 0x01ab, 0, &mmSDMA1_RLC1_IB_RPTR[0], sizeof(mmSDMA1_RLC1_IB_RPTR)/sizeof(mmSDMA1_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_OFFSET", REG_MMIO, 0x01ac, 0, &mmSDMA1_RLC1_IB_OFFSET[0], sizeof(mmSDMA1_RLC1_IB_OFFSET)/sizeof(mmSDMA1_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_LO", REG_MMIO, 0x01ad, 0, &mmSDMA1_RLC1_IB_BASE_LO[0], sizeof(mmSDMA1_RLC1_IB_BASE_LO)/sizeof(mmSDMA1_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_HI", REG_MMIO, 0x01ae, 0, &mmSDMA1_RLC1_IB_BASE_HI[0], sizeof(mmSDMA1_RLC1_IB_BASE_HI)/sizeof(mmSDMA1_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_SIZE", REG_MMIO, 0x01af, 0, &mmSDMA1_RLC1_IB_SIZE[0], sizeof(mmSDMA1_RLC1_IB_SIZE)/sizeof(mmSDMA1_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_SKIP_CNTL", REG_MMIO, 0x01b0, 0, &mmSDMA1_RLC1_SKIP_CNTL[0], sizeof(mmSDMA1_RLC1_SKIP_CNTL)/sizeof(mmSDMA1_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CONTEXT_STATUS", REG_MMIO, 0x01b1, 0, &mmSDMA1_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL", REG_MMIO, 0x01b2, 0, &mmSDMA1_RLC1_DOORBELL[0], sizeof(mmSDMA1_RLC1_DOORBELL)/sizeof(mmSDMA1_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_STATUS", REG_MMIO, 0x01c8, 0, &mmSDMA1_RLC1_STATUS[0], sizeof(mmSDMA1_RLC1_STATUS)/sizeof(mmSDMA1_RLC1_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL_LOG", REG_MMIO, 0x01c9, 0, &mmSDMA1_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC1_DOORBELL_LOG)/sizeof(mmSDMA1_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_WATERMARK", REG_MMIO, 0x01ca, 0, &mmSDMA1_RLC1_WATERMARK[0], sizeof(mmSDMA1_RLC1_WATERMARK)/sizeof(mmSDMA1_RLC1_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL_OFFSET", REG_MMIO, 0x01cb, 0, &mmSDMA1_RLC1_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC1_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC1_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CSA_ADDR_LO", REG_MMIO, 0x01cc, 0, &mmSDMA1_RLC1_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC1_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC1_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CSA_ADDR_HI", REG_MMIO, 0x01cd, 0, &mmSDMA1_RLC1_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC1_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC1_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_SUB_REMAIN", REG_MMIO, 0x01cf, 0, &mmSDMA1_RLC1_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC1_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC1_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_PREEMPT", REG_MMIO, 0x01d0, 0, &mmSDMA1_RLC1_PREEMPT[0], sizeof(mmSDMA1_RLC1_PREEMPT)/sizeof(mmSDMA1_RLC1_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DUMMY_REG", REG_MMIO, 0x01d1, 0, &mmSDMA1_RLC1_DUMMY_REG[0], sizeof(mmSDMA1_RLC1_DUMMY_REG)/sizeof(mmSDMA1_RLC1_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x01d2, 0, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x01d3, 0, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_AQL_CNTL", REG_MMIO, 0x01d4, 0, &mmSDMA1_RLC1_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC1_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC1_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MINOR_PTR_UPDATE", REG_MMIO, 0x01d5, 0, &mmSDMA1_RLC1_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC1_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC1_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA0", REG_MMIO, 0x01e0, 0, &mmSDMA1_RLC1_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA1", REG_MMIO, 0x01e1, 0, &mmSDMA1_RLC1_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA2", REG_MMIO, 0x01e2, 0, &mmSDMA1_RLC1_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA3", REG_MMIO, 0x01e3, 0, &mmSDMA1_RLC1_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA4", REG_MMIO, 0x01e4, 0, &mmSDMA1_RLC1_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA5", REG_MMIO, 0x01e5, 0, &mmSDMA1_RLC1_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA6", REG_MMIO, 0x01e6, 0, &mmSDMA1_RLC1_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA7", REG_MMIO, 0x01e7, 0, &mmSDMA1_RLC1_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA8", REG_MMIO, 0x01e8, 0, &mmSDMA1_RLC1_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_CNTL", REG_MMIO, 0x01e9, 0, &mmSDMA1_RLC1_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC1_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC1_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_CNTL", REG_MMIO, 0x0200, 0, &mmSDMA1_RLC2_RB_CNTL[0], sizeof(mmSDMA1_RLC2_RB_CNTL)/sizeof(mmSDMA1_RLC2_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_BASE", REG_MMIO, 0x0201, 0, &mmSDMA1_RLC2_RB_BASE[0], sizeof(mmSDMA1_RLC2_RB_BASE)/sizeof(mmSDMA1_RLC2_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_BASE_HI", REG_MMIO, 0x0202, 0, &mmSDMA1_RLC2_RB_BASE_HI[0], sizeof(mmSDMA1_RLC2_RB_BASE_HI)/sizeof(mmSDMA1_RLC2_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_RPTR", REG_MMIO, 0x0203, 0, &mmSDMA1_RLC2_RB_RPTR[0], sizeof(mmSDMA1_RLC2_RB_RPTR)/sizeof(mmSDMA1_RLC2_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_RPTR_HI", REG_MMIO, 0x0204, 0, &mmSDMA1_RLC2_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC2_RB_RPTR_HI)/sizeof(mmSDMA1_RLC2_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_WPTR", REG_MMIO, 0x0205, 0, &mmSDMA1_RLC2_RB_WPTR[0], sizeof(mmSDMA1_RLC2_RB_WPTR)/sizeof(mmSDMA1_RLC2_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_WPTR_HI", REG_MMIO, 0x0206, 0, &mmSDMA1_RLC2_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC2_RB_WPTR_HI)/sizeof(mmSDMA1_RLC2_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0207, 0, &mmSDMA1_RLC2_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_RPTR_ADDR_HI", REG_MMIO, 0x0208, 0, &mmSDMA1_RLC2_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC2_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC2_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_RPTR_ADDR_LO", REG_MMIO, 0x0209, 0, &mmSDMA1_RLC2_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC2_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC2_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_CNTL", REG_MMIO, 0x020a, 0, &mmSDMA1_RLC2_IB_CNTL[0], sizeof(mmSDMA1_RLC2_IB_CNTL)/sizeof(mmSDMA1_RLC2_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_RPTR", REG_MMIO, 0x020b, 0, &mmSDMA1_RLC2_IB_RPTR[0], sizeof(mmSDMA1_RLC2_IB_RPTR)/sizeof(mmSDMA1_RLC2_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_OFFSET", REG_MMIO, 0x020c, 0, &mmSDMA1_RLC2_IB_OFFSET[0], sizeof(mmSDMA1_RLC2_IB_OFFSET)/sizeof(mmSDMA1_RLC2_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_BASE_LO", REG_MMIO, 0x020d, 0, &mmSDMA1_RLC2_IB_BASE_LO[0], sizeof(mmSDMA1_RLC2_IB_BASE_LO)/sizeof(mmSDMA1_RLC2_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_BASE_HI", REG_MMIO, 0x020e, 0, &mmSDMA1_RLC2_IB_BASE_HI[0], sizeof(mmSDMA1_RLC2_IB_BASE_HI)/sizeof(mmSDMA1_RLC2_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_SIZE", REG_MMIO, 0x020f, 0, &mmSDMA1_RLC2_IB_SIZE[0], sizeof(mmSDMA1_RLC2_IB_SIZE)/sizeof(mmSDMA1_RLC2_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_SKIP_CNTL", REG_MMIO, 0x0210, 0, &mmSDMA1_RLC2_SKIP_CNTL[0], sizeof(mmSDMA1_RLC2_SKIP_CNTL)/sizeof(mmSDMA1_RLC2_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_CONTEXT_STATUS", REG_MMIO, 0x0211, 0, &mmSDMA1_RLC2_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC2_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC2_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_DOORBELL", REG_MMIO, 0x0212, 0, &mmSDMA1_RLC2_DOORBELL[0], sizeof(mmSDMA1_RLC2_DOORBELL)/sizeof(mmSDMA1_RLC2_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_STATUS", REG_MMIO, 0x0228, 0, &mmSDMA1_RLC2_STATUS[0], sizeof(mmSDMA1_RLC2_STATUS)/sizeof(mmSDMA1_RLC2_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_DOORBELL_LOG", REG_MMIO, 0x0229, 0, &mmSDMA1_RLC2_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC2_DOORBELL_LOG)/sizeof(mmSDMA1_RLC2_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_WATERMARK", REG_MMIO, 0x022a, 0, &mmSDMA1_RLC2_WATERMARK[0], sizeof(mmSDMA1_RLC2_WATERMARK)/sizeof(mmSDMA1_RLC2_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_DOORBELL_OFFSET", REG_MMIO, 0x022b, 0, &mmSDMA1_RLC2_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC2_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC2_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_CSA_ADDR_LO", REG_MMIO, 0x022c, 0, &mmSDMA1_RLC2_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC2_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC2_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_CSA_ADDR_HI", REG_MMIO, 0x022d, 0, &mmSDMA1_RLC2_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC2_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC2_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_IB_SUB_REMAIN", REG_MMIO, 0x022f, 0, &mmSDMA1_RLC2_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC2_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC2_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_PREEMPT", REG_MMIO, 0x0230, 0, &mmSDMA1_RLC2_PREEMPT[0], sizeof(mmSDMA1_RLC2_PREEMPT)/sizeof(mmSDMA1_RLC2_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_DUMMY_REG", REG_MMIO, 0x0231, 0, &mmSDMA1_RLC2_DUMMY_REG[0], sizeof(mmSDMA1_RLC2_DUMMY_REG)/sizeof(mmSDMA1_RLC2_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0232, 0, &mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0233, 0, &mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_RB_AQL_CNTL", REG_MMIO, 0x0234, 0, &mmSDMA1_RLC2_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC2_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC2_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MINOR_PTR_UPDATE", REG_MMIO, 0x0235, 0, &mmSDMA1_RLC2_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC2_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC2_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA0", REG_MMIO, 0x0240, 0, &mmSDMA1_RLC2_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA1", REG_MMIO, 0x0241, 0, &mmSDMA1_RLC2_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA2", REG_MMIO, 0x0242, 0, &mmSDMA1_RLC2_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA3", REG_MMIO, 0x0243, 0, &mmSDMA1_RLC2_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA4", REG_MMIO, 0x0244, 0, &mmSDMA1_RLC2_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA5", REG_MMIO, 0x0245, 0, &mmSDMA1_RLC2_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA6", REG_MMIO, 0x0246, 0, &mmSDMA1_RLC2_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA7", REG_MMIO, 0x0247, 0, &mmSDMA1_RLC2_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_DATA8", REG_MMIO, 0x0248, 0, &mmSDMA1_RLC2_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC2_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC2_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC2_MIDCMD_CNTL", REG_MMIO, 0x0249, 0, &mmSDMA1_RLC2_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC2_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC2_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_CNTL", REG_MMIO, 0x0260, 0, &mmSDMA1_RLC3_RB_CNTL[0], sizeof(mmSDMA1_RLC3_RB_CNTL)/sizeof(mmSDMA1_RLC3_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_BASE", REG_MMIO, 0x0261, 0, &mmSDMA1_RLC3_RB_BASE[0], sizeof(mmSDMA1_RLC3_RB_BASE)/sizeof(mmSDMA1_RLC3_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_BASE_HI", REG_MMIO, 0x0262, 0, &mmSDMA1_RLC3_RB_BASE_HI[0], sizeof(mmSDMA1_RLC3_RB_BASE_HI)/sizeof(mmSDMA1_RLC3_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_RPTR", REG_MMIO, 0x0263, 0, &mmSDMA1_RLC3_RB_RPTR[0], sizeof(mmSDMA1_RLC3_RB_RPTR)/sizeof(mmSDMA1_RLC3_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_RPTR_HI", REG_MMIO, 0x0264, 0, &mmSDMA1_RLC3_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC3_RB_RPTR_HI)/sizeof(mmSDMA1_RLC3_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_WPTR", REG_MMIO, 0x0265, 0, &mmSDMA1_RLC3_RB_WPTR[0], sizeof(mmSDMA1_RLC3_RB_WPTR)/sizeof(mmSDMA1_RLC3_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_WPTR_HI", REG_MMIO, 0x0266, 0, &mmSDMA1_RLC3_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC3_RB_WPTR_HI)/sizeof(mmSDMA1_RLC3_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0267, 0, &mmSDMA1_RLC3_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_RPTR_ADDR_HI", REG_MMIO, 0x0268, 0, &mmSDMA1_RLC3_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC3_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC3_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_RPTR_ADDR_LO", REG_MMIO, 0x0269, 0, &mmSDMA1_RLC3_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC3_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC3_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_CNTL", REG_MMIO, 0x026a, 0, &mmSDMA1_RLC3_IB_CNTL[0], sizeof(mmSDMA1_RLC3_IB_CNTL)/sizeof(mmSDMA1_RLC3_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_RPTR", REG_MMIO, 0x026b, 0, &mmSDMA1_RLC3_IB_RPTR[0], sizeof(mmSDMA1_RLC3_IB_RPTR)/sizeof(mmSDMA1_RLC3_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_OFFSET", REG_MMIO, 0x026c, 0, &mmSDMA1_RLC3_IB_OFFSET[0], sizeof(mmSDMA1_RLC3_IB_OFFSET)/sizeof(mmSDMA1_RLC3_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_BASE_LO", REG_MMIO, 0x026d, 0, &mmSDMA1_RLC3_IB_BASE_LO[0], sizeof(mmSDMA1_RLC3_IB_BASE_LO)/sizeof(mmSDMA1_RLC3_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_BASE_HI", REG_MMIO, 0x026e, 0, &mmSDMA1_RLC3_IB_BASE_HI[0], sizeof(mmSDMA1_RLC3_IB_BASE_HI)/sizeof(mmSDMA1_RLC3_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_SIZE", REG_MMIO, 0x026f, 0, &mmSDMA1_RLC3_IB_SIZE[0], sizeof(mmSDMA1_RLC3_IB_SIZE)/sizeof(mmSDMA1_RLC3_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_SKIP_CNTL", REG_MMIO, 0x0270, 0, &mmSDMA1_RLC3_SKIP_CNTL[0], sizeof(mmSDMA1_RLC3_SKIP_CNTL)/sizeof(mmSDMA1_RLC3_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_CONTEXT_STATUS", REG_MMIO, 0x0271, 0, &mmSDMA1_RLC3_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC3_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC3_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_DOORBELL", REG_MMIO, 0x0272, 0, &mmSDMA1_RLC3_DOORBELL[0], sizeof(mmSDMA1_RLC3_DOORBELL)/sizeof(mmSDMA1_RLC3_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_STATUS", REG_MMIO, 0x0288, 0, &mmSDMA1_RLC3_STATUS[0], sizeof(mmSDMA1_RLC3_STATUS)/sizeof(mmSDMA1_RLC3_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_DOORBELL_LOG", REG_MMIO, 0x0289, 0, &mmSDMA1_RLC3_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC3_DOORBELL_LOG)/sizeof(mmSDMA1_RLC3_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_WATERMARK", REG_MMIO, 0x028a, 0, &mmSDMA1_RLC3_WATERMARK[0], sizeof(mmSDMA1_RLC3_WATERMARK)/sizeof(mmSDMA1_RLC3_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_DOORBELL_OFFSET", REG_MMIO, 0x028b, 0, &mmSDMA1_RLC3_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC3_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC3_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_CSA_ADDR_LO", REG_MMIO, 0x028c, 0, &mmSDMA1_RLC3_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC3_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC3_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_CSA_ADDR_HI", REG_MMIO, 0x028d, 0, &mmSDMA1_RLC3_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC3_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC3_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_IB_SUB_REMAIN", REG_MMIO, 0x028f, 0, &mmSDMA1_RLC3_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC3_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC3_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_PREEMPT", REG_MMIO, 0x0290, 0, &mmSDMA1_RLC3_PREEMPT[0], sizeof(mmSDMA1_RLC3_PREEMPT)/sizeof(mmSDMA1_RLC3_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_DUMMY_REG", REG_MMIO, 0x0291, 0, &mmSDMA1_RLC3_DUMMY_REG[0], sizeof(mmSDMA1_RLC3_DUMMY_REG)/sizeof(mmSDMA1_RLC3_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0292, 0, &mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0293, 0, &mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_RB_AQL_CNTL", REG_MMIO, 0x0294, 0, &mmSDMA1_RLC3_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC3_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC3_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MINOR_PTR_UPDATE", REG_MMIO, 0x0295, 0, &mmSDMA1_RLC3_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC3_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC3_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA0", REG_MMIO, 0x02a0, 0, &mmSDMA1_RLC3_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA1", REG_MMIO, 0x02a1, 0, &mmSDMA1_RLC3_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA2", REG_MMIO, 0x02a2, 0, &mmSDMA1_RLC3_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA3", REG_MMIO, 0x02a3, 0, &mmSDMA1_RLC3_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA4", REG_MMIO, 0x02a4, 0, &mmSDMA1_RLC3_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA5", REG_MMIO, 0x02a5, 0, &mmSDMA1_RLC3_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA6", REG_MMIO, 0x02a6, 0, &mmSDMA1_RLC3_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA7", REG_MMIO, 0x02a7, 0, &mmSDMA1_RLC3_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_DATA8", REG_MMIO, 0x02a8, 0, &mmSDMA1_RLC3_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC3_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC3_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC3_MIDCMD_CNTL", REG_MMIO, 0x02a9, 0, &mmSDMA1_RLC3_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC3_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC3_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_CNTL", REG_MMIO, 0x02c0, 0, &mmSDMA1_RLC4_RB_CNTL[0], sizeof(mmSDMA1_RLC4_RB_CNTL)/sizeof(mmSDMA1_RLC4_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_BASE", REG_MMIO, 0x02c1, 0, &mmSDMA1_RLC4_RB_BASE[0], sizeof(mmSDMA1_RLC4_RB_BASE)/sizeof(mmSDMA1_RLC4_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_BASE_HI", REG_MMIO, 0x02c2, 0, &mmSDMA1_RLC4_RB_BASE_HI[0], sizeof(mmSDMA1_RLC4_RB_BASE_HI)/sizeof(mmSDMA1_RLC4_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_RPTR", REG_MMIO, 0x02c3, 0, &mmSDMA1_RLC4_RB_RPTR[0], sizeof(mmSDMA1_RLC4_RB_RPTR)/sizeof(mmSDMA1_RLC4_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_RPTR_HI", REG_MMIO, 0x02c4, 0, &mmSDMA1_RLC4_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC4_RB_RPTR_HI)/sizeof(mmSDMA1_RLC4_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_WPTR", REG_MMIO, 0x02c5, 0, &mmSDMA1_RLC4_RB_WPTR[0], sizeof(mmSDMA1_RLC4_RB_WPTR)/sizeof(mmSDMA1_RLC4_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_WPTR_HI", REG_MMIO, 0x02c6, 0, &mmSDMA1_RLC4_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC4_RB_WPTR_HI)/sizeof(mmSDMA1_RLC4_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_WPTR_POLL_CNTL", REG_MMIO, 0x02c7, 0, &mmSDMA1_RLC4_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_RPTR_ADDR_HI", REG_MMIO, 0x02c8, 0, &mmSDMA1_RLC4_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC4_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC4_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_RPTR_ADDR_LO", REG_MMIO, 0x02c9, 0, &mmSDMA1_RLC4_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC4_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC4_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_CNTL", REG_MMIO, 0x02ca, 0, &mmSDMA1_RLC4_IB_CNTL[0], sizeof(mmSDMA1_RLC4_IB_CNTL)/sizeof(mmSDMA1_RLC4_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_RPTR", REG_MMIO, 0x02cb, 0, &mmSDMA1_RLC4_IB_RPTR[0], sizeof(mmSDMA1_RLC4_IB_RPTR)/sizeof(mmSDMA1_RLC4_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_OFFSET", REG_MMIO, 0x02cc, 0, &mmSDMA1_RLC4_IB_OFFSET[0], sizeof(mmSDMA1_RLC4_IB_OFFSET)/sizeof(mmSDMA1_RLC4_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_BASE_LO", REG_MMIO, 0x02cd, 0, &mmSDMA1_RLC4_IB_BASE_LO[0], sizeof(mmSDMA1_RLC4_IB_BASE_LO)/sizeof(mmSDMA1_RLC4_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_BASE_HI", REG_MMIO, 0x02ce, 0, &mmSDMA1_RLC4_IB_BASE_HI[0], sizeof(mmSDMA1_RLC4_IB_BASE_HI)/sizeof(mmSDMA1_RLC4_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_SIZE", REG_MMIO, 0x02cf, 0, &mmSDMA1_RLC4_IB_SIZE[0], sizeof(mmSDMA1_RLC4_IB_SIZE)/sizeof(mmSDMA1_RLC4_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_SKIP_CNTL", REG_MMIO, 0x02d0, 0, &mmSDMA1_RLC4_SKIP_CNTL[0], sizeof(mmSDMA1_RLC4_SKIP_CNTL)/sizeof(mmSDMA1_RLC4_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_CONTEXT_STATUS", REG_MMIO, 0x02d1, 0, &mmSDMA1_RLC4_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC4_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC4_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_DOORBELL", REG_MMIO, 0x02d2, 0, &mmSDMA1_RLC4_DOORBELL[0], sizeof(mmSDMA1_RLC4_DOORBELL)/sizeof(mmSDMA1_RLC4_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_STATUS", REG_MMIO, 0x02e8, 0, &mmSDMA1_RLC4_STATUS[0], sizeof(mmSDMA1_RLC4_STATUS)/sizeof(mmSDMA1_RLC4_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_DOORBELL_LOG", REG_MMIO, 0x02e9, 0, &mmSDMA1_RLC4_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC4_DOORBELL_LOG)/sizeof(mmSDMA1_RLC4_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_WATERMARK", REG_MMIO, 0x02ea, 0, &mmSDMA1_RLC4_WATERMARK[0], sizeof(mmSDMA1_RLC4_WATERMARK)/sizeof(mmSDMA1_RLC4_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_DOORBELL_OFFSET", REG_MMIO, 0x02eb, 0, &mmSDMA1_RLC4_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC4_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC4_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_CSA_ADDR_LO", REG_MMIO, 0x02ec, 0, &mmSDMA1_RLC4_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC4_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC4_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_CSA_ADDR_HI", REG_MMIO, 0x02ed, 0, &mmSDMA1_RLC4_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC4_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC4_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_IB_SUB_REMAIN", REG_MMIO, 0x02ef, 0, &mmSDMA1_RLC4_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC4_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC4_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_PREEMPT", REG_MMIO, 0x02f0, 0, &mmSDMA1_RLC4_PREEMPT[0], sizeof(mmSDMA1_RLC4_PREEMPT)/sizeof(mmSDMA1_RLC4_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_DUMMY_REG", REG_MMIO, 0x02f1, 0, &mmSDMA1_RLC4_DUMMY_REG[0], sizeof(mmSDMA1_RLC4_DUMMY_REG)/sizeof(mmSDMA1_RLC4_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x02f2, 0, &mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x02f3, 0, &mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_RB_AQL_CNTL", REG_MMIO, 0x02f4, 0, &mmSDMA1_RLC4_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC4_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC4_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MINOR_PTR_UPDATE", REG_MMIO, 0x02f5, 0, &mmSDMA1_RLC4_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC4_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC4_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA0", REG_MMIO, 0x0300, 0, &mmSDMA1_RLC4_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA1", REG_MMIO, 0x0301, 0, &mmSDMA1_RLC4_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA2", REG_MMIO, 0x0302, 0, &mmSDMA1_RLC4_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA3", REG_MMIO, 0x0303, 0, &mmSDMA1_RLC4_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA4", REG_MMIO, 0x0304, 0, &mmSDMA1_RLC4_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA5", REG_MMIO, 0x0305, 0, &mmSDMA1_RLC4_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA6", REG_MMIO, 0x0306, 0, &mmSDMA1_RLC4_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA7", REG_MMIO, 0x0307, 0, &mmSDMA1_RLC4_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_DATA8", REG_MMIO, 0x0308, 0, &mmSDMA1_RLC4_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC4_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC4_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC4_MIDCMD_CNTL", REG_MMIO, 0x0309, 0, &mmSDMA1_RLC4_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC4_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC4_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_CNTL", REG_MMIO, 0x0320, 0, &mmSDMA1_RLC5_RB_CNTL[0], sizeof(mmSDMA1_RLC5_RB_CNTL)/sizeof(mmSDMA1_RLC5_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_BASE", REG_MMIO, 0x0321, 0, &mmSDMA1_RLC5_RB_BASE[0], sizeof(mmSDMA1_RLC5_RB_BASE)/sizeof(mmSDMA1_RLC5_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_BASE_HI", REG_MMIO, 0x0322, 0, &mmSDMA1_RLC5_RB_BASE_HI[0], sizeof(mmSDMA1_RLC5_RB_BASE_HI)/sizeof(mmSDMA1_RLC5_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_RPTR", REG_MMIO, 0x0323, 0, &mmSDMA1_RLC5_RB_RPTR[0], sizeof(mmSDMA1_RLC5_RB_RPTR)/sizeof(mmSDMA1_RLC5_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_RPTR_HI", REG_MMIO, 0x0324, 0, &mmSDMA1_RLC5_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC5_RB_RPTR_HI)/sizeof(mmSDMA1_RLC5_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_WPTR", REG_MMIO, 0x0325, 0, &mmSDMA1_RLC5_RB_WPTR[0], sizeof(mmSDMA1_RLC5_RB_WPTR)/sizeof(mmSDMA1_RLC5_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_WPTR_HI", REG_MMIO, 0x0326, 0, &mmSDMA1_RLC5_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC5_RB_WPTR_HI)/sizeof(mmSDMA1_RLC5_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0327, 0, &mmSDMA1_RLC5_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_RPTR_ADDR_HI", REG_MMIO, 0x0328, 0, &mmSDMA1_RLC5_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC5_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC5_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_RPTR_ADDR_LO", REG_MMIO, 0x0329, 0, &mmSDMA1_RLC5_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC5_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC5_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_CNTL", REG_MMIO, 0x032a, 0, &mmSDMA1_RLC5_IB_CNTL[0], sizeof(mmSDMA1_RLC5_IB_CNTL)/sizeof(mmSDMA1_RLC5_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_RPTR", REG_MMIO, 0x032b, 0, &mmSDMA1_RLC5_IB_RPTR[0], sizeof(mmSDMA1_RLC5_IB_RPTR)/sizeof(mmSDMA1_RLC5_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_OFFSET", REG_MMIO, 0x032c, 0, &mmSDMA1_RLC5_IB_OFFSET[0], sizeof(mmSDMA1_RLC5_IB_OFFSET)/sizeof(mmSDMA1_RLC5_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_BASE_LO", REG_MMIO, 0x032d, 0, &mmSDMA1_RLC5_IB_BASE_LO[0], sizeof(mmSDMA1_RLC5_IB_BASE_LO)/sizeof(mmSDMA1_RLC5_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_BASE_HI", REG_MMIO, 0x032e, 0, &mmSDMA1_RLC5_IB_BASE_HI[0], sizeof(mmSDMA1_RLC5_IB_BASE_HI)/sizeof(mmSDMA1_RLC5_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_SIZE", REG_MMIO, 0x032f, 0, &mmSDMA1_RLC5_IB_SIZE[0], sizeof(mmSDMA1_RLC5_IB_SIZE)/sizeof(mmSDMA1_RLC5_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_SKIP_CNTL", REG_MMIO, 0x0330, 0, &mmSDMA1_RLC5_SKIP_CNTL[0], sizeof(mmSDMA1_RLC5_SKIP_CNTL)/sizeof(mmSDMA1_RLC5_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_CONTEXT_STATUS", REG_MMIO, 0x0331, 0, &mmSDMA1_RLC5_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC5_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC5_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_DOORBELL", REG_MMIO, 0x0332, 0, &mmSDMA1_RLC5_DOORBELL[0], sizeof(mmSDMA1_RLC5_DOORBELL)/sizeof(mmSDMA1_RLC5_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_STATUS", REG_MMIO, 0x0348, 0, &mmSDMA1_RLC5_STATUS[0], sizeof(mmSDMA1_RLC5_STATUS)/sizeof(mmSDMA1_RLC5_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_DOORBELL_LOG", REG_MMIO, 0x0349, 0, &mmSDMA1_RLC5_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC5_DOORBELL_LOG)/sizeof(mmSDMA1_RLC5_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_WATERMARK", REG_MMIO, 0x034a, 0, &mmSDMA1_RLC5_WATERMARK[0], sizeof(mmSDMA1_RLC5_WATERMARK)/sizeof(mmSDMA1_RLC5_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_DOORBELL_OFFSET", REG_MMIO, 0x034b, 0, &mmSDMA1_RLC5_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC5_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC5_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_CSA_ADDR_LO", REG_MMIO, 0x034c, 0, &mmSDMA1_RLC5_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC5_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC5_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_CSA_ADDR_HI", REG_MMIO, 0x034d, 0, &mmSDMA1_RLC5_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC5_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC5_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_IB_SUB_REMAIN", REG_MMIO, 0x034f, 0, &mmSDMA1_RLC5_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC5_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC5_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_PREEMPT", REG_MMIO, 0x0350, 0, &mmSDMA1_RLC5_PREEMPT[0], sizeof(mmSDMA1_RLC5_PREEMPT)/sizeof(mmSDMA1_RLC5_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_DUMMY_REG", REG_MMIO, 0x0351, 0, &mmSDMA1_RLC5_DUMMY_REG[0], sizeof(mmSDMA1_RLC5_DUMMY_REG)/sizeof(mmSDMA1_RLC5_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0352, 0, &mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0353, 0, &mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_RB_AQL_CNTL", REG_MMIO, 0x0354, 0, &mmSDMA1_RLC5_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC5_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC5_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MINOR_PTR_UPDATE", REG_MMIO, 0x0355, 0, &mmSDMA1_RLC5_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC5_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC5_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA0", REG_MMIO, 0x0360, 0, &mmSDMA1_RLC5_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA1", REG_MMIO, 0x0361, 0, &mmSDMA1_RLC5_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA2", REG_MMIO, 0x0362, 0, &mmSDMA1_RLC5_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA3", REG_MMIO, 0x0363, 0, &mmSDMA1_RLC5_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA4", REG_MMIO, 0x0364, 0, &mmSDMA1_RLC5_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA5", REG_MMIO, 0x0365, 0, &mmSDMA1_RLC5_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA6", REG_MMIO, 0x0366, 0, &mmSDMA1_RLC5_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA7", REG_MMIO, 0x0367, 0, &mmSDMA1_RLC5_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_DATA8", REG_MMIO, 0x0368, 0, &mmSDMA1_RLC5_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC5_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC5_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC5_MIDCMD_CNTL", REG_MMIO, 0x0369, 0, &mmSDMA1_RLC5_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC5_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC5_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_CNTL", REG_MMIO, 0x0380, 0, &mmSDMA1_RLC6_RB_CNTL[0], sizeof(mmSDMA1_RLC6_RB_CNTL)/sizeof(mmSDMA1_RLC6_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_BASE", REG_MMIO, 0x0381, 0, &mmSDMA1_RLC6_RB_BASE[0], sizeof(mmSDMA1_RLC6_RB_BASE)/sizeof(mmSDMA1_RLC6_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_BASE_HI", REG_MMIO, 0x0382, 0, &mmSDMA1_RLC6_RB_BASE_HI[0], sizeof(mmSDMA1_RLC6_RB_BASE_HI)/sizeof(mmSDMA1_RLC6_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_RPTR", REG_MMIO, 0x0383, 0, &mmSDMA1_RLC6_RB_RPTR[0], sizeof(mmSDMA1_RLC6_RB_RPTR)/sizeof(mmSDMA1_RLC6_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_RPTR_HI", REG_MMIO, 0x0384, 0, &mmSDMA1_RLC6_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC6_RB_RPTR_HI)/sizeof(mmSDMA1_RLC6_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_WPTR", REG_MMIO, 0x0385, 0, &mmSDMA1_RLC6_RB_WPTR[0], sizeof(mmSDMA1_RLC6_RB_WPTR)/sizeof(mmSDMA1_RLC6_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_WPTR_HI", REG_MMIO, 0x0386, 0, &mmSDMA1_RLC6_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC6_RB_WPTR_HI)/sizeof(mmSDMA1_RLC6_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_WPTR_POLL_CNTL", REG_MMIO, 0x0387, 0, &mmSDMA1_RLC6_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_RPTR_ADDR_HI", REG_MMIO, 0x0388, 0, &mmSDMA1_RLC6_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC6_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC6_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_RPTR_ADDR_LO", REG_MMIO, 0x0389, 0, &mmSDMA1_RLC6_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC6_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC6_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_CNTL", REG_MMIO, 0x038a, 0, &mmSDMA1_RLC6_IB_CNTL[0], sizeof(mmSDMA1_RLC6_IB_CNTL)/sizeof(mmSDMA1_RLC6_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_RPTR", REG_MMIO, 0x038b, 0, &mmSDMA1_RLC6_IB_RPTR[0], sizeof(mmSDMA1_RLC6_IB_RPTR)/sizeof(mmSDMA1_RLC6_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_OFFSET", REG_MMIO, 0x038c, 0, &mmSDMA1_RLC6_IB_OFFSET[0], sizeof(mmSDMA1_RLC6_IB_OFFSET)/sizeof(mmSDMA1_RLC6_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_BASE_LO", REG_MMIO, 0x038d, 0, &mmSDMA1_RLC6_IB_BASE_LO[0], sizeof(mmSDMA1_RLC6_IB_BASE_LO)/sizeof(mmSDMA1_RLC6_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_BASE_HI", REG_MMIO, 0x038e, 0, &mmSDMA1_RLC6_IB_BASE_HI[0], sizeof(mmSDMA1_RLC6_IB_BASE_HI)/sizeof(mmSDMA1_RLC6_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_SIZE", REG_MMIO, 0x038f, 0, &mmSDMA1_RLC6_IB_SIZE[0], sizeof(mmSDMA1_RLC6_IB_SIZE)/sizeof(mmSDMA1_RLC6_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_SKIP_CNTL", REG_MMIO, 0x0390, 0, &mmSDMA1_RLC6_SKIP_CNTL[0], sizeof(mmSDMA1_RLC6_SKIP_CNTL)/sizeof(mmSDMA1_RLC6_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_CONTEXT_STATUS", REG_MMIO, 0x0391, 0, &mmSDMA1_RLC6_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC6_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC6_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_DOORBELL", REG_MMIO, 0x0392, 0, &mmSDMA1_RLC6_DOORBELL[0], sizeof(mmSDMA1_RLC6_DOORBELL)/sizeof(mmSDMA1_RLC6_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_STATUS", REG_MMIO, 0x03a8, 0, &mmSDMA1_RLC6_STATUS[0], sizeof(mmSDMA1_RLC6_STATUS)/sizeof(mmSDMA1_RLC6_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_DOORBELL_LOG", REG_MMIO, 0x03a9, 0, &mmSDMA1_RLC6_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC6_DOORBELL_LOG)/sizeof(mmSDMA1_RLC6_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_WATERMARK", REG_MMIO, 0x03aa, 0, &mmSDMA1_RLC6_WATERMARK[0], sizeof(mmSDMA1_RLC6_WATERMARK)/sizeof(mmSDMA1_RLC6_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_DOORBELL_OFFSET", REG_MMIO, 0x03ab, 0, &mmSDMA1_RLC6_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC6_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC6_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_CSA_ADDR_LO", REG_MMIO, 0x03ac, 0, &mmSDMA1_RLC6_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC6_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC6_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_CSA_ADDR_HI", REG_MMIO, 0x03ad, 0, &mmSDMA1_RLC6_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC6_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC6_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_IB_SUB_REMAIN", REG_MMIO, 0x03af, 0, &mmSDMA1_RLC6_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC6_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC6_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_PREEMPT", REG_MMIO, 0x03b0, 0, &mmSDMA1_RLC6_PREEMPT[0], sizeof(mmSDMA1_RLC6_PREEMPT)/sizeof(mmSDMA1_RLC6_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_DUMMY_REG", REG_MMIO, 0x03b1, 0, &mmSDMA1_RLC6_DUMMY_REG[0], sizeof(mmSDMA1_RLC6_DUMMY_REG)/sizeof(mmSDMA1_RLC6_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x03b2, 0, &mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x03b3, 0, &mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_RB_AQL_CNTL", REG_MMIO, 0x03b4, 0, &mmSDMA1_RLC6_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC6_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC6_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MINOR_PTR_UPDATE", REG_MMIO, 0x03b5, 0, &mmSDMA1_RLC6_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC6_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC6_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA0", REG_MMIO, 0x03c0, 0, &mmSDMA1_RLC6_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA1", REG_MMIO, 0x03c1, 0, &mmSDMA1_RLC6_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA2", REG_MMIO, 0x03c2, 0, &mmSDMA1_RLC6_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA3", REG_MMIO, 0x03c3, 0, &mmSDMA1_RLC6_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA4", REG_MMIO, 0x03c4, 0, &mmSDMA1_RLC6_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA5", REG_MMIO, 0x03c5, 0, &mmSDMA1_RLC6_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA6", REG_MMIO, 0x03c6, 0, &mmSDMA1_RLC6_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA7", REG_MMIO, 0x03c7, 0, &mmSDMA1_RLC6_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_DATA8", REG_MMIO, 0x03c8, 0, &mmSDMA1_RLC6_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC6_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC6_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC6_MIDCMD_CNTL", REG_MMIO, 0x03c9, 0, &mmSDMA1_RLC6_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC6_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC6_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_CNTL", REG_MMIO, 0x03e0, 0, &mmSDMA1_RLC7_RB_CNTL[0], sizeof(mmSDMA1_RLC7_RB_CNTL)/sizeof(mmSDMA1_RLC7_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_BASE", REG_MMIO, 0x03e1, 0, &mmSDMA1_RLC7_RB_BASE[0], sizeof(mmSDMA1_RLC7_RB_BASE)/sizeof(mmSDMA1_RLC7_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_BASE_HI", REG_MMIO, 0x03e2, 0, &mmSDMA1_RLC7_RB_BASE_HI[0], sizeof(mmSDMA1_RLC7_RB_BASE_HI)/sizeof(mmSDMA1_RLC7_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_RPTR", REG_MMIO, 0x03e3, 0, &mmSDMA1_RLC7_RB_RPTR[0], sizeof(mmSDMA1_RLC7_RB_RPTR)/sizeof(mmSDMA1_RLC7_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_RPTR_HI", REG_MMIO, 0x03e4, 0, &mmSDMA1_RLC7_RB_RPTR_HI[0], sizeof(mmSDMA1_RLC7_RB_RPTR_HI)/sizeof(mmSDMA1_RLC7_RB_RPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_WPTR", REG_MMIO, 0x03e5, 0, &mmSDMA1_RLC7_RB_WPTR[0], sizeof(mmSDMA1_RLC7_RB_WPTR)/sizeof(mmSDMA1_RLC7_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_WPTR_HI", REG_MMIO, 0x03e6, 0, &mmSDMA1_RLC7_RB_WPTR_HI[0], sizeof(mmSDMA1_RLC7_RB_WPTR_HI)/sizeof(mmSDMA1_RLC7_RB_WPTR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_WPTR_POLL_CNTL", REG_MMIO, 0x03e7, 0, &mmSDMA1_RLC7_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_RPTR_ADDR_HI", REG_MMIO, 0x03e8, 0, &mmSDMA1_RLC7_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC7_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC7_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_RPTR_ADDR_LO", REG_MMIO, 0x03e9, 0, &mmSDMA1_RLC7_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC7_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC7_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_CNTL", REG_MMIO, 0x03ea, 0, &mmSDMA1_RLC7_IB_CNTL[0], sizeof(mmSDMA1_RLC7_IB_CNTL)/sizeof(mmSDMA1_RLC7_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_RPTR", REG_MMIO, 0x03eb, 0, &mmSDMA1_RLC7_IB_RPTR[0], sizeof(mmSDMA1_RLC7_IB_RPTR)/sizeof(mmSDMA1_RLC7_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_OFFSET", REG_MMIO, 0x03ec, 0, &mmSDMA1_RLC7_IB_OFFSET[0], sizeof(mmSDMA1_RLC7_IB_OFFSET)/sizeof(mmSDMA1_RLC7_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_BASE_LO", REG_MMIO, 0x03ed, 0, &mmSDMA1_RLC7_IB_BASE_LO[0], sizeof(mmSDMA1_RLC7_IB_BASE_LO)/sizeof(mmSDMA1_RLC7_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_BASE_HI", REG_MMIO, 0x03ee, 0, &mmSDMA1_RLC7_IB_BASE_HI[0], sizeof(mmSDMA1_RLC7_IB_BASE_HI)/sizeof(mmSDMA1_RLC7_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_SIZE", REG_MMIO, 0x03ef, 0, &mmSDMA1_RLC7_IB_SIZE[0], sizeof(mmSDMA1_RLC7_IB_SIZE)/sizeof(mmSDMA1_RLC7_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_SKIP_CNTL", REG_MMIO, 0x03f0, 0, &mmSDMA1_RLC7_SKIP_CNTL[0], sizeof(mmSDMA1_RLC7_SKIP_CNTL)/sizeof(mmSDMA1_RLC7_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_CONTEXT_STATUS", REG_MMIO, 0x03f1, 0, &mmSDMA1_RLC7_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC7_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC7_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_DOORBELL", REG_MMIO, 0x03f2, 0, &mmSDMA1_RLC7_DOORBELL[0], sizeof(mmSDMA1_RLC7_DOORBELL)/sizeof(mmSDMA1_RLC7_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_STATUS", REG_MMIO, 0x0408, 0, &mmSDMA1_RLC7_STATUS[0], sizeof(mmSDMA1_RLC7_STATUS)/sizeof(mmSDMA1_RLC7_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_DOORBELL_LOG", REG_MMIO, 0x0409, 0, &mmSDMA1_RLC7_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC7_DOORBELL_LOG)/sizeof(mmSDMA1_RLC7_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_WATERMARK", REG_MMIO, 0x040a, 0, &mmSDMA1_RLC7_WATERMARK[0], sizeof(mmSDMA1_RLC7_WATERMARK)/sizeof(mmSDMA1_RLC7_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_DOORBELL_OFFSET", REG_MMIO, 0x040b, 0, &mmSDMA1_RLC7_DOORBELL_OFFSET[0], sizeof(mmSDMA1_RLC7_DOORBELL_OFFSET)/sizeof(mmSDMA1_RLC7_DOORBELL_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_CSA_ADDR_LO", REG_MMIO, 0x040c, 0, &mmSDMA1_RLC7_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC7_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC7_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_CSA_ADDR_HI", REG_MMIO, 0x040d, 0, &mmSDMA1_RLC7_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC7_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC7_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_IB_SUB_REMAIN", REG_MMIO, 0x040f, 0, &mmSDMA1_RLC7_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC7_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC7_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_PREEMPT", REG_MMIO, 0x0410, 0, &mmSDMA1_RLC7_PREEMPT[0], sizeof(mmSDMA1_RLC7_PREEMPT)/sizeof(mmSDMA1_RLC7_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_DUMMY_REG", REG_MMIO, 0x0411, 0, &mmSDMA1_RLC7_DUMMY_REG[0], sizeof(mmSDMA1_RLC7_DUMMY_REG)/sizeof(mmSDMA1_RLC7_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x0412, 0, &mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x0413, 0, &mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_RB_AQL_CNTL", REG_MMIO, 0x0414, 0, &mmSDMA1_RLC7_RB_AQL_CNTL[0], sizeof(mmSDMA1_RLC7_RB_AQL_CNTL)/sizeof(mmSDMA1_RLC7_RB_AQL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MINOR_PTR_UPDATE", REG_MMIO, 0x0415, 0, &mmSDMA1_RLC7_MINOR_PTR_UPDATE[0], sizeof(mmSDMA1_RLC7_MINOR_PTR_UPDATE)/sizeof(mmSDMA1_RLC7_MINOR_PTR_UPDATE[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA0", REG_MMIO, 0x0420, 0, &mmSDMA1_RLC7_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA1", REG_MMIO, 0x0421, 0, &mmSDMA1_RLC7_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA2", REG_MMIO, 0x0422, 0, &mmSDMA1_RLC7_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA3", REG_MMIO, 0x0423, 0, &mmSDMA1_RLC7_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA4", REG_MMIO, 0x0424, 0, &mmSDMA1_RLC7_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA5", REG_MMIO, 0x0425, 0, &mmSDMA1_RLC7_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA6", REG_MMIO, 0x0426, 0, &mmSDMA1_RLC7_MIDCMD_DATA6[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA6)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA6[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA7", REG_MMIO, 0x0427, 0, &mmSDMA1_RLC7_MIDCMD_DATA7[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA7)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA7[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_DATA8", REG_MMIO, 0x0428, 0, &mmSDMA1_RLC7_MIDCMD_DATA8[0], sizeof(mmSDMA1_RLC7_MIDCMD_DATA8)/sizeof(mmSDMA1_RLC7_MIDCMD_DATA8[0]), 0, 0 },
+	{ "mmSDMA1_RLC7_MIDCMD_CNTL", REG_MMIO, 0x0429, 0, &mmSDMA1_RLC7_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC7_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC7_MIDCMD_CNTL[0]), 0, 0 },
diff --git a/src/umr.h b/src/umr.h
index 0540af6..3ea543e 100644
--- a/src/umr.h
+++ b/src/umr.h
@@ -583,6 +583,8 @@ struct umr_ip_block *umr_create_oss40(struct umr_ip_offsets_soc15 *soc15_offsets
 struct umr_ip_block *umr_create_oss401(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
 struct umr_ip_block *umr_create_sdma040(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
 struct umr_ip_block *umr_create_sdma140(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
+struct umr_ip_block *umr_create_sdma042(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
+struct umr_ip_block *umr_create_sdma142(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
 struct umr_ip_block *umr_create_sdma041(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
 struct umr_ip_block *umr_create_mmhub10(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);
 struct umr_ip_block *umr_create_mmhub91(struct umr_ip_offsets_soc15 *soc15_offsets, struct umr_options *options);