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path: root/src/gallium/drivers/radeon
AgeCommit message (Expand)AuthorFilesLines
2012-11-02r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fsVincent Lejeune1-0/+3
2012-10-26radeon/llvm: Add intrinsic for reading SI FRONT_FACE VGPR in the pixel shader.Michel Dänzer2-0/+6
2012-10-19radeon/llvm: Sort tgsi opcode action initializationTom Stellard1-59/+50
2012-10-19radeon/llvm: Fix lowering TGSI_OPCODE_SSGTom Stellard1-1/+1
2012-10-11radeon/llvm: Fix build with LLVM 3.2Tom Stellard1-3/+10
2012-10-10radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinfVincent Lejeune3-6/+2
2012-10-10radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floorVincent Lejeune5-5/+5
2012-10-10radeon/llvm: use llvm fabs intrinsicVincent Lejeune3-6/+4
2012-10-10radeon/llvm: use llvm intrinsic for flog2Vincent Lejeune4-5/+4
2012-10-10radeon/llvm: add support for cos/sin intrinsicVincent Lejeune3-12/+15
2012-10-10radeon/llvm: add a pattern for fsqrtVincent Lejeune1-0/+3
2012-10-02radeon/llvm: Disable SI flow control again for now.Michel Dänzer1-1/+2
2012-10-01radeon/llvm: Only initialize the AMDGPU targetTom Stellard1-7/+1
2012-10-01radeon: Fix build with LLVM 3.1Tom Stellard1-0/+1
2012-10-01radeon: Support LLVM 3.2Tom Stellard3-3/+11
2012-09-28r600g: add some members to radeon_llvm_contextVincent Lejeune1-0/+6
2012-09-27radeon/llvm: improve select_cc lowering to generate CND* more oftenVincent Lejeune3-41/+88
2012-09-24radeon/llvm: Fix instruction encoding for r600 family GPUsTom Stellard3-15/+14
2012-09-22radeon/llvm: support for interpolation intrinsicsVincent Lejeune10-2/+318
2012-09-21radeon/llvm: Handle loads from the constants address space.Tom Stellard2-0/+10
2012-09-21radeon/llvm: Add support for v4f32 stores on R600Tom Stellard3-9/+27
2012-09-21radeon/llvm: Add support for i8 reads on R600Tom Stellard3-0/+25
2012-09-21radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard1-0/+3
2012-09-21radeon/llvm: Add optimization for FP_ROUNDTom Stellard2-0/+27
2012-09-21radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard4-7/+26
2012-09-19radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo5-139/+238
2012-09-19radeon/llvm: Only support 512 constant registers on R600Tom Stellard1-1/+1
2012-09-18radeon/llvm: Add a fdiv pattern.Vincent Lejeune1-3/+10
2012-09-18radeon/llvm: reserve also corresponding 128bits regVincent Lejeune1-0/+1
2012-09-17radeon/llvm: Inital flow control support for SITom Stellard7-2/+168
2012-09-17radeon/llvm: Fix unused variable warningTom Stellard1-1/+0
2012-09-17radeon/llvm: Move kernel arg lowering into R600TargetLowering classTom Stellard6-470/+35
2012-09-17radeon/llvm: Match integer add/sub for SI.Michel Dänzer1-2/+8
2012-09-17radeon/llvm: Complete integer comparison patterns for SI.Michel Dänzer1-4/+12
2012-09-17radeon/llvm: Match AMDGPUfract on SI.Michel Dänzer1-1/+3
2012-09-17radeon/llvm: Match int_AMDGPU_floor for SI.Michel Dänzer1-1/+3
2012-09-17radeon/llvm: Match vector logical operations on SI.Michel Dänzer1-3/+9
2012-09-14radeon/llvm: Support frint on SIChristian König1-1/+3
2012-09-13radeon/llvm: Fix lowering of vbuildTom Stellard7-93/+19
2012-09-13radeon/llvm: Support fmul on SITom Stellard1-1/+4
2012-09-11radeon/llvm: Fix operand order of V_CNDMASK in custom inserterTom Stellard1-1/+1
2012-09-11radeon/llvm: Assert if we try to encode an unknown registerTom Stellard1-1/+1
2012-09-11radeon/llvm: Add register encoding for VCCTom Stellard1-0/+1
2012-09-11radeon/llvm: Ignore special registers when calculating reg countTom Stellard1-0/+2
2012-09-11radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2-0/+22
2012-09-11radeon/llvm: Coding style fixesTom Stellard4-31/+31
2012-09-11radeonsi: Move interpolation mode check into the compilerTom Stellard1-1/+12
2012-09-11radeon/llvm: Add SHADER_TYPE instructionTom Stellard8-1/+32
2012-09-07radeon/llvm: Match fexp2 for SI.Michel Dänzer1-1/+3
2012-09-06radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer4-0/+23
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