From c527b5b6c03ea0d47a66b7523b716ea81c47cb2c Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 11 Dec 2012 18:43:05 +0100 Subject: R600: enable S_*N2_* instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They seem to work fine. Reviewed-by: Tom Stellard Tested-by: Michel Dänzer Signed-off-by: Christian König --- lib/Target/AMDGPU/SIInstructions.td | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index ea8de91406..008652f55e 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -971,10 +971,10 @@ def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; -////def S_ANDN2_B32 : SOP2_ANDN2 <0x00000014, "S_ANDN2_B32", []>; -////def S_ANDN2_B64 : SOP2_ANDN2 <0x00000015, "S_ANDN2_B64", []>; -////def S_ORN2_B32 : SOP2_ORN2 <0x00000016, "S_ORN2_B32", []>; -////def S_ORN2_B64 : SOP2_ORN2 <0x00000017, "S_ORN2_B64", []>; +def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; +def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; +def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; +def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; -- cgit v1.2.3