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path: root/lib/Target/CellSPU
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2012-04-29Update the documentation of CellSPU, in case it gets removed in 3.1.Kalle Raiskila1-0/+14
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd1-0/+5
2012-04-20Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper2-35/+35
2012-04-20Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper1-40/+36
2012-04-17Remove unused CCIfSubtarget.Jay Foad1-4/+0
2012-04-04Always compute all the bits in ComputeMaskedBits.Rafael Espindola2-2/+0
2012-03-27Prune some includesCraig Topper1-1/+0
2012-03-27Remove unnecessary llvm:: qualificationsCraig Topper1-1/+1
2012-03-22Remove some unnecessary forward declarations.Craig Topper1-2/+0
2012-03-17Reorder includes in Target backends to following coding standards. Remove som...Craig Topper6-8/+5
2012-03-11Remove global map. This code isn't even hot.Benjamin Kramer1-38/+28
2012-03-11Use uint16_t to store registers and opcode in static tables in the target spe...Craig Topper1-2/+2
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce siz...Craig Topper2-3/+3
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a dire...Evan Cheng2-4/+5
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre...Daniel Dunbar2-5/+4
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2-4/+5
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu24-35/+35
2012-02-10unnecessary includeAndrew Trick1-1/+0
2012-02-07Convert assert(0) to llvm_unreachableCraig Topper1-4/+2
2012-02-05Convert assert(0) to llvm_unreachableCraig Topper1-0/+1
2012-02-04TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2-8/+5
2012-02-03Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2-11/+32
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie3-28/+3
2012-01-07Remove VectorExtras. This unused helper was written for a type of API that is...Benjamin Kramer1-1/+0
2011-12-20Fix up the CMake build for the new files added in r146960, they'reChandler Carruth1-0/+1
2011-12-20Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_...David Blaikie4-2/+21
2011-12-13Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth1-0/+10
2011-12-12LLVMBuild: Introduce a common section which currently has a list of theDaniel Dunbar1-0/+3
2011-12-12LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar3-3/+0
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky3-3/+5
2011-11-29build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar3-23/+0
2011-11-16Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng3-11/+12
2011-11-15Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad1-1/+0
2011-11-12build: Attempt to rectify inconsistencies between CMake and LLVMBuild version...Daniel Dunbar2-2/+2
2011-11-11LLVMBuild: Add explicit information on whether targets define an assembly pri...Daniel Dunbar1-0/+1
2011-11-10llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar1-1/+0
2011-11-10llvm-build: Add an explicit component type to represent targets.Daniel Dunbar1-1/+1
2011-11-08Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2-6/+9
2011-11-04build/cmake: Use tblgen macro directly instead of llvm_tablegen, which justDaniel Dunbar1-7/+7
2011-11-03build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar3-0/+78
2011-10-16Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem1-3/+5
2011-10-15The CELL backend cannot select patterns for vector trunc-store and shl on v2...Nadav Rotem1-0/+9
2011-10-13Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila1-2/+4
2011-10-11Fix a iterator out of bounds error, that triggers rarely.Kalle Raiskila1-0/+2
2011-10-06Build system infrastructure for multiple tblgens.Peter Collingbourne1-7/+7
2011-10-04Set operation actions to legal types only.Nadav Rotem1-8/+9
2011-10-04Operations should be custom lowered only if their type is legal.Nadav Rotem1-6/+8
2011-09-06Add codegen support for vector select (in the IR this means a selectDuncan Sands2-2/+3
2011-09-02Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila1-2/+2
2011-08-30Fix typos in SPUMCTargetDesc.hJames Molloy1-2/+2