~vlj/llvm - AMDGPU backend development for LLVM

Age	Commit message (Expand)	Author	Files	Lines
2012-10-19	R600: Use native operands for KILLGT instruction	tstellar	1	-29/+18
2012-10-19	R600: Use native operands for CUBE, DOT4 instructions	tstellar	1	-42/+16
2012-10-19	R600: Organize pseudo instruction in R600Instructions.td	tstellar	1	-27/+10
2012-10-19	R600: Lower PRED_X to a native instruction prior to codegen	tstellar	1	-18/+34
2012-10-19	R600: Use native operands for R600_OP3 instructions	tstellar	1	-34/+64
2012-10-19	R600: Use native operands for R600_2OP instructions	tstellar	1	-110/+54
2012-10-19	R600: Use native operands for MOV_IMM_* instructions	tstellar	1	-18/+14
2012-10-19	R600: Use native operands for the MOV Instruction	tstellar	1	-14/+1
2012-10-19	R600: Use native operands for R600_1OP instructions	tstellar	1	-95/+178
2012-10-19	AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsic	tstellar	1	-7/+0
2012-10-19	R600: Fix DIV_Common pattern use	tstellar	1	-1/+3
2012-10-19	R600: Set FlagOperandIdx for RECIP_IEEE	tstellar	1	-5/+5
2012-10-19	R600: Cayman now uses vector version of EXP_IEEE, LOG_IEEE and RECIPSQRT_CLAMPED	tstellar	1	-9/+19
2012-10-19	R600: Lower fpow(A, B) to fexp(mul(B, flog(A))) at DAG level	tstellar	1	-2/+0
2012-10-15	R600: use floor intrinsic instead of llvm.AMDIL.floor	tstellar	1	-1/+1
2012-10-15	R600: use llvm intrinsic for flog2	tstellar	1	-1/+1
2012-10-15	R600: add support for cos/sin intrinsic	tstellar	1	-6/+11
2012-10-15	R600: add a pattern for fsqrt	tstellar	1	-0/+3
2012-10-10	R600: Fix typo in SETGE_UINT pattern	tstellar	1	-1/+1
2012-10-09	R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)	tstellar	1	-0/+7
2012-10-09	R600: Add a comment explaining why we use TRUNC before FLT_TO_*INT	tstellar	1	-0/+10
2012-10-03	R600: Add support for v4i32 global stores	tstellar	1	-0/+6
2012-10-02	R600: improve select_cc lowering to generate CND* more often	tstellar	1	-6/+32
2012-09-24	R600: support for interpolation intrinsics	tstellar	1	-0/+54
2012-09-24	R600: Handle loads from the constants address space.	tstellar	1	-0/+9
2012-09-24	R600: Add support for v4f32 stores on R600	tstellar	1	-7/+23
2012-09-24	R600: Add support for i8 reads on R600	tstellar	1	-0/+16
2012-09-21	Some cleanups after merge of Mesa branch	tstellar	1	-1/+1
2012-09-21	R600: Emit ISA for ALU instructions in the R600 code emitter	Michal Sciubidlo	1	-61/+119
2012-09-21	R600: Add a fdiv pattern.	Tom Stellard	1	-3/+10
2012-09-21	R600: Fix lowering of vbuild	Tom Stellard	1	-10/+10
2012-09-21	AMDGPU: Don't print the default predicate state	Tom Stellard	1	-1/+1
2012-09-21	AMDGPU: Use new OperandWithDefaultOps for DOT* instructions	Tom Stellard	1	-10/+5
2012-09-21	AMDGPU: Updates for new tablegen property inferences	Tom Stellard	1	-4/+17
2012-09-21	AMDGPU: Add core backend files for R600/SI codegen	Tom Stellard	1	-0/+1266
2012-07-16	Revert "AMDGPU: Add core backend files for R600/SI codegen v6"	Tom Stellard	1	-1322/+0
2012-07-16	AMDGPU: Add core backend files for R600/SI codegen v6	Tom Stellard	1	-0/+1322