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2013-01-18Revert "temp fix"constbuf2Vincent Lejeune1-2/+2
This reverts commit a3e1937719aad1d542680da3a0cfdc8367558182.
2013-01-16avoid and/or/xor blend loweringVincent Lejeune1-0/+1
2013-01-16some improvementsVincent Lejeune1-7/+31
2013-01-14temp fixVincent Lejeune1-2/+2
2013-01-13some fixes ?Vincent Lejeune1-1/+2
2013-01-13radeon/llvm: Expand various vector operationVincent Lejeune2-0/+32
2013-01-11radeon/llvm: add a llvm.R600.store.swizzle intrinsicsVincent Lejeune3-2/+34
This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs
2013-01-11radeon/llvm: simplify stream outputs intrinsicVincent Lejeune5-47/+13
2013-01-08radeon/llvm: switch instructions matching fmul and int_AMDGPU_mulVincent Lejeune3-7/+8
2013-01-08R600: Fold CONST_ADDRESS when possibleVincent Lejeune2-2/+73
2013-01-08R600: use pointers for constantsVincent Lejeune9-84/+296
2013-01-08R600: Add a CONST_ADDRESS node to model constant buf readVincent Lejeune3-1/+12
2013-01-08R600: Factorise VTX_WORD0 and VTX_WORD1 in tblgen defVincent Lejeune1-45/+65
2013-01-05R600: rework handling of the constantsVadim Girlin10-99/+195
Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver.
2013-01-04AMDGPU: Rename backend to R600Tom Stellard109-39/+51
2013-01-02DAGCombiner: Avoid generating illegal vector INT_TO_FP nodeststellar4-7/+42
DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two mistakes: 1. It was checking the legality of scalar INT_TO_FP nodes and then generating vector nodes. 2. It was passing the result value type to TargetLoweringInfo::getOperationAction() when it should have been passing the value type of the first operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02Merge LLVM 3.2 branchTom Stellard190-1855/+6365
2012-12-21R600: Coding style - remove empty spaces from the beginning of functionsTom Stellard3-35/+0
No functionality change.
2012-12-21R600: Fix MAX_UINT definitionVadim Girlin1-1/+1
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-21R600: Add SHADOWCUBE to TEX_SHADOW patternVadim Girlin1-1/+1
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-21R600: Expand vec4 INT <-> FP conversionststellar2-0/+56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14R600: Remove unecessary VREG alignment.Christian König1-6/+6
Unlike SGPRs VGPRs doesn't need to be aligned. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-12-14R600: control flow optimizationChristian König1-0/+49
Branch if we have enough instructions so that it makes sense. Also remove branches if they don't make sense. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-12-14R600: New control flow for SI v2Christian König13-384/+1498
This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-14R600: enable S_*N2_* instructionsChristian König1-4/+4
They seem to work fine. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-12-14R600: BB operand support for SIChristian König4-4/+27
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-12-14R600: remove nonsense setPrefLoopAlignmentChristian König1-1/+0
The Align parameter is a power of two, so 16 results in 64K alignment. Additional to that even 16 byte alignment doesn't make any sense, so just remove it. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-12-11R600: Add an intrinsic to handle stream outputs.Vincent Lejeune6-0/+102
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11R600: Add a field for Export node (compMask) and factorise code handling ↵Vincent Lejeune2-42/+58
store intrinsic Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11R600: Split Word0 and Word1 in Export instructionVincent Lejeune3-49/+60
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.Michel Dänzer1-4/+4
VALU instructions can only read from one SGPR, and that's the condition code mask in this case. Fixes a number of radeonsi piglit regressions from Vincent's max/min changes (which means the matching to AMDGPUfmax/min doesn't work for some reason). Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-11AMDGPU: Match fdiv for SI.Michel Dänzer1-0/+5
Fixes hundreds of radeonsi piglit regressions from commit 62c8e1ec4a93b28c55c1c7accb6cbd64952e59c2 ('AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP pattern'). Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-11R600: Add support for i8 and i16 function argumentsTom Stellard5-15/+92
2012-12-11R600: Improve assembly output for VTX instructionsTom Stellard4-7/+13
2012-12-11AMDGPU: Promote floating-point load/store to integer load/storeTom Stellard4-60/+37
This will reduce the number of tablegen patterns we need.
2012-12-11LegalizeDAG: Allow promotion of scalar loadsTom Stellard1-3/+2
2012-12-11LegalizeDAG: Allow type promotion for scalar storesTom Stellard1-3/+4
2012-12-11R600: Convert global store address to dword offset during iselTom Stellard7-14/+46
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-12-05R600: Fix use iterator in custom select of ISD::ConstantTom Stellard1-2/+3
The use list may change during the execution of the loop, so we need to manually keep track of the next item in the list.
2012-12-05AMDGPU: add a pattern for min/maxTom Stellard6-8/+79
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-05AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP patternVincent Lejeune3-4/+4
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-05AMDGPU: Match AMDGPU.cube intrinsic for SI.Michel Dänzer1-0/+21
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-05AMDGPU: Doxygen fixesTom Stellard72-517/+572
- Add \file to every file - Use \brief, \returns, \param, etc. where necessary - Remove duplicate function / class names from doxygen comments
2012-12-05AMDGPU: Various coding style fixesTom Stellard46-518/+452
- Fix more coding style errors with braces on their own line Found using: grep -rn '^[ ]*{$' - Remove underscore from start of macro defs - Remove all tabs - Remove "end of" comments that don't refer to namespaces. - Fix an issue with parens being on the wrong line. - Fix warnings from building with clang
2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard9-6/+153
v2: - Fold the immediates using the SelectionDAG Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Remove or document commented out codeTom Stellard4-92/+13
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Fix 4-space indentationTom Stellard3-73/+73
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Remove unused macros v2Tom Stellard6-100/+19
v2: - Fix alignment of case statements Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Coding style - put braces on same line as function headersTom Stellard27-458/+229
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Simplify SI control flow loweringChristian König1-41/+38
By using the S_*_SAVEEXEC_b64 instructions. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
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