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2012-11-29AMDGPU: Fix S_*_SAVEEXEC_B64 definesChristian König1-2/+8
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-11-29R600: rename if/break operator to improve readabilityVincent Lejeune4-61/+29
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: do not use magic number for resourceIdVincent Lejeune4-53/+60
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: add fsqrt pattern for r600/r700Vincent Lejeune1-0/+3
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: Valid pixel mode and EOP were inverted in exportVincent Lejeune1-2/+2
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29SI: Use IMAGE_SAMPLE_L for the SI.sample.lod intrinsic.Michel Dänzer1-2/+2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Fix name of SI control flow lowering source file.Michel Dänzer1-1/+1
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.Michel Dänzer1-2/+2
Two SGPRs are used for VCC, so it's not possible to use these and VCC together. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Fix string concatenation in AMDGPUInstPrinter::printRel().Michel Dänzer1-1/+1
Pointed out by compiler warning: /home/daenzer/src/llvm-git/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:96:16: warning: adding 'int64_t' (aka 'long') to a string does not append to the string [-Wstring-plus-int] O << " + " + Op.getImm(); ~~~~~~^~~~~~~~~~~~~ /home/daenzer/src/llvm-git/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:96:16: note: use array indexing to silence this warning O << " + " + Op.getImm(); ^ & [ ] 1 warning generated. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16R600: replaces fragment input with negative index with undef valuesVincent Lejeune1-3/+9
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-16R600: Fix operand index table for OP3 instructionsTom Stellard1-1/+1
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-16AMDGPU: Print integer and floating point values for literalsTom Stellard3-1/+13
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-16R600: Add helper function for setting instruction modifiersTom Stellard3-9/+16
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-13AMDGPU: Fix builds with -DNDEBUGtstellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13R600: Fix sampler->resource_id mappingtstellar1-2/+2
Patch by: Vadim Girlin Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: s/flow control/control flow/g .tstellar4-15/+15
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: fix SGPR liveness v4tstellar4-0/+191
SGPRs are not affected by control flow. v2: don't use liveness analyse any more, handle partial dominated end notes. v3: fix old pass name in CMakeLists.txt v4: remove unnecessary successor handling and kill handling Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Add intrinsic for sampling with explicit LOD.tstellar2-1/+9
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Add intrinsic for sampling with bias.tstellar2-1/+9
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Update flow control comments to match current code.tstellar1-4/+5
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Merge master branchtstellar599-7650/+20056
Build with clang checkouts: SVN: r167547 Git Mirror: b578aee665aad5ed1a46a26217c730fdfbfc8c2e git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Only allow SGPR for the first operand of VOP3 instructions.tstellar2-4/+4
This is technically too strict: While a VOP3 instruction can only use one SGPR, it can be used for any operand, even for several operands at the same. But for now this is a simple solution which fixes the problem (e.g. causing broken linear fog with radeonsi) at little extra cost (in the form of V_MOV_* from SGPR to VGPR). Patch by: Michel Dänzer Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Enable control flow pass againtstellar1-2/+1
radeonsi can run piglit reliably with it now. It fixes hundreds of tests and prevents many more from crashing. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Handle kilp intrinsictstellar1-0/+5
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Use SReg_1 class for SI_IF_(N)Z condition code operandtstellar1-3/+3
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Prevent instructions modifying the EXEC register from being movedtstellar2-0/+6
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167126 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Handle more cases in copyPhysReg callbacktstellar1-3/+15
Also add assertions failing in unhandled cases. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Alternative handling of EXEC register for control flowtstellar2-26/+36
This version handles the EXEC register being modified in the if/else blocks, e.g. for pixel discard. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Use SReg_64RegClass for i64 register clasststellar1-1/+1
Fixes invalid code being generated, trying to copy from VGPRs to SGPRs. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31R600: use specialised R600.store.pixel.* for fragment shadertstellar8-2/+185
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26R600: Add a v4f32 to v4i32 BitConvert patterntstellar1-0/+1
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26R600: Set isBarrier bit for JUMP instructiontstellar1-2/+2
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25SI: Add intrinsic for reading the FRONT_FACE VGPR.tstellar2-0/+6
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25SI: Use 64-bit encoding for V_CMP instructionststellar6-51/+155
The 64-bit encoding allows V_CMP instructions to write to any SGPR rather than just VCC. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEEtstellar1-10/+20
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166419 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: turn select into select_cctstellar2-0/+17
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: add support for vector setCCtstellar1-4/+2
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: Remove input.face and input.position intrinsicststellar3-40/+0
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166416 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: Add super reg to reserved reg listtstellar1-0/+3
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166415 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: interp instructions emits native outputststellar3-38/+27
Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166414 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22R600: Fix llvm.pow.ll testtstellar1-1/+1
This test needs to use the IEEE version of MUL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166413 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22AMDGPU: Fix build after mergetstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166412 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Merge master branchtstellar164-783/+5586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Remove deprecated code from R600MCCodeEmitterHEADmastertstellar1-129/+9
All ALU instructions now have their encodings defined in tablegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Use native operands for KILLGT instructiontstellar4-38/+29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Use native operands for CUBE*, DOT4* instructionststellar3-68/+46
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Organize pseudo instruction in R600Instructions.tdtstellar1-27/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Add support for the AMDGPU::BREAK instructiontstellar1-1/+17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Lower PRED_X to a native instruction prior to codegentstellar9-50/+111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19R600: Use native operands for R600_OP3 instructionststellar1-34/+64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166330 91177308-0d34-0410-b5e6-96231b3b80d8
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