SI: s/flow control/control flow/g .

Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167843 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 15 insertions, 15 deletions

diff --git a/lib/Target/AMDGPU/AMDGPU.h b/lib/Target/AMDGPU/AMDGPU.h
index 33a74dc597..2a06ade2bd 100644
--- a/lib/Target/AMDGPU/AMDGPU.h
+++ b/lib/Target/AMDGPU/AMDGPU.h
@@ -25,7 +25,7 @@ FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
 
 // SI Passes
 FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-FunctionPass *createSILowerFlowControlPass(TargetMachine &tm);
+FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 FunctionPass *createSILowerLiteralConstantsPass(TargetMachine &tm);
 FunctionPass *createSIFixSGPRLivenessPass(TargetMachine &tm);
diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 024ff3d600..5c4af91fce 100644
--- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -137,7 +137,7 @@ bool AMDGPUPassConfig::addPreEmitPass() {
     addPass(&FinalizeMachineBundlesID);
   } else {
     addPass(createSILowerLiteralConstantsPass(*TM));
-    addPass(createSILowerFlowControlPass(*TM));
+    addPass(createSILowerControlFlowPass(*TM));
   }
 
   return false;
diff --git a/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp b/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp
index 8c06f9ca6d..71641d1c83 100644
--- a/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp
+++ b/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// SGPRs are not affected by flow control. This pass adjust SGPR liveness in
+// SGPRs are not affected by control flow. This pass adjust SGPR liveness in
 // so that the register allocator can still correctly allocate them.
 //
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/AMDGPU/SILowerFlowControl.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 0d90c136ee..b43fdeb108 100644
--- a/lib/Target/AMDGPU/SILowerFlowControl.cpp
+++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -1,4 +1,4 @@
-//===-- SILowerFlowControl.cpp - Use predicates for flow control ----------===//
+//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,10 +7,10 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This pass lowers the pseudo flow control instructions (SI_IF_NZ, ELSE, ENDIF)
+// This pass lowers the pseudo control flow instructions (SI_IF_NZ, ELSE, ENDIF)
 // to predicated instructions.
 //
-// All flow control (except loops) is handled using predicated instructions and
+// All control flow (except loops) is handled using predicated instructions and
 // a predicate stack.  Each Scalar ALU controls the operations of 64 Vector
 // ALUs.  The Scalar ALU can update the predicate for any of the Vector ALUs
 // by writting to the 64-bit EXEC register (each bit corresponds to a
@@ -61,7 +61,7 @@ using namespace llvm;
 
 namespace {
 
-class SILowerFlowControlPass : public MachineFunctionPass {
+class SILowerControlFlowPass : public MachineFunctionPass {
 
 private:
   static char ID;
@@ -73,26 +73,26 @@ private:
   void popExecMask(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
 
 public:
-  SILowerFlowControlPass(TargetMachine &tm) :
+  SILowerControlFlowPass(TargetMachine &tm) :
     MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
 
   virtual bool runOnMachineFunction(MachineFunction &MF);
 
   const char *getPassName() const {
-    return "SI Lower flow control instructions";
+    return "SI Lower control flow instructions";
   }
 
 };
 
 } // End anonymous namespace
 
-char SILowerFlowControlPass::ID = 0;
+char SILowerControlFlowPass::ID = 0;
 
-FunctionPass *llvm::createSILowerFlowControlPass(TargetMachine &tm) {
-  return new SILowerFlowControlPass(tm);
+FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
+  return new SILowerControlFlowPass(tm);
 }
 
-bool SILowerFlowControlPass::runOnMachineFunction(MachineFunction &MF) {
+bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
 
   // Find all the unused registers that can be used for the predicate stack.
   for (TargetRegisterClass::iterator I = AMDGPU::SReg_64RegClass.begin(),
@@ -169,7 +169,7 @@ bool SILowerFlowControlPass::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-void SILowerFlowControlPass::pushExecMask(MachineBasicBlock &MBB,
+void SILowerControlFlowPass::pushExecMask(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator I) {
 
   assert(!UnusedRegisters.empty() && "Ran out of registers for predicate stack");
@@ -181,7 +181,7 @@ void SILowerFlowControlPass::pushExecMask(MachineBasicBlock &MBB,
           .addReg(AMDGPU::EXEC);
 }
 
-void SILowerFlowControlPass::popExecMask(MachineBasicBlock &MBB,
+void SILowerControlFlowPass::popExecMask(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator I) {
   unsigned StackReg = PredicateStack.back();
   PredicateStack.pop_back();