radeon/llvm: simplify stream outputs intrinsic

5 files changed, 13 insertions, 47 deletions

diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index 2cebe08fb4..37272b568f 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -388,39 +388,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
           Chain);
 
     }
-    case AMDGPUIntrinsic::R600_store_stream_output : {
-      MachineFunction &MF = DAG.getMachineFunction();
-      R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
-      int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
-      int64_t BufIndex = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
-
-      SDNode **OutputsMap = MFI->StreamOutputs[BufIndex];
-      unsigned Inst;
-      switch (cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue()  ) {
-      // STREAM3
-      case 3:
-        Inst = 4;
-        break;
-      // STREAM2
-      case 2:
-        Inst = 3;
-        break;
-      // STREAM1
-      case 1:
-        Inst = 2;
-        break;
-      // STREAM0
-      case 0:
-        Inst = 1;
-        break;
-      default:
-        assert(0 && "Wrong buffer id for stream outputs !");
-      }
 
-      return InsertScalarToRegisterExport(DAG, Op.getDebugLoc(), OutputsMap,
-          RegIndex / 4, RegIndex % 4, Inst, 0, Op.getOperand(2),
-          Chain);
-    }
     // default for switch(IntrinsicID)
     default: break;
     }
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 85869b32a8..b66f6cc8e0 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -597,24 +597,24 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
 multiclass SteamOutputExportPattern<Instruction ExportInst,
     bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
 // Stream0
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
-      (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
-      (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
+      (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
+      (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
       4095, imm:$mask, buf0inst, 0)>;
 // Stream1
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 2),
-      (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
-      (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
+      (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
+      (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
       4095, imm:$mask, buf1inst, 0)>;
 // Stream2
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 3),
-      (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
-      (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
+      (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
+      (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
       4095, imm:$mask, buf2inst, 0)>;
 // Stream3
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 4),
-      (i32 imm:$type), (i32 imm:$arraybase), (i32 imm:$mask)),
-      (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
+  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
+      (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
+      (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
       4095, imm:$mask, buf3inst, 0)>;
 }
 
diff --git a/lib/Target/R600/R600Intrinsics.td b/lib/Target/R600/R600Intrinsics.td
index 3825bc4d3b..06a734123f 100644
--- a/lib/Target/R600/R600Intrinsics.td
+++ b/lib/Target/R600/R600Intrinsics.td
@@ -20,7 +20,7 @@ let TargetPrefix = "R600", isTarget = 1 in {
   def int_R600_load_input_linear :
     Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
   def int_R600_store_stream_output :
-    Intrinsic<[], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], []>;
+    Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
   def int_R600_store_pixel_color :
       Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
   def int_R600_store_pixel_depth :
diff --git a/lib/Target/R600/R600MachineFunctionInfo.cpp b/lib/Target/R600/R600MachineFunctionInfo.cpp
index 4eb5efa19f..bcb7f94360 100644
--- a/lib/Target/R600/R600MachineFunctionInfo.cpp
+++ b/lib/Target/R600/R600MachineFunctionInfo.cpp
@@ -17,7 +17,6 @@ R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
     HasLinearInterpolation(false),
     HasPerspectiveInterpolation(false) {
     memset(Outputs, 0, sizeof(Outputs));
-    memset(StreamOutputs, 0, sizeof(StreamOutputs));
   }
 
 unsigned R600MachineFunctionInfo::GetIJPerspectiveIndex() const {
diff --git a/lib/Target/R600/R600MachineFunctionInfo.h b/lib/Target/R600/R600MachineFunctionInfo.h
index e97fb5be62..91f9de2827 100644
--- a/lib/Target/R600/R600MachineFunctionInfo.h
+++ b/lib/Target/R600/R600MachineFunctionInfo.h
@@ -25,7 +25,6 @@ public:
   R600MachineFunctionInfo(const MachineFunction &MF);
   std::vector<unsigned> ReservedRegs;
   SDNode *Outputs[16];
-  SDNode *StreamOutputs[64][4];
   bool HasLinearInterpolation;
   bool HasPerspectiveInterpolation;