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| author | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-10-22 15:04:10 +0000 |
|---|---|---|
| committer | tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8> | 2012-10-22 15:04:10 +0000 |
| commit | 075e37e688cdf9773b75b25a0536583f4ed96d45 (patch) | |
| tree | 2234c4d5c40f75769f3aefe61929acba735caa7e | |
| parent | c8387aead840d70b852fbbeff4e2d6dd0e74fedc (diff) | |
R600: Add super reg to reserved reg list
Patch by: Vincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166415 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/AMDGPU/R600ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index a7cb010124..094d920316 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -169,6 +169,9 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( unsigned ReservedReg = AMDGPU::R600_TReg32RegClass.getRegister(ReservedIndex); MFI->ReservedRegs.push_back(ReservedReg); + unsigned SuperReg = + AMDGPU::R600_Reg128RegClass.getRegister(ReservedIndex / 4); + MFI->ReservedRegs.push_back(SuperReg); break; } |