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-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/common.c42
-rw-r--r--arch/arm/plat-omap/counter_32k.c3
-rw-r--r--arch/arm/plat-omap/debug-devices.c3
-rw-r--r--arch/arm/plat-omap/debug-leds.c1
-rw-r--r--arch/arm/plat-omap/devices.c92
-rw-r--r--arch/arm/plat-omap/dma.c54
-rw-r--r--arch/arm/plat-omap/fb.c2
-rw-r--r--arch/arm/plat-omap/i2c.c4
-rw-r--r--arch/arm/plat-omap/include/plat/am33xx.h25
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h71
-rw-r--r--arch/arm/plat-omap/include/plat/board-sx1.h52
-rw-r--r--arch/arm/plat-omap/include/plat/board-voiceblue.h19
-rw-r--r--arch/arm/plat-omap/include/plat/board.h138
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h2
-rw-r--r--arch/arm/plat-omap/include/plat/dsp.h34
-rw-r--r--arch/arm/plat-omap/include/plat/flash.h17
-rw-r--r--arch/arm/plat-omap/include/plat/gpio-switch.h54
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h228
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smc91x.h42
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smsc911x.h35
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h19
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h293
-rw-r--r--arch/arm/plat-omap/include/plat/hdq1w.h36
-rw-r--r--arch/arm/plat-omap/include/plat/irda.h33
-rw-r--r--arch/arm/plat-omap/include/plat/irqs-44xx.h144
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h453
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h52
-rw-r--r--arch/arm/plat-omap/include/plat/l3_2xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l3_3xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l4_2xxx.h24
-rw-r--r--arch/arm/plat-omap/include/plat/l4_3xxx.h34
-rw-r--r--arch/arm/plat-omap/include/plat/lcd_mipid.h29
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h62
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h23
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h1
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h454
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h44
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap1510.h50
-rw-r--r--arch/arm/plat-omap/include/plat/omap16xx.h202
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h89
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h101
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h62
-rw-r--r--arch/arm/plat-omap/include/plat/omap54xx.h32
-rw-r--r--arch/arm/plat-omap/include/plat/omap7xx.h107
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h53
-rw-r--r--arch/arm/plat-omap/include/plat/param.h8
-rw-r--r--arch/arm/plat-omap/include/plat/remoteproc.h57
-rw-r--r--arch/arm/plat-omap/include/plat/ti81xx.h27
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h1
-rw-r--r--arch/arm/plat-omap/include/plat/voltage.h39
-rw-r--r--arch/arm/plat-omap/mux.c90
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c39
-rw-r--r--arch/arm/plat-omap/omap_device.c25
-rw-r--r--arch/arm/plat-omap/sram.c1
59 files changed, 83 insertions, 3576 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba9506c..d15a4a6d6146 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2PLUS
bool "TI OMAP2/3/4"
select CLKDEV_LOOKUP
select GENERIC_IRQ_CHIP
+ select SPARSE_IRQ
select OMAP_DM_TIMER
select USE_OF
select PROC_DEVICETREE if PROC_FS
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 961bf859bc0c..dacaee009a4e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,7 @@
#
# Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
- fb.o counter_32k.o
+obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o
obj-m :=
obj-n :=
obj- :=
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 89a3723b3538..111315a69354 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -17,52 +17,12 @@
#include <linux/dma-mapping.h>
#include <plat/common.h>
-#include <plat/board.h>
#include <plat/vram.h>
-#include <plat/dsp.h>
+#include <linux/platform_data/dsp-omap.h>
#include <plat/dma.h>
#include <plat/omap-secure.h>
-
-#define NO_LENGTH_CHECK 0xffffffff
-
-struct omap_board_config_kernel *omap_board_config __initdata;
-int omap_board_config_size;
-
-static const void *__init get_config(u16 tag, size_t len,
- int skip, size_t *len_out)
-{
- struct omap_board_config_kernel *kinfo = NULL;
- int i;
-
- /* Try to find the config from the board-specific structures
- * in the kernel. */
- for (i = 0; i < omap_board_config_size; i++) {
- if (omap_board_config[i].tag == tag) {
- if (skip == 0) {
- kinfo = &omap_board_config[i];
- break;
- } else {
- skip--;
- }
- }
- }
- if (kinfo == NULL)
- return NULL;
- return kinfo->data;
-}
-
-const void *__init __omap_get_config(u16 tag, size_t len, int nr)
-{
- return get_config(tag, len, nr, NULL);
-}
-
-const void *__init omap_get_var_config(u16 tag, size_t *len)
-{
- return get_config(tag, NO_LENGTH_CHECK, 0, len);
-}
-
void __init omap_reserve(void)
{
omap_vram_reserve_sdram_memblock();
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index dbf1e03029a5..2e826f1faf7b 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,10 +22,7 @@
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
-#include <plat/hardware.h>
#include <plat/common.h>
-#include <plat/board.h>
-
#include <plat/clock.h>
/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index caa1f7b6cc21..c7a4c0902b38 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -17,9 +17,6 @@
#include <mach/hardware.h>
-#include <plat/board.h>
-
-
/* Many OMAP development platforms reuse the same "debug board"; these
* platforms include H2, H3, H4, and Perseus2.
*/
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cbe34c6..195aaae65872 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -12,6 +12,7 @@
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
#include <mach/hardware.h>
#include <asm/leds.h>
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
deleted file mode 100644
index 1cba9273d2cb..000000000000
--- a/arch/arm/plat-omap/devices.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/devices.c
- *
- * Common platform device setup/initialization for OMAP1 and OMAP2
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/memblock.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-
-#include <plat/tc.h>
-#include <plat/board.h>
-#include <plat/mmc.h>
-#include <plat/menelaus.h>
-#include <plat/omap44xx.h>
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-#define OMAP_RNG_BASE 0x480A0000
-#else
-#define OMAP_RNG_BASE 0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
- {
- .start = OMAP_RNG_BASE,
- .end = OMAP_RNG_BASE + 0x4f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device omap_rng_device = {
- .name = "omap_rng",
- .id = -1,
- .num_resources = ARRAY_SIZE(rng_resources),
- .resource = rng_resources,
-};
-
-static void omap_init_rng(void)
-{
- (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
-/*
- * This gets called after board-specific INIT_MACHINE, and initializes most
- * on-chip peripherals accessible on this board (except for few like USB):
- *
- * (a) Does any "standard config" pin muxing needed. Board-specific
- * code will have muxed GPIO pins and done "nonstandard" setup;
- * that code could live in the boot loader.
- * (b) Populating board-specific platform_data with the data drivers
- * rely on to handle wiring variations.
- * (c) Creating platform devices as meaningful on this board and
- * with this kernel configuration.
- *
- * Claiming GPIOs, and setting their direction and initial values, is the
- * responsibility of the device drivers. So is responding to probe().
- *
- * Board-specific knowledge like creating devices or pin setup is to be
- * kept out of drivers as much as possible. In particular, pin setup
- * may be handled by the boot loader, and drivers should expect it will
- * normally have been done by the time they're probed.
- */
-static int __init omap_init_devices(void)
-{
- /* please keep these calls, and their implementations above,
- * in alphabetical order so they're easier to sort through.
- */
- omap_init_rng();
- return 0;
-}
-arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fe626761e53..c76ed8bff838 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,8 @@
#include <linux/slab.h>
#include <linux/delay.h>
-#include <mach/hardware.h>
+#include <plat/cpu.h>
#include <plat/dma.h>
-
#include <plat/tc.h>
/*
@@ -969,8 +968,7 @@ void omap_stop_dma(int lch)
l = p->dma_read(CCR, lch);
}
if (i >= 100)
- printk(KERN_ERR "DMA drain did not complete on "
- "lch %d\n", lch);
+ pr_err("DMA drain did not complete on lch %d\n", lch);
/* Restore OCP_SYSCONFIG */
p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
} else {
@@ -1154,8 +1152,7 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) {
- printk(KERN_ERR "omap_dma: trying to link "
- "non requested channels\n");
+ pr_err("omap_dma: trying to link non requested channels\n");
dump_stack();
}
@@ -1181,15 +1178,13 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) {
- printk(KERN_ERR "omap_dma: trying to unlink "
- "non linked channels\n");
+ pr_err("omap_dma: trying to unlink non linked channels\n");
dump_stack();
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
- printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
- "before unlinking\n");
+ pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
dump_stack();
}
@@ -1831,16 +1826,15 @@ static int omap1_dma_handle_ch(int ch)
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
- printk(KERN_WARNING "Spurious interrupt from DMA channel "
- "%d (CSR %04x)\n", ch, csr);
+ pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+ ch, csr);
return 0;
}
if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
- printk(KERN_WARNING "DMA timeout with device %d\n",
- dma_chan[ch].dev_id);
+ pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
- printk(KERN_WARNING "DMA synchronization event drop occurred "
- "with device %d\n", dma_chan[ch].dev_id);
+ pr_warn("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
@@ -1880,21 +1874,19 @@ static int omap2_dma_handle_ch(int ch)
if (!status) {
if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
- ch);
+ pr_warn("Spurious DMA IRQ for lch %d\n", ch);
p->dma_write(1 << ch, IRQSTATUS_L0, ch);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {
if (printk_ratelimit())
- printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
- "channel %d\n", status, ch);
+ pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+ status, ch);
return 0;
}
if (unlikely(status & OMAP_DMA_DROP_IRQ))
- printk(KERN_INFO
- "DMA synchronization event drop occurred with device "
- "%d\n", dma_chan[ch].dev_id);
+ pr_info("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
@@ -2014,8 +2006,9 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
p = pdev->dev.platform_data;
if (!p) {
- dev_err(&pdev->dev, "%s: System DMA initialized without"
- "platform data\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: System DMA initialized without platform data\n",
+ __func__);
return -EINVAL;
}
@@ -2090,8 +2083,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
}
ret = setup_irq(dma_irq, &omap24xx_dma_irq);
if (ret) {
- dev_err(&pdev->dev, "set_up failed for IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
goto exit_dma_lch_fail;
}
}
@@ -2099,8 +2092,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
/* reserve dma channels 0 and 1 in high security devices */
if (cpu_is_omap34xx() &&
(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
- "HS ROM code\n");
+ pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
dma_chan[0].dev_id = 0;
dma_chan[1].dev_id = 1;
}
@@ -2108,8 +2100,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
return 0;
exit_dma_irq_fail:
- dev_err(&pdev->dev, "unable to request IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
for (irq_rel = 0; irq_rel < ch; irq_rel++) {
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index dd6f92c99e56..bcbb9d5dc293 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,8 +33,6 @@
#include <mach/hardware.h>
#include <asm/mach/map.h>
-#include <plat/board.h>
-
#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc71c4d..6013831a043e 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -32,13 +32,13 @@
#include <linux/clk.h>
#include <mach/irqs.h>
-#include <plat/mux.h>
#include <plat/i2c.h>
#include <plat/omap-pm.h>
#include <plat/omap_device.h>
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
+#define OMAP1_INT_I2C (32 + 4)
static const char name[] = "omap_i2c";
@@ -105,7 +105,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
res = pdev->resource;
res[0].start = OMAP1_I2C_BASE;
res[0].end = res[0].start + OMAP_I2C_SIZE;
- res[1].start = INT_I2C;
+ res[1].start = OMAP1_INT_I2C;
pdata = &i2c_pdata[bus_id - 1];
/* all OMAP1 have IP version 1 register set */
diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h
deleted file mode 100644
index 06c19bb7bca6..000000000000
--- a/arch/arm/plat-omap/include/plat/am33xx.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file contains the address info for various AM33XX modules.
- *
- * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_AM33XX_H
-#define __ASM_ARCH_AM33XX_H
-
-#define L4_SLOW_AM33XX_BASE 0x48000000
-
-#define AM33XX_SCM_BASE 0x44E10000
-#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
-#define AM33XX_PRCM_BASE 0x44E00000
-
-#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
deleted file mode 100644
index ad6f865d1f16..000000000000
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board-ams-delta.h
- *
- * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
-#define __ASM_ARCH_OMAP_AMS_DELTA_H
-
-#if defined (CONFIG_MACH_AMS_DELTA)
-
-#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
-#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
-#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
-
-#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
-#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
-#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
-#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
-#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
-#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
-#define AMS_DELTA_GPIO_PIN_CONFIG 11
-#define AMS_DELTA_GPIO_PIN_NAND_RB 12
-
-#define AMS_DELTA_GPIO_PIN_LCD_VBLEN 240
-#define AMS_DELTA_GPIO_PIN_LCD_NDISP 241
-#define AMS_DELTA_GPIO_PIN_NAND_NCE 242
-#define AMS_DELTA_GPIO_PIN_NAND_NRE 243
-#define AMS_DELTA_GPIO_PIN_NAND_NWP 244
-#define AMS_DELTA_GPIO_PIN_NAND_NWE 245
-#define AMS_DELTA_GPIO_PIN_NAND_ALE 246
-#define AMS_DELTA_GPIO_PIN_NAND_CLE 247
-#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR 248
-#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT 249
-#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN 250
-#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC 251
-#define AMS_DELTA_GPIO_PIN_MODEM_NRESET 252
-#define AMS_DELTA_GPIO_PIN_MODEM_CODEC 253
-
-#define AMS_DELTA_LATCH2_GPIO_BASE AMS_DELTA_GPIO_PIN_LCD_VBLEN
-#define AMS_DELTA_LATCH2_NGPIO 16
-
-#ifndef __ASSEMBLY__
-void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
-#define ams_delta_latch2_write(mask, value) \
- ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
- AMS_DELTA_LATCH2_NGPIO, (mask), (value))
-#endif
-
-#endif /* CONFIG_MACH_AMS_DELTA */
-
-#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
deleted file mode 100644
index 355adbdaae33..000000000000
--- a/arch/arm/plat-omap/include/plat/board-sx1.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Siemens SX1 board definitions
- *
- * Copyright: Vovan888 at gmail com
- *
- * This package is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
-#define __ASM_ARCH_SX1_I2C_CHIPS_H
-
-#define SOFIA_MAX_LIGHT_VAL 0x2B
-
-#define SOFIA_I2C_ADDR 0x32
-/* Sofia reg 3 bits masks */
-#define SOFIA_POWER1_REG 0x03
-
-#define SOFIA_USB_POWER 0x01
-#define SOFIA_MMC_POWER 0x04
-#define SOFIA_BLUETOOTH_POWER 0x08
-#define SOFIA_MMILIGHT_POWER 0x20
-
-#define SOFIA_POWER2_REG 0x04
-#define SOFIA_BACKLIGHT_REG 0x06
-#define SOFIA_KEYLIGHT_REG 0x07
-#define SOFIA_DIMMING_REG 0x09
-
-
-/* Function Prototypes for SX1 devices control on I2C bus */
-
-int sx1_setbacklight(u8 backlight);
-int sx1_getbacklight(u8 *backlight);
-int sx1_setkeylight(u8 keylight);
-int sx1_getkeylight(u8 *keylight);
-
-int sx1_setmmipower(u8 onoff);
-int sx1_setusbpower(u8 onoff);
-int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
-int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
-
-/* MMC prototypes */
-
-extern void sx1_mmc_init(void);
-extern void sx1_mmc_slot_cover_handler(void *arg, int state);
-
-#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
deleted file mode 100644
index 27916b210f57..000000000000
--- a/arch/arm/plat-omap/include/plat/board-voiceblue.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
- *
- * Hardware definitions for OMAP5910 based VoiceBlue board.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_VOICEBLUE_H
-#define __ASM_ARCH_VOICEBLUE_H
-
-extern void voiceblue_wdt_enable(void);
-extern void voiceblue_wdt_disable(void);
-extern void voiceblue_wdt_ping(void);
-
-#endif /* __ASM_ARCH_VOICEBLUE_H */
-
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
deleted file mode 100644
index e62f20a5c0af..000000000000
--- a/arch/arm/plat-omap/include/plat/board.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/board.h
- *
- * Information structures for board-specific data
- *
- * Copyright (C) 2004 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- */
-
-#ifndef _OMAP_BOARD_H
-#define _OMAP_BOARD_H
-
-#include <linux/types.h>
-
-#include <plat/gpio-switch.h>
-
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- * GEN_1 = 0x01150000
- * GEN_2 = 0x92200000
- */
-enum {
- OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
- OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
-};
-
-/* Different peripheral ids */
-#define OMAP_TAG_CLOCK 0x4f01
-#define OMAP_TAG_GPIO_SWITCH 0x4f06
-#define OMAP_TAG_STI_CONSOLE 0x4f09
-#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
-
-#define OMAP_TAG_BOOT_REASON 0x4f80
-#define OMAP_TAG_FLASH_PART 0x4f81
-#define OMAP_TAG_VERSION_STR 0x4f82
-
-struct omap_clock_config {
- /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
- u8 system_clock_type;
-};
-
-struct omap_serial_console_config {
- u8 console_uart;
- u32 console_speed;
-};
-
-struct omap_sti_console_config {
- unsigned enable:1;
- u8 channel;
-};
-
-struct omap_camera_sensor_config {
- u16 reset_gpio;
- int (*power_on)(void * data);
- int (*power_off)(void * data);
-};
-
-struct omap_lcd_config {
- char panel_name[16];
- char ctrl_name[16];
- s16 nreset_gpio;
- u8 data_lines;
-};
-
-struct device;
-struct fb_info;
-struct omap_backlight_config {
- int default_intensity;
- int (*set_power)(struct device *dev, int state);
-};
-
-struct omap_fbmem_config {
- u32 start;
- u32 size;
-};
-
-struct omap_pwm_led_platform_data {
- const char *name;
- int intensity_timer;
- int blink_timer;
- void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
-};
-
-struct omap_uart_config {
- /* Bit field of UARTs present; bit 0 --> UART1 */
- unsigned int enabled_uarts;
-};
-
-
-struct omap_flash_part_config {
- char part_table[0];
-};
-
-struct omap_boot_reason_config {
- char reason_str[12];
-};
-
-struct omap_version_config {
- char component[12];
- char version[12];
-};
-
-struct omap_board_config_entry {
- u16 tag;
- u16 len;
- u8 data[0];
-};
-
-struct omap_board_config_kernel {
- u16 tag;
- const void *data;
-};
-
-extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
-
-#define omap_get_config(tag, type) \
- ((const type *) __omap_get_config((tag), sizeof(type), 0))
-#define omap_get_nr_config(tag, type, nr) \
- ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-
-extern const void *__init omap_get_var_config(u16 tag, size_t *len);
-
-extern struct omap_board_config_kernel *omap_board_config;
-extern int omap_board_config_size;
-
-
-/* for TI reference platforms sharing the same debug card */
-extern int debug_card_init(u32 addr, unsigned gpio);
-
-/* OMAP3EVM revision */
-#if defined(CONFIG_MACH_OMAP3EVM)
-u8 get_omap3_evm_rev(void);
-#else
-#define get_omap3_evm_rev() (-EINVAL)
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index bb5d08a70dbc..67da857783ce 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -30,6 +30,8 @@
#ifndef __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
+#ifndef __ASSEMBLY__
+
#include <linux/bitops.h>
#include <plat/multi.h>
@@ -493,4 +495,5 @@ OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index c5811d4409b0..0a87b052f8f7 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -31,6 +31,8 @@
/* Move omap4 specific defines to dma-44xx.h */
#include "dma-44xx.h"
+#define INT_DMA_LCD 25
+
/* DMA channels for omap1 */
#define OMAP_DMA_NO_DEVICE 0
#define OMAP_DMA_MCSI1_TX 1
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
deleted file mode 100644
index 5927709b1908..000000000000
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef __OMAP_DSP_H__
-#define __OMAP_DSP_H__
-
-#include <linux/types.h>
-
-struct omap_dsp_platform_data {
- void (*dsp_set_min_opp) (u8 opp_id);
- u8 (*dsp_get_opp) (void);
- void (*cpu_set_freq) (unsigned long f);
- unsigned long (*cpu_get_freq) (void);
- unsigned long mpu_speed[6];
-
- /* functions to write and read PRCM registers */
- void (*dsp_prm_write)(u32, s16 , u16);
- u32 (*dsp_prm_read)(s16 , u16);
- u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
- void (*dsp_cm_write)(u32, s16 , u16);
- u32 (*dsp_cm_read)(s16 , u16);
- u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
-
- void (*set_bootaddr)(u32);
- void (*set_bootmode)(u8);
-
- phys_addr_t phys_mempool_base;
- phys_addr_t phys_mempool_size;
-};
-
-#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
-extern void omap_dsp_reserve_sdram_memblock(void);
-#else
-static inline void omap_dsp_reserve_sdram_memblock(void) { }
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
deleted file mode 100644
index 0d88499b79e9..000000000000
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Flash support for OMAP1
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __OMAP_FLASH_H
-#define __OMAP_FLASH_H
-
-#include <linux/mtd/map.h>
-
-struct platform_device;
-extern void omap1_set_vpp(struct platform_device *pdev, int enable);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
deleted file mode 100644
index 10da0e07c0cf..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio-switch.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * GPIO switch definitions
- *
- * Copyright (C) 2006 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
-#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
-
-#include <linux/types.h>
-
-/* Cover:
- * high -> closed
- * low -> open
- * Connection:
- * high -> connected
- * low -> disconnected
- * Activity:
- * high -> active
- * low -> inactive
- *
- */
-#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
-#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
-#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
-#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
-#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
-
-struct omap_gpio_switch {
- const char *name;
- s16 gpio;
- unsigned flags:4;
- unsigned type:4;
-
- /* Time in ms to debounce when transitioning from
- * inactive state to active state. */
- u16 debounce_rising;
- /* Same for transition from active to inactive state. */
- u16 debounce_falling;
-
- /* notify board-specific code about state changes */
- void (* notify)(void *data, int state);
- void *notify_data;
-};
-
-/* Call at init time only */
-extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
- int count);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
deleted file mode 100644
index 50fb7cc000ea..000000000000
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/gpio.h
- *
- * OMAP GPIO handling defines and functions
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- *
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_OMAP_GPIO_H
-#define __ASM_ARCH_OMAP_GPIO_H
-
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/irqs.h>
-
-#define OMAP1_MPUIO_BASE 0xfffb5000
-
-/*
- * These are the omap15xx/16xx offsets. The omap7xx offset are
- * OMAP_MPUIO_ / 2 offsets below.
- */
-#define OMAP_MPUIO_INPUT_LATCH 0x00
-#define OMAP_MPUIO_OUTPUT 0x04
-#define OMAP_MPUIO_IO_CNTL 0x08
-#define OMAP_MPUIO_KBR_LATCH 0x10
-#define OMAP_MPUIO_KBC 0x14
-#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
-#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
-#define OMAP_MPUIO_KBD_INT 0x20
-#define OMAP_MPUIO_GPIO_INT 0x24
-#define OMAP_MPUIO_KBD_MASKIT 0x28
-#define OMAP_MPUIO_GPIO_MASKIT 0x2c
-#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
-#define OMAP_MPUIO_LATCH 0x34
-
-#define OMAP34XX_NR_GPIOS 6
-
-/*
- * OMAP1510 GPIO registers
- */
-#define OMAP1510_GPIO_DATA_INPUT 0x00
-#define OMAP1510_GPIO_DATA_OUTPUT 0x04
-#define OMAP1510_GPIO_DIR_CONTROL 0x08
-#define OMAP1510_GPIO_INT_CONTROL 0x0c
-#define OMAP1510_GPIO_INT_MASK 0x10
-#define OMAP1510_GPIO_INT_STATUS 0x14
-#define OMAP1510_GPIO_PIN_CONTROL 0x18
-
-#define OMAP1510_IH_GPIO_BASE 64
-
-/*
- * OMAP1610 specific GPIO registers
- */
-#define OMAP1610_GPIO_REVISION 0x0000
-#define OMAP1610_GPIO_SYSCONFIG 0x0010
-#define OMAP1610_GPIO_SYSSTATUS 0x0014
-#define OMAP1610_GPIO_IRQSTATUS1 0x0018
-#define OMAP1610_GPIO_IRQENABLE1 0x001c
-#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
-#define OMAP1610_GPIO_DATAIN 0x002c
-#define OMAP1610_GPIO_DATAOUT 0x0030
-#define OMAP1610_GPIO_DIRECTION 0x0034
-#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
-#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
-#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
-#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
-#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
-#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
-#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
-#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
-
-/*
- * OMAP7XX specific GPIO registers
- */
-#define OMAP7XX_GPIO_DATA_INPUT 0x00
-#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
-#define OMAP7XX_GPIO_DIR_CONTROL 0x08
-#define OMAP7XX_GPIO_INT_CONTROL 0x0c
-#define OMAP7XX_GPIO_INT_MASK 0x10
-#define OMAP7XX_GPIO_INT_STATUS 0x14
-
-/*
- * omap2+ specific GPIO registers
- */
-#define OMAP24XX_GPIO_REVISION 0x0000
-#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
-#define OMAP24XX_GPIO_IRQENABLE2 0x002c
-#define OMAP24XX_GPIO_IRQENABLE1 0x001c
-#define OMAP24XX_GPIO_WAKE_EN 0x0020
-#define OMAP24XX_GPIO_CTRL 0x0030
-#define OMAP24XX_GPIO_OE 0x0034
-#define OMAP24XX_GPIO_DATAIN 0x0038
-#define OMAP24XX_GPIO_DATAOUT 0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
-#define OMAP24XX_GPIO_RISINGDETECT 0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
-#define OMAP24XX_GPIO_SETWKUENA 0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
-#define OMAP24XX_GPIO_SETDATAOUT 0x0094
-
-#define OMAP4_GPIO_REVISION 0x0000
-#define OMAP4_GPIO_EOI 0x0020
-#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
-#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
-#define OMAP4_GPIO_IRQSTATUS0 0x002c
-#define OMAP4_GPIO_IRQSTATUS1 0x0030
-#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
-#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
-#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
-#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
-#define OMAP4_GPIO_IRQWAKEN0 0x0044
-#define OMAP4_GPIO_IRQWAKEN1 0x0048
-#define OMAP4_GPIO_IRQENABLE1 0x011c
-#define OMAP4_GPIO_WAKE_EN 0x0120
-#define OMAP4_GPIO_IRQSTATUS2 0x0128
-#define OMAP4_GPIO_IRQENABLE2 0x012c
-#define OMAP4_GPIO_CTRL 0x0130
-#define OMAP4_GPIO_OE 0x0134
-#define OMAP4_GPIO_DATAIN 0x0138
-#define OMAP4_GPIO_DATAOUT 0x013c
-#define OMAP4_GPIO_LEVELDETECT0 0x0140
-#define OMAP4_GPIO_LEVELDETECT1 0x0144
-#define OMAP4_GPIO_RISINGDETECT 0x0148
-#define OMAP4_GPIO_FALLINGDETECT 0x014c
-#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
-#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
-#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
-#define OMAP4_GPIO_SETIRQENABLE1 0x0164
-#define OMAP4_GPIO_CLEARWKUENA 0x0180
-#define OMAP4_GPIO_SETWKUENA 0x0184
-#define OMAP4_GPIO_CLEARDATAOUT 0x0190
-#define OMAP4_GPIO_SETDATAOUT 0x0194
-
-#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
-#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
-
-struct omap_gpio_dev_attr {
- int bank_width; /* GPIO bank width */
- bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
-};
-
-struct omap_gpio_reg_offs {
- u16 revision;
- u16 direction;
- u16 datain;
- u16 dataout;
- u16 set_dataout;
- u16 clr_dataout;
- u16 irqstatus;
- u16 irqstatus2;
- u16 irqstatus_raw0;
- u16 irqstatus_raw1;
- u16 irqenable;
- u16 irqenable2;
- u16 set_irqenable;
- u16 clr_irqenable;
- u16 debounce;
- u16 debounce_en;
- u16 ctrl;
- u16 wkup_en;
- u16 leveldetect0;
- u16 leveldetect1;
- u16 risingdetect;
- u16 fallingdetect;
- u16 irqctrl;
- u16 edgectrl1;
- u16 edgectrl2;
- u16 pinctrl;
-
- bool irqenable_inv;
-};
-
-struct omap_gpio_platform_data {
- int bank_type;
- int bank_width; /* GPIO bank width */
- int bank_stride; /* Only needed for omap1 MPUIO */
- bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
- bool loses_context; /* whether the bank would ever lose context */
- bool is_mpuio; /* whether the bank is of type MPUIO */
- u32 non_wakeup_gpios;
-
- struct omap_gpio_reg_offs *regs;
-
- /* Return context loss count due to PM states changing */
- int (*get_context_loss_count)(struct device *dev);
-};
-
-extern void omap2_gpio_prepare_for_idle(int off_mode);
-extern void omap2_gpio_resume_after_idle(void);
-extern void omap_set_gpio_debounce(int gpio, int enable);
-extern void omap_set_gpio_debounce_time(int gpio, int enable);
-/*-------------------------------------------------------------------------*/
-
-/*
- * Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- *
- * The original OMAP-specific calls should eventually be removed.
- */
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
deleted file mode 100644
index b64fbee4d567..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
-
-#define GPMC_TIMINGS_SMC91C96 (1 << 4)
-#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
-#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
-#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
-
-struct omap_smc91x_platform_data {
- int cs;
- int gpio_irq;
- int gpio_pwrdwn;
- int gpio_reset;
- int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
- u32 flags;
- int (*retime)(void);
-};
-
-#if defined(CONFIG_SMC91X) || \
- defined(CONFIG_SMC91X_MODULE)
-
-extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
-
-#else
-
-#define board_smc91x_data NULL
-
-static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
-{
-}
-
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
deleted file mode 100644
index ea6c9c88c725..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
- *
- * Copyright (C) 2009 Li-Pro.Net
- * Stephan Linz <linz@li-pro.net>
- *
- * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
-
-struct omap_smsc911x_platform_data {
- int id;
- int cs;
- int gpio_irq;
- int gpio_reset;
- u32 flags;
-};
-
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-
-extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
-
-#else
-
-static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
-{
-}
-
-#endif
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index f37764a36072..2e6e2597178c 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -133,6 +133,25 @@ struct gpmc_timings {
u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
};
+struct gpmc_nand_regs {
+ void __iomem *gpmc_status;
+ void __iomem *gpmc_nand_command;
+ void __iomem *gpmc_nand_address;
+ void __iomem *gpmc_nand_data;
+ void __iomem *gpmc_prefetch_config1;
+ void __iomem *gpmc_prefetch_config2;
+ void __iomem *gpmc_prefetch_control;
+ void __iomem *gpmc_prefetch_status;
+ void __iomem *gpmc_ecc_config;
+ void __iomem *gpmc_ecc_control;
+ void __iomem *gpmc_ecc_size_config;
+ void __iomem *gpmc_ecc1_result;
+ void __iomem *gpmc_bch_result0;
+};
+
+extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
+extern int gpmc_get_client_irq(unsigned irq_config);
+
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
deleted file mode 100644
index ddbde38e1e33..000000000000
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/hardware.h
- *
- * Hardware definitions for TI OMAP processors and boards
- *
- * NOTE: Please put device driver specific defines into a separate header
- * file for each driver.
- *
- * Copyright (C) 2001 RidgeRun, Inc.
- * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
- *
- * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
- * and Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP_HARDWARE_H
-#define __ASM_ARCH_OMAP_HARDWARE_H
-
-#include <asm/sizes.h>
-#ifndef __ASSEMBLER__
-#include <asm/types.h>
-#include <plat/cpu.h>
-#endif
-#include <plat/serial.h>
-
-/*
- * ---------------------------------------------------------------------------
- * Common definitions for all OMAP processors
- * NOTE: Put all processor or board specific parts to the special header
- * files.
- * ---------------------------------------------------------------------------
- */
-
-/*
- * ----------------------------------------------------------------------------
- * Timers
- * ----------------------------------------------------------------------------
- */
-#define OMAP_MPU_TIMER1_BASE (0xfffec500)
-#define OMAP_MPU_TIMER2_BASE (0xfffec600)
-#define OMAP_MPU_TIMER3_BASE (0xfffec700)
-#define MPU_TIMER_FREE (1 << 6)
-#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
-#define MPU_TIMER_AR (1 << 1)
-#define MPU_TIMER_ST (1 << 0)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define CLKGEN_REG_BASE (0xfffece00)
-#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
-#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
-#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
-#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
-#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
-#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
-#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
-#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
-
-#define CK_RATEF 1
-#define CK_IDLEF 2
-#define CK_ENABLEF 4
-#define CK_SELECTF 8
-#define SETARM_IDLE_SHIFT
-
-/* DPLL control registers */
-#define DPLL_CTL (0xfffecf00)
-
-/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
-#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
-#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
-#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
-#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
-#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
-
-/*
- * ---------------------------------------------------------------------------
- * UPLD
- * ---------------------------------------------------------------------------
- */
-#define ULPD_REG_BASE (0xfffe0800)
-#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
-#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
-#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
-# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
-# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
-#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
-# define SOFT_UDC_REQ (1 << 4)
-# define SOFT_USB_CLK_REQ (1 << 3)
-# define SOFT_DPLL_REQ (1 << 0)
-#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
-#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
-# define DIS_MMC2_DPLL_REQ (1 << 11)
-# define DIS_MMC1_DPLL_REQ (1 << 10)
-# define DIS_UART3_DPLL_REQ (1 << 9)
-# define DIS_UART2_DPLL_REQ (1 << 8)
-# define DIS_UART1_DPLL_REQ (1 << 7)
-# define DIS_USB_HOST_DPLL_REQ (1 << 6)
-#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
-#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* Watchdog timer within the OMAP3.2 gigacell */
-#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
-#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
-#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
-#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_ARCH_OMAP1
-
-/*
- * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
- * or something similar.. -- PFM.
- */
-
-#define OMAP_IH1_BASE 0xfffecb00
-#define OMAP_IH2_BASE 0xfffe0000
-
-#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
-#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
-#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
-#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
-#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
-#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
-#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
-
-#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
-#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
-#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
-#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
-#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
-#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
-#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
-
-#define IRQ_ITR_REG_OFFSET 0x00
-#define IRQ_MIR_REG_OFFSET 0x04
-#define IRQ_SIR_IRQ_REG_OFFSET 0x10
-#define IRQ_SIR_FIQ_REG_OFFSET 0x14
-#define IRQ_CONTROL_REG_OFFSET 0x18
-#define IRQ_ISR_REG_OFFSET 0x9c
-#define IRQ_ILR0_REG_OFFSET 0x1c
-#define IRQ_GMR_REG_OFFSET 0xa0
-
-#endif
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define MOD_CONF_CTRL_0 0xfffe1080
-#define MOD_CONF_CTRL_1 0xfffe1110
-
-/*
- * ----------------------------------------------------------------------------
- * Pin multiplexing registers
- * ----------------------------------------------------------------------------
- */
-#define FUNC_MUX_CTRL_0 0xfffe1000
-#define FUNC_MUX_CTRL_1 0xfffe1004
-#define FUNC_MUX_CTRL_2 0xfffe1008
-#define COMP_MODE_CTRL_0 0xfffe100c
-#define FUNC_MUX_CTRL_3 0xfffe1010
-#define FUNC_MUX_CTRL_4 0xfffe1014
-#define FUNC_MUX_CTRL_5 0xfffe1018
-#define FUNC_MUX_CTRL_6 0xfffe101C
-#define FUNC_MUX_CTRL_7 0xfffe1020
-#define FUNC_MUX_CTRL_8 0xfffe1024
-#define FUNC_MUX_CTRL_9 0xfffe1028
-#define FUNC_MUX_CTRL_A 0xfffe102C
-#define FUNC_MUX_CTRL_B 0xfffe1030
-#define FUNC_MUX_CTRL_C 0xfffe1034
-#define FUNC_MUX_CTRL_D 0xfffe1038
-#define PULL_DWN_CTRL_0 0xfffe1040
-#define PULL_DWN_CTRL_1 0xfffe1044
-#define PULL_DWN_CTRL_2 0xfffe1048
-#define PULL_DWN_CTRL_3 0xfffe104c
-#define PULL_DWN_CTRL_4 0xfffe10ac
-
-/* OMAP-1610 specific multiplexing registers */
-#define FUNC_MUX_CTRL_E 0xfffe1090
-#define FUNC_MUX_CTRL_F 0xfffe1094
-#define FUNC_MUX_CTRL_10 0xfffe1098
-#define FUNC_MUX_CTRL_11 0xfffe109c
-#define FUNC_MUX_CTRL_12 0xfffe10a0
-#define PU_PD_SEL_0 0xfffe10b4
-#define PU_PD_SEL_1 0xfffe10b8
-#define PU_PD_SEL_2 0xfffe10bc
-#define PU_PD_SEL_3 0xfffe10c0
-#define PU_PD_SEL_4 0xfffe10c4
-
-/* Timer32K for 1610 and 1710*/
-#define OMAP_TIMER32K_BASE 0xFFFBC400
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
-
-/*
- * ----------------------------------------------------------------------------
- * MPUI interface
- * ----------------------------------------------------------------------------
- */
-#define MPUI_BASE (0xfffec900)
-#define MPUI_CTRL (MPUI_BASE + 0x0)
-#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
-#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
-#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
-#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
-#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
-#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
-#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
-
-/*
- * ----------------------------------------------------------------------------
- * LED Pulse Generator
- * ----------------------------------------------------------------------------
- */
-#define OMAP_LPG1_BASE 0xfffbd000
-#define OMAP_LPG2_BASE 0xfffbd800
-#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
-#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
-#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
-#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
-
-/*
- * ----------------------------------------------------------------------------
- * Pulse-Width Light
- * ----------------------------------------------------------------------------
- */
-#define OMAP_PWL_BASE 0xfffb5800
-#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
-#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
-
-/*
- * ---------------------------------------------------------------------------
- * Processor specific defines
- * ---------------------------------------------------------------------------
- */
-
-#include <plat/omap7xx.h>
-#include <plat/omap1510.h>
-#include <plat/omap16xx.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/ti81xx.h>
-#include <plat/am33xx.h>
-#include <plat/omap54xx.h>
-
-#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/plat-omap/include/plat/hdq1w.h
deleted file mode 100644
index 0c1efc846d8d..000000000000
--- a/arch/arm/plat-omap/include/plat/hdq1w.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Shared macros and function prototypes for the HDQ1W/1-wire IP block
- *
- * Copyright (C) 2012 Texas Instruments, Inc.
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- */
-#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
-#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
-
-#include <plat/omap_hwmod.h>
-
-/*
- * XXX A future cleanup patch should modify
- * drivers/w1/masters/omap_hdq.c to use these macros
- */
-#define HDQ_CTRL_STATUS_OFFSET 0x0c
-#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT 5
-
-
-extern int omap_hdq1w_reset(struct omap_hwmod *oh);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/plat-omap/include/plat/irda.h
deleted file mode 100644
index 40f60339d1c6..000000000000
--- a/arch/arm/plat-omap/include/plat/irda.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/irda.h
- *
- * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_IRDA_H
-#define ASMARM_ARCH_IRDA_H
-
-/* board specific transceiver capabilities */
-
-#define IR_SEL 1 /* Selects IrDA */
-#define IR_SIRMODE 2
-#define IR_FIRMODE 4
-#define IR_MIRMODE 8
-
-struct omap_irda_config {
- int transceiver_cap;
- int (*transceiver_mode)(struct device *dev, int mode);
- int (*select_irda)(struct device *dev, int state);
- int rx_channel;
- int tx_channel;
- unsigned long dest_start;
- unsigned long src_start;
- int tx_trigger;
- int rx_trigger;
- int mode;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs-44xx.h b/arch/arm/plat-omap/include/plat/irqs-44xx.h
deleted file mode 100644
index 518322c80116..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs-44xx.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * OMAP4 Interrupt lines definitions
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Santosh Shilimkar (santosh.shilimkar@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_IRQS_H
-
-/* OMAP44XX IRQs numbers definitions */
-#define OMAP44XX_IRQ_LOCALTIMER 29
-#define OMAP44XX_IRQ_LOCALWDT 30
-
-#define OMAP44XX_IRQ_GIC_START 32
-
-#define OMAP44XX_IRQ_PL310 (0 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI0 (1 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CTI1 (2 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ELM (4 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_1N (7 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SECURITY_EVENTS (8 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_DBG (9 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_L3_APP (10 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PRCM (11 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_0 (12 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_1 (13 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_2 (14 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SDMA_3 (15 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP4 (16 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP1 (17 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_MCU (18 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_CORE (19 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPMC (20 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GFX (21 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP2 (22 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCBSP3 (23 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ISS_5 (24 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DISPC (25 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MAIL_U0 (26 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_0 (27 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TESLA_MMU (28 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO1 (29 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO2 (30 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO3 (31 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO4 (32 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO5 (33 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPIO6 (34 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_USIM (35 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT3 (36 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT1 (37 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT2 (38 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT3 (39 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT4 (40 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT5 (41 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT6 (42 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT7 (43 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT8 (44 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT9 (45 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT10 (46 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT11 (47 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI4 (48 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_S (49 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FPKA_SINTREQUEST_S (50 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SHA1_P (51 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_RNG (52 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI1 (53 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C1 (56 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C2 (57 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HDQ (58 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC5 (59 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C3 (61 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_I2C4 (62 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_S (63 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES2_P (64 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI1 (65 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI2 (66 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P1 (67 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_P2 (68 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FDIF_3 (69 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART4 (70 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HSI_DMA (71 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART1 (72 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART2 (73 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UART3 (74 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_PBIAS (75 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_OHCI (76 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EHCI (77 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_TLL (78 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_S (79 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_WDT2 (80 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_S (81 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DES_P (82 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC1 (83 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_DSI2 (84 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_AES1_P (85 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC2 (86 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MPU_ICR (87 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_C2C_SSCM_1 (88 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB (89 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_FSUSB_SMI (90 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SPI3 (91 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_MC_N (92 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_HS_USB_DMA_N (93 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC3 (94 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_GPT12 (95 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MMC4 (96 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS1 (97 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SLIMBUS2 (98 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_ABE (99 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DUCATI_MMU (100 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DSS_HDMI (101 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SR_IVA (102 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_1 (103 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POSYNCITRPEND_0 (104 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_IVA_HD_POMBINTRPEND_0 (107 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AR (108 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCASP1_AX (109 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_1 (110 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_EMIF4_2 (111 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_MCPDM (112 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMM (113 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_DMIC (114 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_0 (115 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_1 (116 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_2 (117 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_CDMA_3 (118 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_SYS_2N (119 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_KBD_CTL (120 + OMAP44XX_IRQ_GIC_START)
-#define OMAP44XX_IRQ_UNIPRO1 (124 + OMAP44XX_IRQ_GIC_START)
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
deleted file mode 100644
index 37bbbbb981b2..000000000000
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/irqs.h
- *
- * Copyright (C) Greg Lonnon 2001
- * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
- * are different.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
-#define __ASM_ARCH_OMAP15XX_IRQS_H
-
-/* All OMAP4 specific defines are moved to irqs-44xx.h */
-#include "irqs-44xx.h"
-
-/*
- * IRQ numbers for interrupt handler 1
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- *
- */
-#define INT_CAMERA 1
-#define INT_FIQ 3
-#define INT_RTDX 6
-#define INT_DSP_MMU_ABORT 7
-#define INT_HOST 8
-#define INT_ABORT 9
-#define INT_BRIDGE_PRIV 13
-#define INT_GPIO_BANK1 14
-#define INT_UART3 15
-#define INT_TIMER3 16
-#define INT_DMA_CH0_6 19
-#define INT_DMA_CH1_7 20
-#define INT_DMA_CH2_8 21
-#define INT_DMA_CH3 22
-#define INT_DMA_CH4 23
-#define INT_DMA_CH5 24
-#define INT_DMA_LCD 25
-#define INT_TIMER1 26
-#define INT_WD_TIMER 27
-#define INT_BRIDGE_PUB 28
-#define INT_TIMER2 30
-#define INT_LCD_CTRL 31
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1510_IH2_IRQ 0
-#define INT_1510_RES2 2
-#define INT_1510_SPI_TX 4
-#define INT_1510_SPI_RX 5
-#define INT_1510_DSP_MAILBOX1 10
-#define INT_1510_DSP_MAILBOX2 11
-#define INT_1510_RES12 12
-#define INT_1510_LB_MMU 17
-#define INT_1510_RES18 18
-#define INT_1510_LOCAL_BUS 29
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 1
- */
-#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
-#define INT_1610_IH2_FIQ 2
-#define INT_1610_McBSP2_TX 4
-#define INT_1610_McBSP2_RX 5
-#define INT_1610_DSP_MAILBOX1 10
-#define INT_1610_DSP_MAILBOX2 11
-#define INT_1610_LCD_LINE 12
-#define INT_1610_GPTIMER1 17
-#define INT_1610_GPTIMER2 18
-#define INT_1610_SSR_FIFO_0 29
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 1
- */
-#define INT_7XX_IH2_FIQ 0
-#define INT_7XX_IH2_IRQ 1
-#define INT_7XX_USB_NON_ISO 2
-#define INT_7XX_USB_ISO 3
-#define INT_7XX_ICR 4
-#define INT_7XX_EAC 5
-#define INT_7XX_GPIO_BANK1 6
-#define INT_7XX_GPIO_BANK2 7
-#define INT_7XX_GPIO_BANK3 8
-#define INT_7XX_McBSP2TX 10
-#define INT_7XX_McBSP2RX 11
-#define INT_7XX_McBSP2RX_OVF 12
-#define INT_7XX_LCD_LINE 14
-#define INT_7XX_GSM_PROTECT 15
-#define INT_7XX_TIMER3 16
-#define INT_7XX_GPIO_BANK5 17
-#define INT_7XX_GPIO_BANK6 18
-#define INT_7XX_SPGIO_WR 29
-
-/*
- * IRQ numbers for interrupt handler 2
- *
- * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
- */
-#define IH2_BASE 32
-
-#define INT_KEYBOARD (1 + IH2_BASE)
-#define INT_uWireTX (2 + IH2_BASE)
-#define INT_uWireRX (3 + IH2_BASE)
-#define INT_I2C (4 + IH2_BASE)
-#define INT_MPUIO (5 + IH2_BASE)
-#define INT_USB_HHC_1 (6 + IH2_BASE)
-#define INT_McBSP3TX (10 + IH2_BASE)
-#define INT_McBSP3RX (11 + IH2_BASE)
-#define INT_McBSP1TX (12 + IH2_BASE)
-#define INT_McBSP1RX (13 + IH2_BASE)
-#define INT_UART1 (14 + IH2_BASE)
-#define INT_UART2 (15 + IH2_BASE)
-#define INT_BT_MCSI1TX (16 + IH2_BASE)
-#define INT_BT_MCSI1RX (17 + IH2_BASE)
-#define INT_SOSSI_MATCH (19 + IH2_BASE)
-#define INT_USB_W2FC (20 + IH2_BASE)
-#define INT_1WIRE (21 + IH2_BASE)
-#define INT_OS_TIMER (22 + IH2_BASE)
-#define INT_MMC (23 + IH2_BASE)
-#define INT_GAUGE_32K (24 + IH2_BASE)
-#define INT_RTC_TIMER (25 + IH2_BASE)
-#define INT_RTC_ALARM (26 + IH2_BASE)
-#define INT_MEM_STICK (27 + IH2_BASE)
-
-/*
- * OMAP-1510 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1510_DSP_MMU (28 + IH2_BASE)
-#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
-
-/*
- * OMAP-1610 specific IRQ numbers for interrupt handler 2
- */
-#define INT_1610_FAC (0 + IH2_BASE)
-#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
-#define INT_1610_USB_OTG (8 + IH2_BASE)
-#define INT_1610_SoSSI (9 + IH2_BASE)
-#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
-#define INT_1610_DSP_MMU (28 + IH2_BASE)
-#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
-#define INT_1610_STI (32 + IH2_BASE)
-#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
-#define INT_1610_GPTIMER3 (34 + IH2_BASE)
-#define INT_1610_GPTIMER4 (35 + IH2_BASE)
-#define INT_1610_GPTIMER5 (36 + IH2_BASE)
-#define INT_1610_GPTIMER6 (37 + IH2_BASE)
-#define INT_1610_GPTIMER7 (38 + IH2_BASE)
-#define INT_1610_GPTIMER8 (39 + IH2_BASE)
-#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
-#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
-#define INT_1610_MMC2 (42 + IH2_BASE)
-#define INT_1610_CF (43 + IH2_BASE)
-#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
-#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
-#define INT_1610_SPI (49 + IH2_BASE)
-#define INT_1610_DMA_CH6 (53 + IH2_BASE)
-#define INT_1610_DMA_CH7 (54 + IH2_BASE)
-#define INT_1610_DMA_CH8 (55 + IH2_BASE)
-#define INT_1610_DMA_CH9 (56 + IH2_BASE)
-#define INT_1610_DMA_CH10 (57 + IH2_BASE)
-#define INT_1610_DMA_CH11 (58 + IH2_BASE)
-#define INT_1610_DMA_CH12 (59 + IH2_BASE)
-#define INT_1610_DMA_CH13 (60 + IH2_BASE)
-#define INT_1610_DMA_CH14 (61 + IH2_BASE)
-#define INT_1610_DMA_CH15 (62 + IH2_BASE)
-#define INT_1610_NAND (63 + IH2_BASE)
-#define INT_1610_SHA1MD5 (91 + IH2_BASE)
-
-/*
- * OMAP-7xx specific IRQ numbers for interrupt handler 2
- */
-#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
-#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
-#define INT_7XX_CFCD (2 + IH2_BASE)
-#define INT_7XX_CFIREQ (3 + IH2_BASE)
-#define INT_7XX_I2C (4 + IH2_BASE)
-#define INT_7XX_PCC (5 + IH2_BASE)
-#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
-#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
-#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
-#define INT_7XX_VLYNQ (9 + IH2_BASE)
-#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
-#define INT_7XX_McBSP1TX (11 + IH2_BASE)
-#define INT_7XX_McBSP1RX (12 + IH2_BASE)
-#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
-#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
-#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
-#define INT_7XX_MCSI (16 + IH2_BASE)
-#define INT_7XX_uWireTX (17 + IH2_BASE)
-#define INT_7XX_uWireRX (18 + IH2_BASE)
-#define INT_7XX_SMC_CD (19 + IH2_BASE)
-#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
-#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
-#define INT_7XX_TIMER32K (22 + IH2_BASE)
-#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
-#define INT_7XX_UPLD (24 + IH2_BASE)
-#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
-#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
-#define INT_7XX_USB_GENI (29 + IH2_BASE)
-#define INT_7XX_USB_OTG (30 + IH2_BASE)
-#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
-#define INT_7XX_RNG (32 + IH2_BASE)
-#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
-#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
-#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
-#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
-#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
-#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
-#define INT_7XX_MPUIO (39 + IH2_BASE)
-#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
-#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
-#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
-#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
-#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
-#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
-#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
-#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
-#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
-#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
-#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
-#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
-#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
-#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
-#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
-#define INT_7XX_NAND (63 + IH2_BASE)
-
-#define INT_24XX_SYS_NIRQ 7
-#define INT_24XX_SDMA_IRQ0 12
-#define INT_24XX_SDMA_IRQ1 13
-#define INT_24XX_SDMA_IRQ2 14
-#define INT_24XX_SDMA_IRQ3 15
-#define INT_24XX_CAM_IRQ 24
-#define INT_24XX_DSS_IRQ 25
-#define INT_24XX_MAIL_U0_MPU 26
-#define INT_24XX_DSP_UMA 27
-#define INT_24XX_DSP_MMU 28
-#define INT_24XX_GPIO_BANK1 29
-#define INT_24XX_GPIO_BANK2 30
-#define INT_24XX_GPIO_BANK3 31
-#define INT_24XX_GPIO_BANK4 32
-#define INT_24XX_GPIO_BANK5 33
-#define INT_24XX_MAIL_U3_MPU 34
-#define INT_24XX_GPTIMER1 37
-#define INT_24XX_GPTIMER2 38
-#define INT_24XX_GPTIMER3 39
-#define INT_24XX_GPTIMER4 40
-#define INT_24XX_GPTIMER5 41
-#define INT_24XX_GPTIMER6 42
-#define INT_24XX_GPTIMER7 43
-#define INT_24XX_GPTIMER8 44
-#define INT_24XX_GPTIMER9 45
-#define INT_24XX_GPTIMER10 46
-#define INT_24XX_GPTIMER11 47
-#define INT_24XX_GPTIMER12 48
-#define INT_24XX_SHA1MD5 51
-#define INT_24XX_MCBSP4_IRQ_TX 54
-#define INT_24XX_MCBSP4_IRQ_RX 55
-#define INT_24XX_I2C1_IRQ 56
-#define INT_24XX_I2C2_IRQ 57
-#define INT_24XX_HDQ_IRQ 58
-#define INT_24XX_MCBSP1_IRQ_TX 59
-#define INT_24XX_MCBSP1_IRQ_RX 60
-#define INT_24XX_MCBSP2_IRQ_TX 62
-#define INT_24XX_MCBSP2_IRQ_RX 63
-#define INT_24XX_SPI1_IRQ 65
-#define INT_24XX_SPI2_IRQ 66
-#define INT_24XX_UART1_IRQ 72
-#define INT_24XX_UART2_IRQ 73
-#define INT_24XX_UART3_IRQ 74
-#define INT_24XX_USB_IRQ_GEN 75
-#define INT_24XX_USB_IRQ_NISO 76
-#define INT_24XX_USB_IRQ_ISO 77
-#define INT_24XX_USB_IRQ_HGEN 78
-#define INT_24XX_USB_IRQ_HSOF 79
-#define INT_24XX_USB_IRQ_OTG 80
-#define INT_24XX_MCBSP5_IRQ_TX 81
-#define INT_24XX_MCBSP5_IRQ_RX 82
-#define INT_24XX_MMC_IRQ 83
-#define INT_24XX_MMC2_IRQ 86
-#define INT_24XX_MCBSP3_IRQ_TX 89
-#define INT_24XX_MCBSP3_IRQ_RX 90
-#define INT_24XX_SPI3_IRQ 91
-
-#define INT_243X_MCBSP2_IRQ 16
-#define INT_243X_MCBSP3_IRQ 17
-#define INT_243X_MCBSP4_IRQ 18
-#define INT_243X_MCBSP5_IRQ 19
-#define INT_243X_MCBSP1_IRQ 64
-#define INT_243X_HS_USB_MC 92
-#define INT_243X_HS_USB_DMA 93
-#define INT_243X_CARKIT_IRQ 94
-
-#define INT_34XX_BENCH_MPU_EMUL 3
-#define INT_34XX_ST_MCBSP2_IRQ 4
-#define INT_34XX_ST_MCBSP3_IRQ 5
-#define INT_34XX_SSM_ABORT_IRQ 6
-#define INT_34XX_SYS_NIRQ 7
-#define INT_34XX_D2D_FW_IRQ 8
-#define INT_34XX_L3_DBG_IRQ 9
-#define INT_34XX_L3_APP_IRQ 10
-#define INT_34XX_PRCM_MPU_IRQ 11
-#define INT_34XX_MCBSP1_IRQ 16
-#define INT_34XX_MCBSP2_IRQ 17
-#define INT_34XX_GPMC_IRQ 20
-#define INT_34XX_MCBSP3_IRQ 22
-#define INT_34XX_MCBSP4_IRQ 23
-#define INT_34XX_CAM_IRQ 24
-#define INT_34XX_MCBSP5_IRQ 27
-#define INT_34XX_GPIO_BANK1 29
-#define INT_34XX_GPIO_BANK2 30
-#define INT_34XX_GPIO_BANK3 31
-#define INT_34XX_GPIO_BANK4 32
-#define INT_34XX_GPIO_BANK5 33
-#define INT_34XX_GPIO_BANK6 34
-#define INT_34XX_USIM_IRQ 35
-#define INT_34XX_WDT3_IRQ 36
-#define INT_34XX_SPI4_IRQ 48
-#define INT_34XX_SHA1MD52_IRQ 49
-#define INT_34XX_FPKA_READY_IRQ 50
-#define INT_34XX_SHA1MD51_IRQ 51
-#define INT_34XX_RNG_IRQ 52
-#define INT_34XX_I2C3_IRQ 61
-#define INT_34XX_FPKA_ERROR_IRQ 64
-#define INT_34XX_PBIAS_IRQ 75
-#define INT_34XX_OHCI_IRQ 76
-#define INT_34XX_EHCI_IRQ 77
-#define INT_34XX_TLL_IRQ 78
-#define INT_34XX_PARTHASH_IRQ 79
-#define INT_34XX_MMC3_IRQ 94
-#define INT_34XX_GPT12_IRQ 95
-
-#define INT_36XX_UART4_IRQ 80
-
-#define INT_35XX_HECC0_IRQ 24
-#define INT_35XX_HECC1_IRQ 28
-#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
-#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
-#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
-#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
-#define INT_35XX_USBOTG_IRQ 71
-#define INT_35XX_UART4_IRQ 84
-#define INT_35XX_CCDC_VD0_IRQ 88
-#define INT_35XX_CCDC_VD1_IRQ 92
-#define INT_35XX_CCDC_VD2_IRQ 93
-
-/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
- * 16 MPUIO lines */
-#define OMAP_MAX_GPIO_LINES 192
-#define IH_GPIO_BASE (128 + IH2_BASE)
-#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
-#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
-
-/* External FPGA handles interrupts on Innovator boards */
-#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
-#ifdef CONFIG_MACH_OMAP_INNOVATOR
-#define OMAP_FPGA_NR_IRQS 24
-#else
-#define OMAP_FPGA_NR_IRQS 0
-#endif
-#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
-
-/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
-#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define TWL4030_BASE_NR_IRQS 8
-#define TWL4030_PWR_NR_IRQS 8
-#else
-#define TWL4030_BASE_NR_IRQS 0
-#define TWL4030_PWR_NR_IRQS 0
-#endif
-#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
-#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
-#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
-
-/* External TWL4030 gpio interrupts are optional */
-#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
-#ifdef CONFIG_GPIO_TWL4030
-#define TWL4030_GPIO_NR_IRQS 18
-#else
-#define TWL4030_GPIO_NR_IRQS 0
-#endif
-#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
-
-#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
-#ifdef CONFIG_TWL4030_CORE
-#define TWL6030_BASE_NR_IRQS 20
-#else
-#define TWL6030_BASE_NR_IRQS 0
-#endif
-#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
-
-#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
-#ifdef CONFIG_TWL6040_CODEC
-#define TWL6040_CODEC_NR_IRQS 6
-#else
-#define TWL6040_CODEC_NR_IRQS 0
-#endif
-#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
-
-/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
-#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
-#else
-#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
-#endif
-
-/* GPMC related */
-#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS 8
-#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
-
-/* PRCM IRQ handler */
-#ifdef CONFIG_ARCH_OMAP2PLUS
-#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
-#define OMAP_PRCM_NR_IRQS 64
-#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
-#else
-#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
-#endif
-
-#define NR_IRQS OMAP_PRCM_IRQ_END
-
-#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
-
-#define INTCPS_NR_MIR_REGS 3
-#define INTCPS_NR_IRQS 96
-
-#include <mach/hardware.h>
-
-#ifdef CONFIG_FIQ
-#define FIQ_START 1024
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
deleted file mode 100644
index a6b21eddb212..000000000000
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/keypad.h
- *
- * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_KEYPAD_H
-#define ASMARM_ARCH_KEYPAD_H
-
-#ifndef CONFIG_ARCH_OMAP1
-#warning Please update the board to use matrix-keypad driver
-#define omap_readw(reg) 0
-#define omap_writew(val, reg) do {} while (0)
-#endif
-#include <linux/input/matrix_keypad.h>
-
-struct omap_kp_platform_data {
- int rows;
- int cols;
- const struct matrix_keymap_data *keymap_data;
- bool rep;
- unsigned long delay;
- bool dbounce;
- /* specific to OMAP242x*/
- unsigned int *row_gpios;
- unsigned int *col_gpios;
-};
-
-/* Group (0..3) -- when multiple keys are pressed, only the
- * keys pressed in the same group are considered as pressed. This is
- * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. Two free bits, not used by neither row/col nor keynum,
- * must be available for use as group bits. The below GROUP_SHIFT
- * macro definition is based on some prior knowledge of the
- * matrix_keypad defined KEY() macro internals.
- */
-#define GROUP_SHIFT 14
-#define GROUP_0 (0 << GROUP_SHIFT)
-#define GROUP_1 (1 << GROUP_SHIFT)
-#define GROUP_2 (2 << GROUP_SHIFT)
-#define GROUP_3 (3 << GROUP_SHIFT)
-#define GROUP_MASK GROUP_3
-#if KEY_MAX & GROUP_MASK
-#error Group bits in conflict with keynum bits
-#endif
-
-
-#endif
-
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
deleted file mode 100644
index b8b5641379b0..000000000000
--- a/arch/arm/plat-omap/include/plat/l3_2xxx.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Sumit Semwal
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
-
-/* L3 CONNIDs */
-/* Display Sub system (DSS) */
-#define OMAP2_L3_CORE_FW_CONNID_DSS 8
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
deleted file mode 100644
index cde1938c5f82..000000000000
--- a/arch/arm/plat-omap/include/plat/l3_3xxx.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Sumit Semwal
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
-
-/* L3 Initiator IDs */
-/* Display Sub system (DSS) */
-#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
deleted file mode 100644
index 3f39cf8a35c6..000000000000
--- a/arch/arm/plat-omap/include/plat/l4_2xxx.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- * Sumit Semwal
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
-
-/* L4 CORE */
-/* Display Sub system (DSS) */
-#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
-#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
-#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
-#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
-#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
deleted file mode 100644
index 881a858b1ffc..000000000000
--- a/arch/arm/plat-omap/include/plat/l4_3xxx.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
-
-/* L4 CORE */
-#define OMAP3_L4_CORE_FW_I2C1_REGION 21
-#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22
-#define OMAP3_L4_CORE_FW_I2C2_REGION 23
-#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24
-#define OMAP3_L4_CORE_FW_I2C3_REGION 73
-#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
-
-/* Display Sub system (DSS) */
-#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2
-
-#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104
-#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3
-#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4
-#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4
-#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5
-#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6
-#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7
-#endif
diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
deleted file mode 100644
index 8e52c6572281..000000000000
--- a/arch/arm/plat-omap/include/plat/lcd_mipid.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __LCD_MIPID_H
-#define __LCD_MIPID_H
-
-enum mipid_test_num {
- MIPID_TEST_RGB_LINES,
-};
-
-enum mipid_test_result {
- MIPID_TEST_SUCCESS,
- MIPID_TEST_INVALID,
- MIPID_TEST_FAILED,
-};
-
-#ifdef __KERNEL__
-
-struct mipid_platform_data {
- int nreset_gpio;
- int data_lines;
-
- void (*shutdown)(struct mipid_platform_data *pdata);
- void (*set_bklight_level)(struct mipid_platform_data *pdata,
- int level);
- int (*get_bklight_level)(struct mipid_platform_data *pdata);
- int (*get_bklight_max)(struct mipid_platform_data *pdata);
-};
-
-#endif
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
deleted file mode 100644
index 18814127809a..000000000000
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/mcbsp.h
- *
- * Defines for Multi-Channel Buffered Serial Port
- *
- * Copyright (C) 2002 RidgeRun, Inc.
- * Author: Steve Johnson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __ASM_ARCH_OMAP_MCBSP_H
-#define __ASM_ARCH_OMAP_MCBSP_H
-
-#include <linux/spinlock.h>
-#include <linux/clk.h>
-
-#define MCBSP_CONFIG_TYPE2 0x2
-#define MCBSP_CONFIG_TYPE3 0x3
-#define MCBSP_CONFIG_TYPE4 0x4
-
-/* Platform specific configuration */
-struct omap_mcbsp_ops {
- void (*request)(unsigned int);
- void (*free)(unsigned int);
-};
-
-struct omap_mcbsp_platform_data {
- struct omap_mcbsp_ops *ops;
- u16 buffer_size;
- u8 reg_size;
- u8 reg_step;
-
- /* McBSP platform and instance specific features */
- bool has_wakeup; /* Wakeup capability */
- bool has_ccr; /* Transceiver has configuration control registers */
- int (*enable_st_clock)(unsigned int, bool);
- int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
- int (*mux_signal)(struct device *dev, const char *signal, const char *src);
-};
-
-/**
- * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
- * @sidetone: name of the sidetone device
- */
-struct omap_mcbsp_dev_attr {
- const char *sidetone;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
deleted file mode 100644
index a357eb26bd25..000000000000
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _OMAP2_MCSPI_H
-#define _OMAP2_MCSPI_H
-
-#define OMAP2_MCSPI_REV 0
-#define OMAP3_MCSPI_REV 1
-#define OMAP4_MCSPI_REV 2
-
-#define OMAP4_MCSPI_REG_OFFSET 0x100
-
-struct omap2_mcspi_platform_config {
- unsigned short num_cs;
- unsigned int regs_offset;
-};
-
-struct omap2_mcspi_dev_attr {
- unsigned short num_chipselect;
-};
-
-struct omap2_mcspi_device_config {
- unsigned turbo_mode:1;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index eb3e4d555343..8b4e4f2da2f5 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -15,7 +15,6 @@
#include <linux/device.h>
#include <linux/mmc/host.h>
-#include <plat/board.h>
#include <plat/omap_hwmod.h>
#define OMAP15XX_NR_MMC 1
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
deleted file mode 100644
index 323948959200..000000000000
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/mux.h
- *
- * Table of the Omap register configurations for the FUNC_MUX and
- * PULL_DWN combinations.
- *
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * NOTE: Please use the following naming style for new pin entries.
- * For example, W8_1610_MMC2_DAT0, where:
- * - W8 = ball
- * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
- * - MMC2_DAT0 = function
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
-#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
-
-#ifdef CONFIG_OMAP_MUX_DEBUG
-#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
- .mux_reg = FUNC_MUX_CTRL_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
- .pull_reg = PULL_DWN_CTRL_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
-#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
- .pu_pd_reg = PU_PD_SEL_##reg, \
- .pu_pd_val = status,
-
-#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
- .mux_reg = OMAP7XX_IO_CONF_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
- .pull_reg = OMAP7XX_IO_CONF_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
-#else
-
-#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
-#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
- .pu_pd_val = status,
-
-#define MUX_REG_7XX(reg, mode_offset, mode) \
- .mux_reg = OMAP7XX_IO_CONF_##reg, \
- .mask_offset = mode_offset, \
- .mask = mode,
-
-#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
- .pull_bit = bit, \
- .pull_val = status,
-
-#endif /* CONFIG_OMAP_MUX_DEBUG */
-
-#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
- pull_reg, pull_bit, pull_status, \
- pu_pd_reg, pu_pd_status, debug_status) \
-{ \
- .name = desc, \
- .debug = debug_status, \
- MUX_REG(mux_reg, mode_offset, mode) \
- PULL_REG(pull_reg, pull_bit, pull_status) \
- PU_PD_REG(pu_pd_reg, pu_pd_status) \
-},
-
-
-/*
- * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
- * not the FUNC_MUX_CTRL_x regs from hardware.h
- * - for pull-up/down, only has one enable bit which is is in the same register
- * as mux config
- */
-#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
- pull_bit, pull_status, debug_status)\
-{ \
- .name = desc, \
- .debug = debug_status, \
- MUX_REG_7XX(mux_reg, mode_offset, mode) \
- PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
- PU_PD_REG(NA, 0) \
-},
-
-struct pin_config {
- char *name;
- const unsigned int mux_reg;
- unsigned char debug;
-
- const unsigned char mask_offset;
- const unsigned char mask;
-
- const char *pull_name;
- const unsigned int pull_reg;
- const unsigned char pull_val;
- const unsigned char pull_bit;
-
- const char *pu_pd_name;
- const unsigned int pu_pd_reg;
- const unsigned char pu_pd_val;
-
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
- const char *mux_reg_name;
-#endif
-
-};
-
-enum omap7xx_index {
- /* OMAP 730 keyboard */
- E2_7XX_KBR0,
- J7_7XX_KBR1,
- E1_7XX_KBR2,
- F3_7XX_KBR3,
- D2_7XX_KBR4,
- C2_7XX_KBC0,
- D3_7XX_KBC1,
- E4_7XX_KBC2,
- F4_7XX_KBC3,
- E3_7XX_KBC4,
-
- /* USB */
- AA17_7XX_USB_DM,
- W16_7XX_USB_PU_EN,
- W17_7XX_USB_VBUSI,
- W18_7XX_USB_DMCK_OUT,
- W19_7XX_USB_DCRST,
-
- /* MMC */
- MMC_7XX_CMD,
- MMC_7XX_CLK,
- MMC_7XX_DAT0,
-
- /* I2C */
- I2C_7XX_SCL,
- I2C_7XX_SDA,
-
- /* SPI */
- SPI_7XX_1,
- SPI_7XX_2,
- SPI_7XX_3,
- SPI_7XX_4,
- SPI_7XX_5,
- SPI_7XX_6,
-
- /* UART */
- UART_7XX_1,
- UART_7XX_2,
-};
-
-enum omap1xxx_index {
- /* UART1 (BT_UART_GATING)*/
- UART1_TX = 0,
- UART1_RTS,
-
- /* UART2 (COM_UART_GATING)*/
- UART2_TX,
- UART2_RX,
- UART2_CTS,
- UART2_RTS,
-
- /* UART3 (GIGA_UART_GATING) */
- UART3_TX,
- UART3_RX,
- UART3_CTS,
- UART3_RTS,
- UART3_CLKREQ,
- UART3_BCLK, /* 12MHz clock out */
- Y15_1610_UART3_RTS,
-
- /* PWT & PWL */
- PWT,
- PWL,
-
- /* USB master generic */
- R18_USB_VBUS,
- R18_1510_USB_GPIO0,
- W4_USB_PUEN,
- W4_USB_CLKO,
- W4_USB_HIGHZ,
- W4_GPIO58,
-
- /* USB1 master */
- USB1_SUSP,
- USB1_SEO,
- W13_1610_USB1_SE0,
- USB1_TXEN,
- USB1_TXD,
- USB1_VP,
- USB1_VM,
- USB1_RCV,
- USB1_SPEED,
- R13_1610_USB1_SPEED,
- R13_1710_USB1_SE0,
-
- /* USB2 master */
- USB2_SUSP,
- USB2_VP,
- USB2_TXEN,
- USB2_VM,
- USB2_RCV,
- USB2_SEO,
- USB2_TXD,
-
- /* OMAP-1510 GPIO */
- R18_1510_GPIO0,
- R19_1510_GPIO1,
- M14_1510_GPIO2,
-
- /* OMAP1610 GPIO */
- P18_1610_GPIO3,
- Y15_1610_GPIO17,
-
- /* OMAP-1710 GPIO */
- R18_1710_GPIO0,
- V2_1710_GPIO10,
- N21_1710_GPIO14,
- W15_1710_GPIO40,
-
- /* MPUIO */
- MPUIO2,
- N15_1610_MPUIO2,
- MPUIO4,
- MPUIO5,
- T20_1610_MPUIO5,
- W11_1610_MPUIO6,
- V10_1610_MPUIO7,
- W11_1610_MPUIO9,
- V10_1610_MPUIO10,
- W10_1610_MPUIO11,
- E20_1610_MPUIO13,
- U20_1610_MPUIO14,
- E19_1610_MPUIO15,
-
- /* MCBSP2 */
- MCBSP2_CLKR,
- MCBSP2_CLKX,
- MCBSP2_DR,
- MCBSP2_DX,
- MCBSP2_FSR,
- MCBSP2_FSX,
-
- /* MCBSP3 */
- MCBSP3_CLKX,
-
- /* Misc ballouts */
- BALLOUT_V8_ARMIO3,
- N20_HDQ,
-
- /* OMAP-1610 MMC2 */
- W8_1610_MMC2_DAT0,
- V8_1610_MMC2_DAT1,
- W15_1610_MMC2_DAT2,
- R10_1610_MMC2_DAT3,
- Y10_1610_MMC2_CLK,
- Y8_1610_MMC2_CMD,
- V9_1610_MMC2_CMDDIR,
- V5_1610_MMC2_DATDIR0,
- W19_1610_MMC2_DATDIR1,
- R18_1610_MMC2_CLKIN,
-
- /* OMAP-1610 External Trace Interface */
- M19_1610_ETM_PSTAT0,
- L15_1610_ETM_PSTAT1,
- L18_1610_ETM_PSTAT2,
- L19_1610_ETM_D0,
- J19_1610_ETM_D6,
- J18_1610_ETM_D7,
-
- /* OMAP16XX GPIO */
- P20_1610_GPIO4,
- V9_1610_GPIO7,
- W8_1610_GPIO9,
- N20_1610_GPIO11,
- N19_1610_GPIO13,
- P10_1610_GPIO22,
- V5_1610_GPIO24,
- AA20_1610_GPIO_41,
- W19_1610_GPIO48,
- M7_1610_GPIO62,
- V14_16XX_GPIO37,
- R9_16XX_GPIO18,
- L14_16XX_GPIO49,
-
- /* OMAP-1610 uWire */
- V19_1610_UWIRE_SCLK,
- U18_1610_UWIRE_SDI,
- W21_1610_UWIRE_SDO,
- N14_1610_UWIRE_CS0,
- P15_1610_UWIRE_CS3,
- N15_1610_UWIRE_CS1,
-
- /* OMAP-1610 SPI */
- U19_1610_SPIF_SCK,
- U18_1610_SPIF_DIN,
- P20_1610_SPIF_DIN,
- W21_1610_SPIF_DOUT,
- R18_1610_SPIF_DOUT,
- N14_1610_SPIF_CS0,
- N15_1610_SPIF_CS1,
- T19_1610_SPIF_CS2,
- P15_1610_SPIF_CS3,
-
- /* OMAP-1610 Flash */
- L3_1610_FLASH_CS2B_OE,
- M8_1610_FLASH_CS2B_WE,
-
- /* First MMC */
- MMC_CMD,
- MMC_DAT1,
- MMC_DAT2,
- MMC_DAT0,
- MMC_CLK,
- MMC_DAT3,
-
- /* OMAP-1710 MMC CMDDIR and DATDIR0 */
- M15_1710_MMC_CLKI,
- P19_1710_MMC_CMDDIR,
- P20_1710_MMC_DATDIR0,
-
- /* OMAP-1610 USB0 alternate pin configuration */
- W9_USB0_TXEN,
- AA9_USB0_VP,
- Y5_USB0_RCV,
- R9_USB0_VM,
- V6_USB0_TXD,
- W5_USB0_SE0,
- V9_USB0_SPEED,
- V9_USB0_SUSP,
-
- /* USB2 */
- W9_USB2_TXEN,
- AA9_USB2_VP,
- Y5_USB2_RCV,
- R9_USB2_VM,
- V6_USB2_TXD,
- W5_USB2_SE0,
-
- /* 16XX UART */
- R13_1610_UART1_TX,
- V14_16XX_UART1_RX,
- R14_1610_UART1_CTS,
- AA15_1610_UART1_RTS,
- R9_16XX_UART2_RX,
- L14_16XX_UART3_RX,
-
- /* I2C OMAP-1610 */
- I2C_SCL,
- I2C_SDA,
-
- /* Keypad */
- F18_1610_KBC0,
- D20_1610_KBC1,
- D19_1610_KBC2,
- E18_1610_KBC3,
- C21_1610_KBC4,
- G18_1610_KBR0,
- F19_1610_KBR1,
- H14_1610_KBR2,
- E20_1610_KBR3,
- E19_1610_KBR4,
- N19_1610_KBR5,
-
- /* Power management */
- T20_1610_LOW_PWR,
-
- /* MCLK Settings */
- V5_1710_MCLK_ON,
- V5_1710_MCLK_OFF,
- R10_1610_MCLK_ON,
- R10_1610_MCLK_OFF,
-
- /* CompactFlash controller */
- P11_1610_CF_CD2,
- R11_1610_CF_IOIS16,
- V10_1610_CF_IREQ,
- W10_1610_CF_RESET,
- W11_1610_CF_CD1,
-
- /* parallel camera */
- J15_1610_CAM_LCLK,
- J18_1610_CAM_D7,
- J19_1610_CAM_D6,
- J14_1610_CAM_D5,
- K18_1610_CAM_D4,
- K19_1610_CAM_D3,
- K15_1610_CAM_D2,
- K14_1610_CAM_D1,
- L19_1610_CAM_D0,
- L18_1610_CAM_VS,
- L15_1610_CAM_HS,
- M19_1610_CAM_RSTZ,
- Y15_1610_CAM_OUTCLK,
-
- /* serial camera */
- H19_1610_CAM_EXCLK,
- Y12_1610_CCP_CLKP,
- W13_1610_CCP_CLKM,
- W14_1610_CCP_DATAP,
- Y14_1610_CCP_DATAM,
-
-};
-
-struct omap_mux_cfg {
- struct pin_config *pins;
- unsigned long size;
- int (*cfg_reg)(const struct pin_config *cfg);
-};
-
-#ifdef CONFIG_OMAP_MUX
-/* setup pin muxing in Linux */
-extern int omap1_mux_init(void);
-extern int omap_mux_register(struct omap_mux_cfg *);
-extern int omap_cfg_reg(unsigned long reg_cfg);
-#else
-/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
-static inline int omap1_mux_init(void) { return 0; }
-static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
-#endif
-
-extern int omap2_mux_init(void);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
deleted file mode 100644
index 67fc5060183e..000000000000
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/nand.h
- *
- * Copyright (C) 2006 Micron Technology Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <plat/gpmc.h>
-#include <linux/mtd/partitions.h>
-
-enum nand_io {
- NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
- NAND_OMAP_POLLED, /* polled mode, without prefetch */
- NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
- NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
-};
-
-struct omap_nand_platform_data {
- int cs;
- struct mtd_partition *parts;
- struct gpmc_timings *gpmc_t;
- int nr_parts;
- bool dev_ready;
- int gpmc_irq;
- enum nand_io xfer_type;
- unsigned long phys_base;
- int devsize;
- enum omap_ecc ecc_opt;
-};
-
-/* minimum size for IO mapping */
-#define NAND_IO_SIZE 4
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern int gpmc_nand_init(struct omap_nand_platform_data *d);
-#else
-static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
-{
- return 0;
-}
-#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index a531149823bb..f4a4cd014795 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -21,8 +21,6 @@
#include <linux/device.h>
#include <linux/pm_qos.h>
-#include <plat/mux.h>
-
#define DRIVER_NAME "omap_uart"
/*
@@ -54,7 +52,7 @@
#define OMAP_UART_DMA_CH_FREE -1
-#define OMAP_MAX_HSUART_PORTS 4
+#define OMAP_MAX_HSUART_PORTS 6
#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
deleted file mode 100644
index d24004668138..000000000000
--- a/arch/arm/plat-omap/include/plat/omap1510.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap1510.h
- *
- * Hardware definitions for TI OMAP1510 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP15XX_H
-#define __ASM_ARCH_OMAP15XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP1510_DSP_BASE 0xE0000000
-#define OMAP1510_DSP_SIZE 0x28000
-#define OMAP1510_DSP_START 0xE0000000
-
-#define OMAP1510_DSPREG_BASE 0xE1000000
-#define OMAP1510_DSPREG_SIZE SZ_128K
-#define OMAP1510_DSPREG_START 0xE1000000
-
-#define OMAP1510_DSP_MMU_BASE (0xfffed200)
-
-#endif /* __ASM_ARCH_OMAP15XX_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
deleted file mode 100644
index e69e1d857b45..000000000000
--- a/arch/arm/plat-omap/include/plat/omap16xx.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap16xx.h
- *
- * Hardware definitions for TI OMAP1610/5912/1710 processors.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP16XX_H
-#define __ASM_ARCH_OMAP16XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP16XX_DSP_BASE 0xE0000000
-#define OMAP16XX_DSP_SIZE 0x28000
-#define OMAP16XX_DSP_START 0xE0000000
-
-#define OMAP16XX_DSPREG_BASE 0xE1000000
-#define OMAP16XX_DSPREG_SIZE SZ_128K
-#define OMAP16XX_DSPREG_START 0xE1000000
-
-#define OMAP16XX_SEC_BASE 0xFFFE4000
-#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
-#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
-#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
-
-/*
- * ---------------------------------------------------------------------------
- * Interrupts
- * ---------------------------------------------------------------------------
- */
-#define OMAP_IH2_0_BASE (0xfffe0000)
-#define OMAP_IH2_1_BASE (0xfffe0100)
-#define OMAP_IH2_2_BASE (0xfffe0200)
-#define OMAP_IH2_3_BASE (0xfffe0300)
-
-#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
-#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
-#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
-#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
-#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
-#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
-#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
-
-#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
-#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
-#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
-#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
-#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
-#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
-#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
-
-#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
-#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
-#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
-#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
-#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
-#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
-#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
-
-#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
-#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
-#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
-#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
-#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
-#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
-#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
-
-/*
- * ----------------------------------------------------------------------------
- * Clocks
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
-
-/*
- * ----------------------------------------------------------------------------
- * Pin configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
-#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
-#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
-
-/*
- * ----------------------------------------------------------------------------
- * System control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP1610_RESET_CONTROL 0xfffe1140
-
-/*
- * ---------------------------------------------------------------------------
- * TIPB bus interface
- * ---------------------------------------------------------------------------
- */
-#define TIPB_SWITCH_BASE (0xfffbc800)
-#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
-
-/* UART3 Registers Mapping through MPU bus */
-#define UART3_RHR (OMAP1_UART3_BASE + 0)
-#define UART3_THR (OMAP1_UART3_BASE + 0)
-#define UART3_DLL (OMAP1_UART3_BASE + 0)
-#define UART3_IER (OMAP1_UART3_BASE + 4)
-#define UART3_DLH (OMAP1_UART3_BASE + 4)
-#define UART3_IIR (OMAP1_UART3_BASE + 8)
-#define UART3_FCR (OMAP1_UART3_BASE + 8)
-#define UART3_EFR (OMAP1_UART3_BASE + 8)
-#define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
-#define UART3_MCR (OMAP1_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
-#define UART3_LSR (OMAP1_UART3_BASE + 0x14)
-#define UART3_TCR (OMAP1_UART3_BASE + 0x18)
-#define UART3_MSR (OMAP1_UART3_BASE + 0x18)
-#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
-#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
-#define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
-#define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
-#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
-#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
-#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
-#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
-#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
-#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
-#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
-#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
-#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
-#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
-#define UART3_BLR (OMAP1_UART3_BASE + 0x38)
-#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
-#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
-#define UART3_SCR (OMAP1_UART3_BASE + 0x40)
-#define UART3_SSR (OMAP1_UART3_BASE + 0x44)
-#define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
-#define UART3_MVR (OMAP1_UART3_BASE + 0x50)
-
-/*
- * ---------------------------------------------------------------------------
- * Watchdog timer
- * ---------------------------------------------------------------------------
- */
-
-/* 32-bit Watchdog timer in OMAP 16XX */
-#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
-#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
-#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
-#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
-#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
-#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
-#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
-#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
-#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
-#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
-
-#define WCLR_PRE_SHIFT 5
-#define WCLR_PTV_SHIFT 2
-
-#define WWPS_W_PEND_WSPR (1 << 4)
-#define WWPS_W_PEND_WTGR (1 << 3)
-#define WWPS_W_PEND_WLDR (1 << 2)
-#define WWPS_W_PEND_WCRR (1 << 1)
-#define WWPS_W_PEND_WCLR (1 << 0)
-
-#define WSPR_ENABLE_0 (0x0000bbbb)
-#define WSPR_ENABLE_1 (0x00004444)
-#define WSPR_DISABLE_0 (0x0000aaaa)
-#define WSPR_DISABLE_1 (0x00005555)
-
-#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
-#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
-
-#endif /* __ASM_ARCH_OMAP16XX_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
deleted file mode 100644
index 92df9e27cc5c..000000000000
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/omap24xx.h
- *
- * This file contains the processor specific definitions
- * of the TI OMAP24XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_OMAP2_H
-#define __ASM_ARCH_OMAP2_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers. Note also that some of these defines are needed
- * for omap1 to compile without adding ifdefs.
- */
-
-#define L4_24XX_BASE 0x48000000
-#define L4_WK_243X_BASE 0x49000000
-#define L3_24XX_BASE 0x68000000
-
-/* interrupt controller */
-#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
-#define OMAP24XX_IVA_INTC_BASE 0x40000000
-
-#define OMAP242X_CTRL_BASE L4_24XX_BASE
-#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
-#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
-#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
-#define OMAP2420_SMS_BASE 0x68008000
-#define OMAP2420_GPMC_BASE 0x6800a000
-
-#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
-#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
-#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
-
-#define OMAP243X_SMS_BASE 0x6C000000
-#define OMAP243X_SDRC_BASE 0x6D000000
-#define OMAP243X_GPMC_BASE 0x6E000000
-#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
-#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
-#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
-
-/* DSP SS */
-#define OMAP2420_DSP_BASE 0x58000000
-#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
-#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
-#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
-
-#define OMAP243X_DSP_BASE 0x5C000000
-#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
-#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
-
-/* Mailbox */
-#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
-
-/* Camera */
-#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
-
-/* Security */
-#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
-#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
-#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
-#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
-#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
-#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
-
-#endif /* __ASM_ARCH_OMAP2_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
deleted file mode 100644
index 0d818acf3917..000000000000
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/omap34xx.h
- *
- * This file contains the processor specific definitions of the TI OMAP34XX.
- *
- * Copyright (C) 2007 Texas Instruments.
- * Copyright (C) 2007 Nokia Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_OMAP3_H
-#define __ASM_ARCH_OMAP3_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers.
- */
-
-#define L4_34XX_BASE 0x48000000
-#define L4_WK_34XX_BASE 0x48300000
-#define L4_PER_34XX_BASE 0x49000000
-#define L4_EMU_34XX_BASE 0x54000000
-#define L3_34XX_BASE 0x68000000
-
-#define L4_WK_AM33XX_BASE 0x44C00000
-
-#define OMAP3430_32KSYNCT_BASE 0x48320000
-#define OMAP3430_CM_BASE 0x48004800
-#define OMAP3430_PRM_BASE 0x48306800
-#define OMAP343X_SMS_BASE 0x6C000000
-#define OMAP343X_SDRC_BASE 0x6D000000
-#define OMAP34XX_GPMC_BASE 0x6E000000
-#define OMAP343X_SCM_BASE 0x48002000
-#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
-
-#define OMAP34XX_IC_BASE 0x48200000
-
-#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
-#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
-#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
-#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
-#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
-#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
-#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
-#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
-#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
-#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
-#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800)
-#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970)
-#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0)
-#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00)
-#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70)
-#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0)
-
-#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
-#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
-#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
-#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
-#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
-#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
-#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
-#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
-#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
-#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
-#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
-#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
-#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
-#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
-#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
-#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
-
-#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
-#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
-#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
-#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
-#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
-#define OMAP34XX_SR1_BASE 0x480C9000
-#define OMAP34XX_SR2_BASE 0x480CB000
-
-#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
-
-/* Security */
-#define OMAP34XX_SEC_BASE (L4_34XX_BASE + 0xA0000)
-#define OMAP34XX_SEC_SHA1MD5_BASE (OMAP34XX_SEC_BASE + 0x23000)
-#define OMAP34XX_SEC_AES_BASE (OMAP34XX_SEC_BASE + 0x25000)
-
-#endif /* __ASM_ARCH_OMAP3_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
deleted file mode 100644
index 8ad0a377a54b..000000000000
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
-#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
-
-extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
- struct omap_board_data *);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
deleted file mode 100644
index c0d478e55c84..000000000000
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*:
- * Address mappings and base address for OMAP4 interconnects
- * and peripherals.
- *
- * Copyright (C) 2009 Texas Instruments
- *
- * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_OMAP44XX_H
-#define __ASM_ARCH_OMAP44XX_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers.
- */
-#define L4_44XX_BASE 0x4a000000
-#define L4_WK_44XX_BASE 0x4a300000
-#define L4_PER_44XX_BASE 0x48000000
-#define L4_EMU_44XX_BASE 0x54000000
-#define L3_44XX_BASE 0x44000000
-#define OMAP44XX_EMIF1_BASE 0x4c000000
-#define OMAP44XX_EMIF2_BASE 0x4d000000
-#define OMAP44XX_DMM_BASE 0x4e000000
-#define OMAP4430_32KSYNCT_BASE 0x4a304000
-#define OMAP4430_CM1_BASE 0x4a004000
-#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
-#define OMAP4430_CM2_BASE 0x4a008000
-#define OMAP4430_PRM_BASE 0x4a306000
-#define OMAP4430_PRCM_MPU_BASE 0x48243000
-#define OMAP44XX_GPMC_BASE 0x50000000
-#define OMAP443X_SCM_BASE 0x4a002000
-#define OMAP443X_CTRL_BASE 0x4a100000
-#define OMAP44XX_IC_BASE 0x48200000
-#define OMAP44XX_IVA_INTC_BASE 0x40000000
-#define IRQ_SIR_IRQ 0x0040
-#define OMAP44XX_GIC_DIST_BASE 0x48241000
-#define OMAP44XX_GIC_CPU_BASE 0x48240100
-#define OMAP44XX_SCU_BASE 0x48240000
-#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
-#define OMAP44XX_L2CACHE_BASE 0x48242000
-#define OMAP44XX_WKUPGEN_BASE 0x48281000
-#define OMAP44XX_MCPDM_BASE 0x40132000
-#define OMAP44XX_MCPDM_L3_BASE 0x49032000
-#define OMAP44XX_SAR_RAM_BASE 0x4a326000
-
-#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
-#define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000)
-
-#define OMAP4_MMU1_BASE 0x55082000
-#define OMAP4_MMU2_BASE 0x4A066000
-
-#define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000)
-#define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000)
-#define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800)
-#define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00)
-
-#endif /* __ASM_ARCH_OMAP44XX_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
deleted file mode 100644
index a2582bb3cab3..000000000000
--- a/arch/arm/plat-omap/include/plat/omap54xx.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*:
- * Address mappings and base address for OMAP5 interconnects
- * and peripherals.
- *
- * Copyright (C) 2012 Texas Instruments
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Sricharan <r.sricharan@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_SOC_OMAP54XX_H
-#define __ASM_SOC_OMAP54XX_H
-
-/*
- * Please place only base defines here and put the rest in device
- * specific headers.
- */
-#define L4_54XX_BASE 0x4a000000
-#define L4_WK_54XX_BASE 0x4ae00000
-#define L4_PER_54XX_BASE 0x48000000
-#define L3_54XX_BASE 0x44000000
-#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
-#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
-#define OMAP54XX_CM_CORE_BASE 0x4a008000
-#define OMAP54XX_PRM_BASE 0x4ae06000
-#define OMAP54XX_PRCM_MPU_BASE 0x48243000
-#define OMAP54XX_SCM_BASE 0x4a002000
-#define OMAP54XX_CTRL_BASE 0x4a002800
-
-#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
deleted file mode 100644
index 48e4757e1e30..000000000000
--- a/arch/arm/plat-omap/include/plat/omap7xx.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap7xx.h
- *
- * Hardware definitions for TI OMAP7XX processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
- * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP7XX_H
-#define __ASM_ARCH_OMAP7XX_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP7XX_DSP_BASE 0xE0000000
-#define OMAP7XX_DSP_SIZE 0x50000
-#define OMAP7XX_DSP_START 0xE0000000
-
-#define OMAP7XX_DSPREG_BASE 0xE1000000
-#define OMAP7XX_DSPREG_SIZE SZ_128K
-#define OMAP7XX_DSPREG_START 0xE1000000
-
-#define OMAP7XX_SPI1_BASE 0xfffc0800
-#define OMAP7XX_SPI2_BASE 0xfffc1000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_CONFIG_BASE 0xfffe1000
-#define OMAP7XX_IO_CONF_0 0xfffe1070
-#define OMAP7XX_IO_CONF_1 0xfffe1074
-#define OMAP7XX_IO_CONF_2 0xfffe1078
-#define OMAP7XX_IO_CONF_3 0xfffe107c
-#define OMAP7XX_IO_CONF_4 0xfffe1080
-#define OMAP7XX_IO_CONF_5 0xfffe1084
-#define OMAP7XX_IO_CONF_6 0xfffe1088
-#define OMAP7XX_IO_CONF_7 0xfffe108c
-#define OMAP7XX_IO_CONF_8 0xfffe1090
-#define OMAP7XX_IO_CONF_9 0xfffe1094
-#define OMAP7XX_IO_CONF_10 0xfffe1098
-#define OMAP7XX_IO_CONF_11 0xfffe109c
-#define OMAP7XX_IO_CONF_12 0xfffe10a0
-#define OMAP7XX_IO_CONF_13 0xfffe10a4
-
-#define OMAP7XX_MODE_1 0xfffe1010
-#define OMAP7XX_MODE_2 0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP7XX_MODE2_OFFSET 0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_FLASH_CFG_0 0xfffecc10
-#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
-#define OMAP7XX_FLASH_CFG_1 0xfffecc14
-#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_ICR_BASE 0xfffbb800
-#define OMAP7XX_DSP_M_CTL 0xfffbb804
-#define OMAP7XX_DSP_MMU_BASE 0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP7XX PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
-#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /* __ASM_ARCH_OMAP7XX_H */
-
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
deleted file mode 100644
index 2858667d2e4f..000000000000
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/onenand.h
- *
- * Copyright (C) 2006 Nokia Corporation
- * Author: Juha Yrjola
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
-#define ONENAND_SYNC_READ (1 << 0)
-#define ONENAND_SYNC_READWRITE (1 << 1)
-
-struct onenand_freq_info {
- u16 maf_id;
- u16 dev_id;
- u16 ver_id;
-};
-
-struct omap_onenand_platform_data {
- int cs;
- int gpio_irq;
- struct mtd_partition *parts;
- int nr_parts;
- int (*onenand_setup)(void __iomem *, int *freq_ptr);
- int (*get_freq)(const struct onenand_freq_info *freq_info,
- bool *clk_dep);
- int dma_channel;
- u8 flags;
- u8 regulator_can_sleep;
- u8 skip_initial_unlocking;
-};
-
-#define ONENAND_MAX_PARTITIONS 8
-
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
- defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
-
-extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
-
-#else
-
-#define board_onenand_data NULL
-
-static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
-{
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
deleted file mode 100644
index 1eb4dc326979..000000000000
--- a/arch/arm/plat-omap/include/plat/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/param.h
- *
- */
-
-#ifdef CONFIG_OMAP_32K_TIMER_HZ
-#define HZ CONFIG_OMAP_32K_TIMER_HZ
-#endif
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
deleted file mode 100644
index b10eac89e2e9..000000000000
--- a/arch/arm/plat-omap/include/plat/remoteproc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Remote Processor - omap-specific bits
- *
- * Copyright (C) 2011 Texas Instruments, Inc.
- * Copyright (C) 2011 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PLAT_REMOTEPROC_H
-#define _PLAT_REMOTEPROC_H
-
-struct rproc_ops;
-struct platform_device;
-
-/*
- * struct omap_rproc_pdata - omap remoteproc's platform data
- * @name: the remoteproc's name
- * @oh_name: omap hwmod device
- * @oh_name_opt: optional, secondary omap hwmod device
- * @firmware: name of firmware file to load
- * @mbox_name: name of omap mailbox device to use with this rproc
- * @ops: start/stop rproc handlers
- * @device_enable: omap-specific handler for enabling a device
- * @device_shutdown: omap-specific handler for shutting down a device
- */
-struct omap_rproc_pdata {
- const char *name;
- const char *oh_name;
- const char *oh_name_opt;
- const char *firmware;
- const char *mbox_name;
- const struct rproc_ops *ops;
- int (*device_enable) (struct platform_device *pdev);
- int (*device_shutdown) (struct platform_device *pdev);
-};
-
-#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
-
-void __init omap_rproc_reserve_cma(void);
-
-#else
-
-void __init omap_rproc_reserve_cma(void)
-{
-}
-
-#endif
-
-#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/ti81xx.h b/arch/arm/plat-omap/include/plat/ti81xx.h
deleted file mode 100644
index 8f9843f78422..000000000000
--- a/arch/arm/plat-omap/include/plat/ti81xx.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file contains the address data for various TI81XX modules.
- *
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_TI81XX_H
-#define __ASM_ARCH_TI81XX_H
-
-#define L4_SLOW_TI81XX_BASE 0x48000000
-
-#define TI81XX_SCM_BASE 0x48140000
-#define TI81XX_CTRL_BASE TI81XX_SCM_BASE
-#define TI81XX_PRCM_BASE 0x48180000
-
-#define TI81XX_ARM_INTC_BASE 0x48200000
-
-#endif /* __ASM_ARCH_TI81XX_H */
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 548a4c8d63df..bd20588c356b 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -5,7 +5,6 @@
#include <linux/io.h>
#include <linux/usb/musb.h>
-#include <plat/board.h>
#define OMAP3_HS_USB_PORTS 3
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
deleted file mode 100644
index 5be4d5def427..000000000000
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * OMAP Voltage Management Routines
- *
- * Copyright (C) 2011, Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
-#define __ARCH_ARM_OMAP_VOLTAGE_H
-
-/**
- * struct omap_volt_data - Omap voltage specific data.
- * @voltage_nominal: The possible voltage value in uV
- * @sr_efuse_offs: The offset of the efuse register(from system
- * control module base address) from where to read
- * the n-target value for the smartreflex module.
- * @sr_errminlimit: Error min limit value for smartreflex. This value
- * differs at differnet opp and thus is linked
- * with voltage.
- * @vp_errorgain: Error gain value for the voltage processor. This
- * field also differs according to the voltage/opp.
- */
-struct omap_volt_data {
- u32 volt_nominal;
- u32 sr_efuse_offs;
- u8 sr_errminlimit;
- u8 vp_errgain;
-};
-struct voltagedomain;
-
-struct voltagedomain *voltdm_lookup(const char *name);
-int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
-unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
-struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
- unsigned long volt);
-#endif
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
deleted file mode 100644
index cff8712122bb..000000000000
--- a/arch/arm/plat-omap/mux.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/mux.c
- *
- * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h
- *
- * Copyright (C) 2003 - 2008 Nokia Corporation
- *
- * Written by Tony Lindgren
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#include <asm/system.h>
-
-#include <plat/cpu.h>
-#include <plat/mux.h>
-
-#ifdef CONFIG_OMAP_MUX
-
-static struct omap_mux_cfg *mux_cfg;
-
-int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
-{
- if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
- || !arch_mux_cfg->cfg_reg) {
- printk(KERN_ERR "Invalid pin table\n");
- return -EINVAL;
- }
-
- mux_cfg = arch_mux_cfg;
-
- return 0;
-}
-
-/*
- * Sets the Omap MUX and PULL_DWN registers based on the table
- */
-int __init_or_module omap_cfg_reg(const unsigned long index)
-{
- struct pin_config *reg;
-
- if (!cpu_class_is_omap1()) {
- printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
- index);
- WARN_ON(1);
- return -EINVAL;
- }
-
- if (mux_cfg == NULL) {
- printk(KERN_ERR "Pin mux table not initialized\n");
- return -ENODEV;
- }
-
- if (index >= mux_cfg->size) {
- printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
- index, mux_cfg->size);
- dump_stack();
- return -ENODEV;
- }
-
- reg = (struct pin_config *)&mux_cfg->pins[index];
-
- if (!mux_cfg->cfg_reg)
- return -ENODEV;
-
- return mux_cfg->cfg_reg(reg);
-}
-EXPORT_SYMBOL(omap_cfg_reg);
-#else
-#define omap_mux_init() do {} while(0)
-#define omap_cfg_reg(x) do {} while(0)
-#endif /* CONFIG_OMAP_MUX */
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 5a97b4d98d41..9f6413324df9 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -41,11 +41,11 @@ int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
};
if (t == -1)
- pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the MPU to a
@@ -70,11 +70,10 @@ int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
};
if (r == 0)
- pr_debug("OMAP PM: remove min bus tput constraint: "
- "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+ pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
+ dev_name(dev), agent_id);
else
- pr_debug("OMAP PM: add min bus tput constraint: "
- "dev %s for agent_id %d: rate %ld KiB\n",
+ pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
dev_name(dev), agent_id, r);
/*
@@ -97,11 +96,11 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
};
if (t == -1)
- pr_debug("OMAP PM: remove max device latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max device latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the device to a
@@ -127,11 +126,11 @@ int omap_pm_set_max_sdma_lat(struct device *dev, long t)
};
if (t == -1)
- pr_debug("OMAP PM: remove max DMA latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max DMA latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@ int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
}
if (r == 0)
- pr_debug("OMAP PM: remove min clk rate constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add min clk rate constraint: "
- "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+ pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
+ dev_name(dev), r);
/*
* Code in a real implementation should keep track of these
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240bb82c..b59edb065c70 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
-
/*
* omap_device implementation
*
@@ -153,21 +152,19 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
act_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: activate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, act_lat);
+ "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
+ od->pm_lat_level, act_lat);
if (act_lat > odpl->activate_lat) {
odpl->activate_lat_worst = act_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->activate_lat = act_lat;
dev_dbg(&od->pdev->dev,
- "new worst case activate latency "
- "%d: %llu\n",
+ "new worst case activate latency %d: %llu\n",
od->pm_lat_level, act_lat);
} else
dev_warn(&od->pdev->dev,
- "activate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "activate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, act_lat,
odpl->activate_lat);
}
@@ -220,21 +217,19 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
deact_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: deactivate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, deact_lat);
+ "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
+ od->pm_lat_level, deact_lat);
if (deact_lat > odpl->deactivate_lat) {
odpl->deactivate_lat_worst = deact_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->deactivate_lat = deact_lat;
dev_dbg(&od->pdev->dev,
- "new worst case deactivate latency "
- "%d: %llu\n",
+ "new worst case deactivate latency %d: %llu\n",
od->pm_lat_level, deact_lat);
} else
dev_warn(&od->pdev->dev,
- "deactivate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "deactivate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, deact_lat,
odpl->deactivate_lat);
}
@@ -449,8 +444,8 @@ static int omap_device_count_resources(struct omap_device *od)
for (i = 0; i < od->hwmods_cnt; i++)
c += omap_hwmod_count_resources(od->hwmods[i]);
- pr_debug("omap_device: %s: counted %d total resources across %d "
- "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+ pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
+ od->pdev->name, c, od->hwmods_cnt);
return c;
}
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 024f3b08db29..28acb383e7df 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -26,7 +26,6 @@
#include <asm/mach/map.h>
#include <plat/sram.h>
-#include <plat/board.h>
#include <plat/cpu.h>
#include "sram.h"