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| author | Paolo Bonzini <pbonzini@redhat.com> | 2019-11-21 10:01:51 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2019-11-21 12:03:40 +0100 |
| commit | 46f4f0aabc61bfd365e1eb3c8a6d766d1a49cf32 (patch) | |
| tree | f98a256ff3e4b20ca6252f7f80ce17759e57c6f2 /Documentation/devicetree/bindings/riscv/cpus.yaml | |
| parent | 14edff88315add29099fd8eebb9ef989c2e47c18 (diff) | |
| parent | b07a5c53d42a8c87b208614129e947dd2338ff9c (diff) | |
Merge branch 'kvm-tsx-ctrl' into HEAD
Conflicts:
arch/x86/kvm/vmx/vmx.c
Diffstat (limited to 'Documentation/devicetree/bindings/riscv/cpus.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index b261a3015f84..04819ad379c2 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -24,15 +24,17 @@ description: | properties: compatible: - items: - - enum: - - sifive,rocket0 - - sifive,e5 - - sifive,e51 - - sifive,u54-mc - - sifive,u54 - - sifive,u5 - - const: riscv + oneOf: + - items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart. @@ -66,12 +68,8 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. - timebase-frequency: - type: integer - minimum: 1 - description: - Specifies the clock frequency of the system timer in Hz. - This value is common to all harts on a single system image. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here + timebase-frequency: false interrupt-controller: type: object @@ -93,7 +91,6 @@ properties: required: - riscv,isa - - timebase-frequency - interrupt-controller examples: |