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authorMichal Wajdeczko <michal.wajdeczko@intel.com>2018-09-10 13:43:01 +0200
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2018-10-16 12:43:29 +0100
commitff4976b36dade4c4a75d776a3cfe283fdb45ab38 (patch)
tree695d0b42c2b61ecc35bb1a40d8a4b8c454c996f2
parentf9ddefcba4896c2ffc5baf1bde1eab0882242685 (diff)
drm/i915/guc: Simplify preparation of GuC parameter block
Definition of the parameters block passed to GuC is about to change. Slightly refactor code now to make upcoming patch smaller. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: John Spotswood <john.a.spotswood@intel.com> Reviewed-by: John Spotswood <john.a.spotswood@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_guc.c38
1 files changed, 23 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 230aea69385d..982bcc86f222 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -320,19 +320,8 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
return flags;
}
-/*
- * Initialise the GuC parameter block before starting the firmware
- * transfer. These parameters are read by the firmware on startup
- * and cannot be changed thereafter.
- */
-void intel_guc_init_params(struct intel_guc *guc)
+static void guc_prepare_params(struct intel_guc *guc, u32 *params)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 params[GUC_CTL_MAX_DWORDS];
- int i;
-
- memset(params, 0, sizeof(params));
-
/*
* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
* second. This ARAR is calculated by:
@@ -347,9 +336,12 @@ void intel_guc_init_params(struct intel_guc *guc)
params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+}
- for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+static void guc_write_params(struct intel_guc *guc, const u32 *params)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int i;
/*
* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
@@ -360,12 +352,28 @@ void intel_guc_init_params(struct intel_guc *guc)
I915_WRITE(SOFT_SCRATCH(0), 0);
- for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
+ for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) {
+ DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
+ }
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
}
+/*
+ * Initialise the GuC parameter block before starting the firmware
+ * transfer. These parameters are read by the firmware on startup
+ * and cannot be changed thereafter.
+ */
+void intel_guc_init_params(struct intel_guc *guc)
+{
+ u32 params[GUC_CTL_MAX_DWORDS];
+
+ memset(params, 0, sizeof(params));
+ guc_prepare_params(guc, params);
+ guc_write_params(guc, params);
+}
+
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
u32 *response_buf, u32 response_buf_size)
{